From 2b9a0c32479c78620adaed7e2e5ff1a487abf694 Mon Sep 17 00:00:00 2001 From: Kai Jan Kriegel Date: Mon, 23 Jan 2023 03:23:03 +0100 Subject: [PATCH] commit blob of doom --- Software/fab-reader2-c/.gitignore | 102 + Software/fab-reader2-c/CMakeLists.txt | 11 + .../components/rfal/CMakeLists.txt | 14 + .../components/rfal/Inc/rfal_analogConfig.h | 334 + .../rfal/Inc/rfal_analogConfigTbl.h | 426 + .../components/rfal/Inc/rfal_chip.h | 296 + .../components/rfal/Inc/rfal_crc.h | 75 + .../components/rfal/Inc/rfal_dpo.h | 209 + .../components/rfal/Inc/rfal_dpoTbl.h | 56 + .../components/rfal/Inc/rfal_features.h | 115 + .../components/rfal/Inc/rfal_iso15693_2.h | 202 + .../components/rfal/Inc/rfal_isoDep.h | 866 + .../components/rfal/Inc/rfal_nfc.h | 406 + .../components/rfal/Inc/rfal_nfcDep.h | 700 + .../components/rfal/Inc/rfal_nfca.h | 391 + .../components/rfal/Inc/rfal_nfcb.h | 398 + .../components/rfal/Inc/rfal_nfcf.h | 370 + .../components/rfal/Inc/rfal_nfcv.h | 772 + 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Software/fab-reader2/st25r3911b/src/device/mod.rs create mode 100644 Software/fab-reader2/st25r3911b/src/device/nfca.rs create mode 100644 Software/fab-reader2/st25r3911b/src/rf.rs create mode 100644 Waveforms/default.txt create mode 100644 Waveforms/esp32.dwf3logicacq create mode 100644 Waveforms/st25r3911b_commandparser/.idea/.gitignore create mode 100644 Waveforms/st25r3911b_commandparser/.idea/st25r3911b_commandparser.iml create mode 100644 Waveforms/st25r3911b_commandparser/README.md create mode 100644 Waveforms/st25r3911b_commandparser/main.py create mode 100644 Waveforms/st25r3911b_commandparser/requirements.txt create mode 100644 Waveforms/stm32.dwf3logicacq create mode 100644 Waveforms/stm32.dwf3work diff --git a/Software/fab-reader2-c/.gitignore b/Software/fab-reader2-c/.gitignore new file mode 100644 index 0000000..ae9a17b --- /dev/null +++ b/Software/fab-reader2-c/.gitignore @@ -0,0 +1,102 @@ +.config +*.o +*.pyc + +# gtags +GTAGS +GRTAGS +GPATH + +# emacs +.dir-locals.el + +# emacs temp file suffixes +*~ +.#* +\#*# + +# eclipse setting +.settings + +# MacOS directory files +.DS_Store + +# cache dir +.cache/ + +# Components Unit Test Apps files +components/**/build/ +components/**/build_*_*/ +components/**/sdkconfig +components/**/sdkconfig.old + +# Example project files +examples/**/build/ +examples/**/build_esp*_*/ +examples/**/sdkconfig +examples/**/sdkconfig.old + +# Doc build artifacts +docs/_build/ +docs/doxygen_sqlite3.db + +# Downloaded font files +docs/_static/DejaVuSans.ttf +docs/_static/NotoSansSC-Regular.otf + +# Unit test app files +tools/unit-test-app/sdkconfig +tools/unit-test-app/sdkconfig.old +tools/unit-test-app/build +tools/unit-test-app/build_*_*/ +tools/unit-test-app/output +tools/unit-test-app/test_configs + +# Unit Test CMake compile log folder +log_ut_cmake + +# test application build files +tools/test_apps/**/build/ +tools/test_apps/**/build_*_*/ +tools/test_apps/**/sdkconfig +tools/test_apps/**/sdkconfig.old + +# IDF monitor test +tools/test_idf_monitor/outputs + +TEST_LOGS + +# gcov coverage reports +*.gcda +*.gcno +coverage.info +coverage_report/ + +test_multi_heap_host + +# VS Code Settings +.vscode/ + +# VIM files +*.swp +*.swo + +# Clion IDE CMake build & config +.idea/ +cmake-build-*/ + +# Results for the checking of the Python coding style and static analysis +.mypy_cache +flake8_output.txt + +# ESP-IDF default build directory name +build + +# lock files for examples and components +dependencies.lock + +# managed_components for examples +managed_components + +# pytest log +pytest_embedded_log/ diff --git a/Software/fab-reader2-c/CMakeLists.txt b/Software/fab-reader2-c/CMakeLists.txt new file mode 100644 index 0000000..a38c955 --- /dev/null +++ b/Software/fab-reader2-c/CMakeLists.txt @@ -0,0 +1,11 @@ +# For more information about build system see +# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html +# The following five lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(fab-reader2-c) + +set(COMPONENTS main) +#list(SET COMPONENTS "mqtt") diff --git a/Software/fab-reader2-c/components/rfal/CMakeLists.txt b/Software/fab-reader2-c/components/rfal/CMakeLists.txt new file mode 100644 index 0000000..26b4e4c --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/CMakeLists.txt @@ -0,0 +1,14 @@ +idf_component_register(SRCS "Src/rfal_nfc.c" + "Src/rfal_analogConfig.c" + "Src/rfal_crc.c" + "Src/rfal_dpo.c" + "Src/rfal_iso15693_2.c" + "Src/rfal_isoDep.c" + "Src/rfal_nfca.c" + "Src/rfal_nfcb.c" + "Src/rfal_rfst25r3911.c" + "Src/rfal_t1t.c" + "Src/rfal_t2t.c" + "Src/rfal_t4t.c" + INCLUDE_DIRS "Inc" + REQUIRES "st25r3911") diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_analogConfig.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_analogConfig.h new file mode 100644 index 0000000..6da5de9 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_analogConfig.h @@ -0,0 +1,334 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_AnalogConfig.h + * + * \author bkam + * + * \brief RF Chip Analog Configuration Settings + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-HAL + * \brief RFAL Hardware Abstraction Layer + * @{ + * + * \addtogroup AnalogConfig + * \brief RFAL Analog Config Module + * @{ + * + */ + +#ifndef RFAL_ANALOG_CONFIG_H +#define RFAL_ANALOG_CONFIG_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" + +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ + +#define RFAL_ANALOG_CONFIG_LUT_SIZE (87U) /*!< Maximum number of Configuration IDs in the Loop Up Table */ +#define RFAL_ANALOG_CONFIG_LUT_NOT_FOUND (0xFFU) /*!< Index value indicating no Configuration IDs found */ + +#define RFAL_ANALOG_CONFIG_TBL_SIZE (1024U) /*!< Maximum number of Register-Mask-Value in the Setting List */ + + +#define RFAL_ANALOG_CONFIG_POLL_LISTEN_MODE_MASK (0x8000U) /*!< Mask bit of Poll Mode in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_TECH_MASK (0x7F00U) /*!< Mask bits for Technology in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_MASK (0x00F0U) /*!< Mask bits for Bit rate in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_DIRECTION_MASK (0x0003U) /*!< Mask bits for Direction in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_CHIP_SPECIFIC_MASK (0x00FFU) /*!< Mask bits for Chip Specific Technology */ + +#define RFAL_ANALOG_CONFIG_POLL_LISTEN_MODE_SHIFT (15U) /*!< Shift value of Poll Mode in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_TECH_SHIFT (8U) /*!< Shift value for Technology in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_SHIFT (4U) /*!< Shift value for Technology in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_DIRECTION_SHIFT (0U) /*!< Shift value for Direction in Analog Configuration ID */ + +#define RFAL_ANALOG_CONFIG_POLL (0x0000U) /*!< Poll Mode bit setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_LISTEN (0x8000U) /*!< Listen Mode bit setting in Analog Configuration ID */ + +#define RFAL_ANALOG_CONFIG_TECH_CHIP (0x0000U) /*!< Chip-Specific bit setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_TECH_NFCA (0x0100U) /*!< NFC-A Technology bits setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_TECH_NFCB (0x0200U) /*!< NFC-B Technology bits setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_TECH_NFCF (0x0400U) /*!< NFC-F Technology bits setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_TECH_AP2P (0x0800U) /*!< AP2P Technology bits setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_TECH_NFCV (0x1000U) /*!< NFC-V Technology bits setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_TECH_RFU (0x2000U) /*!< RFU for Technology bits */ + +#define RFAL_ANALOG_CONFIG_BITRATE_COMMON (0x0000U) /*!< Common settings for all bit rates in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_106 (0x0010U) /*!< 106kbits/s settings in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_212 (0x0020U) /*!< 212kbits/s settings in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_424 (0x0030U) /*!< 424kbits/s settings in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_848 (0x0040U) /*!< 848kbits/s settings in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_1695 (0x0050U) /*!< 1695kbits/s settings in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_3390 (0x0060U) /*!< 3390kbits/s settings in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_6780 (0x0070U) /*!< 6780kbits/s settings in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_1OF4 (0x00C0U) /*!< 1 out of 4 for NFC-V setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_BITRATE_1OF256 (0x00D0U) /*!< 1 out of 256 for NFC-V setting in Analog Configuration ID */ + +#define RFAL_ANALOG_CONFIG_NO_DIRECTION (0x0000U) /*!< No direction setting in Analog Conf ID (Chip Specific only) */ +#define RFAL_ANALOG_CONFIG_TX (0x0001U) /*!< Transmission bit setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_RX (0x0002U) /*!< Reception bit setting in Analog Configuration ID */ +#define RFAL_ANALOG_CONFIG_ANTICOL (0x0003U) /*!< Anticollision setting in Analog Configuration ID */ + +#define RFAL_ANALOG_CONFIG_CHIP_INIT (0x0000U) /*!< Chip-Specific event: Startup;Reset;Initialize */ +#define RFAL_ANALOG_CONFIG_CHIP_DEINIT (0x0001U) /*!< Chip-Specific event: Deinitialize */ +#define RFAL_ANALOG_CONFIG_CHIP_FIELD_ON (0x0002U) /*!< Chip-Specific event: Field On */ +#define RFAL_ANALOG_CONFIG_CHIP_FIELD_OFF (0x0003U) /*!< Chip-Specific event: Field Off */ +#define RFAL_ANALOG_CONFIG_CHIP_WAKEUP_ON (0x0004U) /*!< Chip-Specific event: Wake-up On */ +#define RFAL_ANALOG_CONFIG_CHIP_WAKEUP_OFF (0x0005U) /*!< Chip-Specific event: Wake-up Off */ +#define RFAL_ANALOG_CONFIG_CHIP_LISTEN_ON (0x0006U) /*!< Chip-Specific event: Listen On */ +#define RFAL_ANALOG_CONFIG_CHIP_LISTEN_OFF (0x0007U) /*!< Chip-Specific event: Listen Off */ +#define RFAL_ANALOG_CONFIG_CHIP_POLL_COMMON (0x0008U) /*!< Chip-Specific event: Poll common */ +#define RFAL_ANALOG_CONFIG_CHIP_LISTEN_COMMON (0x0009U) /*!< Chip-Specific event: Listen common */ + +#define RFAL_ANALOG_CONFIG_UPDATE_LAST (0x00U) /*!< Value indicating Last configuration set during update */ +#define RFAL_ANALOG_CONFIG_UPDATE_MORE (0x01U) /*!< Value indicating More configuration set coming during update */ + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + +#define RFAL_ANALOG_CONFIG_ID_GET_POLL_LISTEN(id) (RFAL_ANALOG_CONFIG_POLL_LISTEN_MODE_MASK & (id)) /*!< Check if id indicates Listen mode */ + +#define RFAL_ANALOG_CONFIG_ID_GET_TECH(id) (RFAL_ANALOG_CONFIG_TECH_MASK & (id)) /*!< Get the technology of Configuration ID */ +#define RFAL_ANALOG_CONFIG_ID_IS_CHIP(id) (RFAL_ANALOG_CONFIG_TECH_MASK & (id)) /*!< Check if ID indicates Chip-specific */ +#define RFAL_ANALOG_CONFIG_ID_IS_NFCA(id) (RFAL_ANALOG_CONFIG_TECH_NFCA & (id)) /*!< Check if ID indicates NFC-A */ +#define RFAL_ANALOG_CONFIG_ID_IS_NFCB(id) (RFAL_ANALOG_CONFIG_TECH_NFCB & (id)) /*!< Check if ID indicates NFC-B */ +#define RFAL_ANALOG_CONFIG_ID_IS_NFCF(id) (RFAL_ANALOG_CONFIG_TECH_NFCF & (id)) /*!< Check if ID indicates NFC-F */ +#define RFAL_ANALOG_CONFIG_ID_IS_AP2P(id) (RFAL_ANALOG_CONFIG_TECH_AP2P & (id)) /*!< Check if ID indicates AP2P */ +#define RFAL_ANALOG_CONFIG_ID_IS_NFCV(id) (RFAL_ANALOG_CONFIG_TECH_NFCV & (id)) /*!< Check if ID indicates NFC-V */ + +#define RFAL_ANALOG_CONFIG_ID_GET_BITRATE(id) (RFAL_ANALOG_CONFIG_BITRATE_MASK & (id)) /*!< Get Bitrate of Configuration ID */ +#define RFAL_ANALOG_CONFIG_ID_IS_COMMON(id) (RFAL_ANALOG_CONFIG_BITRATE_MASK & (id)) /*!< Check if ID indicates common bitrate */ +#define RFAL_ANALOG_CONFIG_ID_IS_106(id) (RFAL_ANALOG_CONFIG_BITRATE_106 & (id)) /*!< Check if ID indicates 106kbits/s */ +#define RFAL_ANALOG_CONFIG_ID_IS_212(id) (RFAL_ANALOG_CONFIG_BITRATE_212 & (id)) /*!< Check if ID indicates 212kbits/s */ +#define RFAL_ANALOG_CONFIG_ID_IS_424(id) (RFAL_ANALOG_CONFIG_BITRATE_424 & (id)) /*!< Check if ID indicates 424kbits/s */ +#define RFAL_ANALOG_CONFIG_ID_IS_848(id) (RFAL_ANALOG_CONFIG_BITRATE_848 & (id)) /*!< Check if ID indicates 848kbits/s */ +#define RFAL_ANALOG_CONFIG_ID_IS_1695(id) (RFAL_ANALOG_CONFIG_BITRATE_1695 & (id)) /*!< Check if ID indicates 1695kbits/s */ +#define RFAL_ANALOG_CONFIG_ID_IS_3390(id) (RFAL_ANALOG_CONFIG_BITRATE_3390 & (id)) /*!< Check if ID indicates 3390kbits/s */ +#define RFAL_ANALOG_CONFIG_ID_IS_6780(id) (RFAL_ANALOG_CONFIG_BITRATE_6780 & (id)) /*!< Check if ID indicates 6780kbits/s */ +#define RFAL_ANALOG_CONFIG_ID_IS_1OF4(id) (RFAL_ANALOG_CONFIG_BITRATE_1OF4 & (id)) /*!< Check if ID indicates 1 out of 4 bitrate */ +#define RFAL_ANALOG_CONFIG_ID_IS_1OF256(id) (RFAL_ANALOG_CONFIG_BITRATE_1OF256 & (id)) /*!< Check if ID indicates 1 out of 256 bitrate */ + +#define RFAL_ANALOG_CONFIG_ID_GET_DIRECTION(id) (RFAL_ANALOG_CONFIG_DIRECTION_MASK & (id)) /*!< Get Direction of Configuration ID */ +#define RFAL_ANALOG_CONFIG_ID_IS_TX(id) (RFAL_ANALOG_CONFIG_TX & (id)) /*!< Check if id indicates TX */ +#define RFAL_ANALOG_CONFIG_ID_IS_RX(id) (RFAL_ANALOG_CONFIG_RX & (id)) /*!< Check if id indicates RX */ + +#define RFAL_ANALOG_CONFIG_CONFIG_NUM(x) (sizeof(x)/sizeof((x)[0])) /*!< Get Analog Config number */ + +/*! Set Analog Config ID value by: Mode, Technology, Bitrate and Direction */ +#define RFAL_ANALOG_CONFIG_ID_SET(mode, tech, br, direction) \ + ( RFAL_ANALOG_CONFIG_ID_GET_POLL_LISTEN(mode) \ + | RFAL_ANALOG_CONFIG_ID_GET_TECH(tech) \ + | RFAL_ANALOG_CONFIG_ID_GET_BITRATE(br) \ + | RFAL_ANALOG_CONFIG_ID_GET_DIRECTION(direction) \ + ) + +/* + ****************************************************************************** + * GLOBAL DATA TYPES + ****************************************************************************** + */ + +typedef uint8_t rfalAnalogConfigMode; /*!< Polling or Listening Mode of Configuration */ +typedef uint8_t rfalAnalogConfigTech; /*!< Technology of Configuration */ +typedef uint8_t rfalAnalogConfigBitrate; /*!< Bitrate of Configuration */ +typedef uint8_t rfalAnalogConfigDirection; /*!< Transmit/Receive direction of Configuration */ + +typedef uint8_t rfalAnalogConfigRegAddr[2]; /*!< Register Address to ST Chip */ +typedef uint8_t rfalAnalogConfigRegMask; /*!< Register Mask Value */ +typedef uint8_t rfalAnalogConfigRegVal; /*!< Register Value */ + +typedef uint16_t rfalAnalogConfigId; /*!< Analog Configuration ID */ +typedef uint16_t rfalAnalogConfigOffset; /*!< Analog Configuration offset address in the table */ +typedef uint8_t rfalAnalogConfigNum; /*!< Number of Analog settings for the respective Configuration ID */ + + +/*! Struct that contain the Register-Mask-Value set. Make sure that the whole structure size is even and unaligned! */ +typedef struct { + rfalAnalogConfigRegAddr addr; /*!< Register Address */ + rfalAnalogConfigRegMask mask; /*!< Register Mask Value */ + rfalAnalogConfigRegVal val; /*!< Register Value */ +} rfalAnalogConfigRegAddrMaskVal; + + +/*! Struct that represents the Analog Configs */ +typedef struct { + uint8_t id[sizeof(rfalAnalogConfigId)]; /*!< Configuration ID */ + rfalAnalogConfigNum num; /*!< Number of Config Sets to follow */ + rfalAnalogConfigRegAddrMaskVal regSet[]; /*!< Register-Mask-Value sets */ /* PRQA S 1060 # MISRA 18.7 - Flexible Array Members are the only meaningful way of denoting a variable length input buffer which follows a fixed header structure. */ +} rfalAnalogConfig; + + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/*! + ***************************************************************************** + * \brief Initialize the Analog Configuration + * + * Reset the Analog Configuration LUT pointer to reference to default settings. + * + ***************************************************************************** + */ +void rfalAnalogConfigInitialize( void ); + + +/*! + ***************************************************************************** + * \brief Indicate if the current Analog Configuration Table is complete and ready to be used. + * + * \return true if current Analog Configuration Table is complete and ready to be used. + * \return false if current Analog Configuration Table is incomplete + * + ***************************************************************************** + */ +bool rfalAnalogConfigIsReady( void ); + +/*! + ***************************************************************************** + * \brief Write the whole Analog Configuration table in raw format + * + * Writes the Analog Configuration and Look Up Table with the given raw table + * + * NOTE: Function does not check the validity of the given Table contents + * + * \param[in] configTbl: location of config Table to be loaded + * \param[in] configTblSize: size of the config Table to be loaded + * + * \return ERR_NONE : if setting is updated + * \return ERR_PARAM : if configTbl is invalid + * \return ERR_NOMEM : if the given Table is bigger exceeds the max size + * \return ERR_REQUEST : if the update Configuration Id is disabled + * + ***************************************************************************** + */ +ReturnCode rfalAnalogConfigListWriteRaw( const uint8_t *configTbl, uint16_t configTblSize ); + +/*! + ***************************************************************************** + * \brief Write the Analog Configuration table with new analog settings. + * + * Writes the Analog Configuration and Look Up Table with the new list of register-mask-value + * and Configuration ID respectively. + * + * NOTE: Function does not check for the validity of the Register Address. + * + * \param[in] more: 0x00 indicates it is last Configuration ID settings; + * 0x01 indicates more Configuration ID setting(s) are coming. + * \param[in] *config: reference to the configuration list of current Configuraiton ID. + * + * \return ERR_PARAM : if Configuration ID or parameter is invalid + * \return ERR_NOMEM : if LUT is full + * \return ERR_REQUEST : if the update Configuration Id is disabled + * \return ERR_NONE : if setting is updated + * + ***************************************************************************** + */ +ReturnCode rfalAnalogConfigListWrite( uint8_t more, const rfalAnalogConfig *config ); + +/*! + ***************************************************************************** + * \brief Read the whole Analog Configuration table in raw format + * + * Reads the whole Analog Configuration Table in raw format + * + * \param[out] tblBuf: location to the buffer to place the Config Table + * \param[in] tblBufLen: length of the buffer to place the Config Table + * \param[out] configTblSize: Config Table size + * + * \return ERR_PARAM : if configTbl or configTblSize is invalid + * \return ERR_NOMEM : if configTblSize is not enough for the whole table + * \return ERR_NONE : if read is successful + * + ***************************************************************************** + */ +ReturnCode rfalAnalogConfigListReadRaw( uint8_t *tblBuf, uint16_t tblBufLen, uint16_t *configTblSize ); + +/*! + ***************************************************************************** + * \brief Read the Analog Configuration table. + * + * Read the Analog Configuration Table + * + * \param[in] configOffset: offset to the next Configuration ID in the List Table to be read. + * \param[out] more: 0x00 indicates it is last Configuration ID settings; + * 0x01 indicates more Configuration ID setting(s) are coming. + * \param[out] config: configuration id, number of configuration sets and register-mask-value sets + * \param[in] numConfig: the remaining configuration settings space available; + * + * \return ERR_NOMEM : if number of Configuration for respective Configuration ID is greater the the remaining configuration setting space available + * \return ERR_NONE : if read is successful + * + ***************************************************************************** + */ +ReturnCode rfalAnalogConfigListRead( rfalAnalogConfigOffset *configOffset, uint8_t *more, rfalAnalogConfig *config, rfalAnalogConfigNum numConfig ); + +/*! + ***************************************************************************** + * \brief Set the Analog settings of indicated Configuration ID. + * + * Update the chip with indicated analog settings of indicated Configuration ID. + * + * \param[in] configId: configuration ID + * + * \return ERR_PARAM if Configuration ID is invalid + * \return ERR_INTERNAL if error updating setting to chip + * \return ERR_NONE if new settings is applied to chip + * + ***************************************************************************** + */ +ReturnCode rfalSetAnalogConfig( rfalAnalogConfigId configId ); + + +#endif /* RFAL_ANALOG_CONFIG_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_analogConfigTbl.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_analogConfigTbl.h new file mode 100644 index 0000000..2c4d0a2 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_analogConfigTbl.h @@ -0,0 +1,426 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_analogConfig.h + * + * \author bkam + * + * \brief ST25R3911 Analog Configuration Settings + * + */ + +#ifndef ST25R3911_ANALOGCONFIG_H +#define ST25R3911_ANALOGCONFIG_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_analogConfig.h" +#include "st25r3911_com.h" + +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + +/*! Macro for Configuration Setting with only one register-mask-value set: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1] */ +#define MODE_ENTRY_1_REG(MODE, R0, M0, V0) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 1, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) + +/*! Macro for Configuration Setting with only two register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1] */ +#define MODE_ENTRY_2_REG(MODE, R0, M0, V0, R1, M1, V1) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 2, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) + +/*! Macro for Configuration Setting with only three register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_3_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 3, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + +/*! Macro for Configuration Setting with only four register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_4_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 4, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + +/*! Macro for Configuration Setting with only five register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_5_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 5, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + +/*! Macro for Configuration Setting with only six register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_6_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 6, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + , (uint8_t)((R5) >> 8), (uint8_t)((R5) & 0xFFU), (uint8_t)(M5), (uint8_t)(V5) \ + +/*! Macro for Configuration Setting with only seven register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_7_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 7, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + , (uint8_t)((R5) >> 8), (uint8_t)((R5) & 0xFFU), (uint8_t)(M5), (uint8_t)(V5) \ + , (uint8_t)((R6) >> 8), (uint8_t)((R6) & 0xFFU), (uint8_t)(M6), (uint8_t)(V6) \ + +/*! Macro for Configuration Setting with only eight register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_8_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 8, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + , (uint8_t)((R5) >> 8), (uint8_t)((R5) & 0xFFU), (uint8_t)(M5), (uint8_t)(V5) \ + , (uint8_t)((R6) >> 8), (uint8_t)((R6) & 0xFFU), (uint8_t)(M6), (uint8_t)(V6) \ + , (uint8_t)((R7) >> 8), (uint8_t)((R7) & 0xFFU), (uint8_t)(M7), (uint8_t)(V7) \ + +/*! Macro for Configuration Setting with only nine register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_9_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU), 9, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + , (uint8_t)((R5) >> 8), (uint8_t)((R5) & 0xFFU), (uint8_t)(M5), (uint8_t)(V5) \ + , (uint8_t)((R6) >> 8), (uint8_t)((R6) & 0xFFU), (uint8_t)(M6), (uint8_t)(V6) \ + , (uint8_t)((R7) >> 8), (uint8_t)((R7) & 0xFFU), (uint8_t)(M7), (uint8_t)(V7) \ + , (uint8_t)((R8) >> 8), (uint8_t)((R8) & 0xFFU), (uint8_t)(M8), (uint8_t)(V8) \ + +/*! Macro for Configuration Setting with only ten register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_10_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8, R9, M9, V9) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU),10, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + , (uint8_t)((R5) >> 8), (uint8_t)((R5) & 0xFFU), (uint8_t)(M5), (uint8_t)(V5) \ + , (uint8_t)((R6) >> 8), (uint8_t)((R6) & 0xFFU), (uint8_t)(M6), (uint8_t)(V6) \ + , (uint8_t)((R7) >> 8), (uint8_t)((R7) & 0xFFU), (uint8_t)(M7), (uint8_t)(V7) \ + , (uint8_t)((R8) >> 8), (uint8_t)((R8) & 0xFFU), (uint8_t)(M8), (uint8_t)(V8) \ + , (uint8_t)((R9) >> 8), (uint8_t)((R9) & 0xFFU), (uint8_t)(M9), (uint8_t)(V9) \ + +/*! Macro for Configuration Setting with eleven register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_11_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8, R9, M9, V9, R10, M10, V10) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU),11, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + , (uint8_t)((R5) >> 8), (uint8_t)((R5) & 0xFFU), (uint8_t)(M5), (uint8_t)(V5) \ + , (uint8_t)((R6) >> 8), (uint8_t)((R6) & 0xFFU), (uint8_t)(M6), (uint8_t)(V6) \ + , (uint8_t)((R7) >> 8), (uint8_t)((R7) & 0xFFU), (uint8_t)(M7), (uint8_t)(V7) \ + , (uint8_t)((R8) >> 8), (uint8_t)((R8) & 0xFFU), (uint8_t)(M8), (uint8_t)(V8) \ + , (uint8_t)((R9) >> 8), (uint8_t)((R9) & 0xFFU), (uint8_t)(M9), (uint8_t)(V9) \ + , (uint8_t)((R10) >> 8), (uint8_t)((R10) & 0xFFU), (uint8_t)(M10), (uint8_t)(V10) \ + +/*! Macro for Configuration Setting with twelve register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_12_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8, R9, M9, V9, R10, M10, V10, R11, M11, V11) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU),12, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + , (uint8_t)((R5) >> 8), (uint8_t)((R5) & 0xFFU), (uint8_t)(M5), (uint8_t)(V5) \ + , (uint8_t)((R6) >> 8), (uint8_t)((R6) & 0xFFU), (uint8_t)(M6), (uint8_t)(V6) \ + , (uint8_t)((R7) >> 8), (uint8_t)((R7) & 0xFFU), (uint8_t)(M7), (uint8_t)(V7) \ + , (uint8_t)((R8) >> 8), (uint8_t)((R8) & 0xFFU), (uint8_t)(M8), (uint8_t)(V8) \ + , (uint8_t)((R9) >> 8), (uint8_t)((R9) & 0xFFU), (uint8_t)(M9), (uint8_t)(V9) \ + , (uint8_t)((R10) >> 8), (uint8_t)((R10) & 0xFFU), (uint8_t)(M10), (uint8_t)(V10) \ + , (uint8_t)((R11) >> 8), (uint8_t)((R11) & 0xFFU), (uint8_t)(M11), (uint8_t)(V11) \ + +/*! Macro for Configuration Setting with thirteen register-mask-value sets: + * - Configuration ID[2], Number of Register sets to follow[1], Register[2], Mask[1], Value[1], Register[2], Mask[1], Value[1], Register[2]... */ +#define MODE_ENTRY_13_REG(MODE, R0, M0, V0, R1, M1, V1, R2, M2, V2, R3, M3, V3, R4, M4, V4, R5, M5, V5, R6, M6, V6, R7, M7, V7, R8, M8, V8, R9, M9, V9, R10, M10, V10, R11, M11, V11, R12, M12, V12) \ + (uint8_t)((MODE) >> 8), (uint8_t)((MODE) & 0xFFU),13, (uint8_t)((R0) >> 8), (uint8_t)((R0) & 0xFFU), (uint8_t)(M0), (uint8_t)(V0) \ + , (uint8_t)((R1) >> 8), (uint8_t)((R1) & 0xFFU), (uint8_t)(M1), (uint8_t)(V1) \ + , (uint8_t)((R2) >> 8), (uint8_t)((R2) & 0xFFU), (uint8_t)(M2), (uint8_t)(V2) \ + , (uint8_t)((R3) >> 8), (uint8_t)((R3) & 0xFFU), (uint8_t)(M3), (uint8_t)(V3) \ + , (uint8_t)((R4) >> 8), (uint8_t)((R4) & 0xFFU), (uint8_t)(M4), (uint8_t)(V4) \ + , (uint8_t)((R5) >> 8), (uint8_t)((R5) & 0xFFU), (uint8_t)(M5), (uint8_t)(V5) \ + , (uint8_t)((R6) >> 8), (uint8_t)((R6) & 0xFFU), (uint8_t)(M6), (uint8_t)(V6) \ + , (uint8_t)((R7) >> 8), (uint8_t)((R7) & 0xFFU), (uint8_t)(M7), (uint8_t)(V7) \ + , (uint8_t)((R8) >> 8), (uint8_t)((R8) & 0xFFU), (uint8_t)(M8), (uint8_t)(V8) \ + , (uint8_t)((R9) >> 8), (uint8_t)((R9) & 0xFFU), (uint8_t)(M9), (uint8_t)(V9) \ + , (uint8_t)((R10) >> 8), (uint8_t)((R10) & 0xFFU), (uint8_t)(M10), (uint8_t)(V10) \ + , (uint8_t)((R11) >> 8), (uint8_t)((R11) & 0xFFU), (uint8_t)(M11), (uint8_t)(V11) \ + , (uint8_t)((R12) >> 8), (uint8_t)((R12) & 0xFFU), (uint8_t)(M12), (uint8_t)(V12) \ + +/* Setting for approximately 14%: */ +#define AM_MOD_DRIVER_LEVEL_DEFAULT 0xb9 +/* + ****************************************************************************** + * GLOBAL DATA TYPES + ****************************************************************************** + */ +/* PRQA S 3406 1 # MISRA 8.6 - Externally generated table included by the library */ /* PRQA S 1514 1 # MISRA 8.9 - Externally generated table included by the library */ + const uint8_t rfalAnalogConfigDefaultSettings[] = { + //****** Default Analog Configuration for Chip-Specific Reset. ******/ + MODE_ENTRY_10_REG( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_INIT) + , ST25R3911_REG_OP_CONTROL, 0x30, 0x10 /* default to AM */ + , ST25R3911_REG_IO_CONF1, 0x06, 0x06 /* MCUCLK: HF clk off */ + , ST25R3911_REG_IO_CONF1, (ST25R3911_REG_IO_CONF1_mask_out_cl | ST25R3911_REG_IO_CONF1_lf_clk_off), 0x07 /* MCUCLK: LF clk off */ + , ST25R3911_REG_IO_CONF2, 0x18, 0x18 /* pull downs */ + , ST25R3911_REG_RX_CONF4, ST25R3911_REG_RX_CONF4_mask_rg2_pm, 0x1U<
© COPYRIGHT 2016 STMicroelectronics
+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_chip.h + * + * \author Gustavo Patricio + * + * \brief RF Chip specific Layer + * + * \warning This layer, which provides direct access to RF chip, should + * only be used for debug purposes and/or advanced features + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-HAL + * \brief RFAL Hardware Abstraction Layer + * @{ + * + * \addtogroup Chip + * \brief RFAL RF Chip Module + * @{ + * + */ + + +#ifndef RFAL_CHIP_H +#define RFAL_CHIP_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" + + +/***************************************************************************** + * RF Chip * + *****************************************************************************/ + +/*! + ***************************************************************************** + * \brief Writes a register on the RF Chip + * + * Checks if the given register is valid and if so, writes the value(s) + * on the RF Chip register + * + * \param[in] reg: register address to be written, or the first if len > 1 + * \param[in] values: pointer with content to be written on the register(s) + * \param[in] len: number of consecutive registers to be written + * + * + * \return ERR_PARAM : Invalid register or bad request + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : Write done with no error + ***************************************************************************** + */ +ReturnCode rfalChipWriteReg( uint16_t reg, const uint8_t* values, uint8_t len ); + +/*! + ***************************************************************************** + * \brief Reads a register on the RF Chip + * + * Checks if the given register is valid and if so, reads the value(s) + * of the RF Chip register(s) + * + * \param[in] reg: register address to be read, or the first if len > 1 + * \param[out] values: pointer where the register(s) read content will be placed + * \param[in] len: number of consecutive registers to be read + * + * \return ERR_PARAM : Invalid register or bad request + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : Read done with no error + ***************************************************************************** + */ +ReturnCode rfalChipReadReg( uint16_t reg, uint8_t* values, uint8_t len ); + +/*! + ***************************************************************************** + * \brief Change a register on the RF Chip + * + * Change the value of the register bits on the RF Chip Test set in the valueMask. + * + * \param[in] reg: register address to be modified + * \param[in] valueMask: mask value of the register bits to be changed + * \param[in] value: register value to be set + * + * \return ERR_PARAM : Invalid register or bad request + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_OK : Change done with no error + ***************************************************************************** + */ +ReturnCode rfalChipChangeRegBits( uint16_t reg, uint8_t valueMask, uint8_t value ); + +/*! + ***************************************************************************** + * \brief Writes a Test register on the RF Chip + * + * Writes the value on the RF Chip Test register + * + * \param[in] reg: register address to be written + * \param[in] value: value to be written on the register + * + * + * \return ERR_PARAM : Invalid register or bad request + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : Write done with no error + ***************************************************************************** + */ +ReturnCode rfalChipWriteTestReg( uint16_t reg, uint8_t value ); + +/*! + ***************************************************************************** + * \brief Reads a Test register on the RF Chip + * + * Reads the value of the RF Chip Test register + * + * \param[in] reg: register address to be read + * \param[out] value: pointer where the register content will be placed + * + * \return ERR_PARAM :Invalid register or bad request + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : Read done with no error + ***************************************************************************** + */ +ReturnCode rfalChipReadTestReg( uint16_t reg, uint8_t* value ); + +/*! + ***************************************************************************** + * \brief Change a Test register on the RF Chip + * + * Change the value of the register bits on the RF Chip Test set in the valueMask. + * + * \param[in] reg: test register address to be modified + * \param[in] valueMask: mask value of the register bits to be changed + * \param[in] value: register value to be set + * + * \return ERR_PARAM : Invalid register or bad request + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_OK : Change done with no error + ***************************************************************************** + */ +ReturnCode rfalChipChangeTestRegBits( uint16_t reg, uint8_t valueMask, uint8_t value ); + +/*! + ***************************************************************************** + * \brief Execute command on the RF Chip + * + * Checks if the given command is valid and if so, executes it on + * the RF Chip + * + * \param[in] cmd: direct command to be executed + * + * \return ERR_PARAM : Invalid command or bad request + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : Direct command executed with no error + ***************************************************************************** + */ +ReturnCode rfalChipExecCmd( uint16_t cmd ); + +/*! + ***************************************************************************** + * \brief Set RFO + * + * Sets the RFO value to be used when the field is on (unmodulated/active) + * + * \param[in] rfo : the RFO value to be used + * + * \return ERR_IO : Internal error + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalChipSetRFO( uint8_t rfo ); + + +/*! + ***************************************************************************** + * \brief Get RFO + * + * Gets the RFO value used used when the field is on (unmodulated/active) + * + * \param[out] result : the current RFO value + * + * \return ERR_IO : Internal error + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalChipGetRFO( uint8_t* result ); + + +/*! + ***************************************************************************** + * \brief Measure Amplitude + * + * Measures the RF Amplitude + * + * \param[out] result : result of RF measurement + * + * \return ERR_IO : Internal error + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalChipMeasureAmplitude( uint8_t* result ); + + +/*! + ***************************************************************************** + * \brief Measure Phase + * + * Measures the Phase + * + * \param[out] result : result of Phase measurement + * + * \return ERR_IO : Internal error + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalChipMeasurePhase( uint8_t* result ); + + +/*! + ***************************************************************************** + * \brief Measure Capacitance + * + * Measures the Capacitance + * + * \param[out] result : result of Capacitance measurement + * + * \return ERR_IO : Internal error + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalChipMeasureCapacitance( uint8_t* result ); + + +/*! + ***************************************************************************** + * \brief Measure Power Supply + * + * Measures the Power Supply + * + * \param[in] param : measurement parameter (chip specific) + * \param[out] result : result of the measurement + * + * \return ERR_IO : Internal error + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalChipMeasurePowerSupply( uint8_t param, uint8_t* result ); + + +#endif /* RFAL_CHIP_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_crc.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_crc.h new file mode 100644 index 0000000..a6ca124 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_crc.h @@ -0,0 +1,75 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_crc.h + * + * \author Ulrich Herrmann + * + * \brief CRC calculation module + * + */ +/*! + * + */ + +#ifndef RFAL_CRC_H_ +#define RFAL_CRC_H_ + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +/*! + ***************************************************************************** + * \brief Calculate CRC according to CCITT standard. + * + * This function takes \a length bytes from \a buf and calculates the CRC + * for this data. The result is returned. + * \note This implementation calculates the CRC with LSB first, i.e. all + * bytes are "read" from right to left. + * + * \param[in] preloadValue : Initial value of CRC calculation. + * \param[in] buf : buffer to calculate the CRC for. + * \param[in] length : size of the buffer. + * + * \return 16 bit long crc value. + * + ***************************************************************************** + */ +extern uint16_t rfalCrcCalculateCcitt(uint16_t preloadValue, const uint8_t* buf, uint16_t length); + +#endif /* RFAL_CRC_H_ */ + diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_dpo.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_dpo.h new file mode 100644 index 0000000..8e7daaa --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_dpo.h @@ -0,0 +1,209 @@ + +/****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * $Revision: $ + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_dpo.h + * + * \author Martin Zechleitner + * + * \brief Dynamic Power adjustment + * + * This module provides an interface to perform the power adjustment dynamically + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-HAL + * \brief RFAL Hardware Abstraction Layer + * @{ + * + * \addtogroup DynamicPower + * \brief RFAL Dynamic Power Module + * @{ + * + */ + + +#ifndef RFAL_DPO_H +#define RFAL_DPO_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_DPO_TABLE_SIZE_MAX 15U /*!< Max DPO table size */ +#define RFAL_DPO_TABLE_PARAMETER 3U /*!< DPO table Parameter length */ + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! DPO table entry struct */ +typedef struct { + uint8_t rfoRes; /*!< Setting for the resistance level of the RFO */ + uint8_t inc; /*!< Threshold for incrementing the output power */ + uint8_t dec; /*!< Threshold for decrementing the output power */ +}rfalDpoEntry; + +/*! Function pointer to methode doing the reference measurement */ +typedef ReturnCode (*rfalDpoMeasureFunc)(uint8_t*); + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + + +/*! + ***************************************************************************** + * \brief Initialize dynamic power table + * + * This function sets the internal dynamic power table to the default + * values stored in rfal_DpoTbl.h + * + ***************************************************************************** + */ +void rfalDpoInitialize( void ); + +/*! + ***************************************************************************** + * \brief Set the measurement methode + * + * This function sets the measurement method used for reference measurement. + * Based on the measurement the power will then be adjusted + * + * \param[in] dpoMeasureFunc: callback of measurement function + * + ***************************************************************************** + */ +void rfalDpoSetMeasureCallback( rfalDpoMeasureFunc dpoMeasureFunc ); + +/*! + ***************************************************************************** + * \brief Write dynamic power table + * + * Load the dynamic power table + * + * \param[in] powerTbl: location of power Table to be loaded + * \param[in] powerTblEntries: number of entries of the power Table to be loaded + * + * \return ERR_NONE : No error + * \return ERR_PARAM : if configTbl is invalid + * \return ERR_NOMEM : if the given Table is bigger exceeds the max size + ***************************************************************************** + */ +ReturnCode rfalDpoTableWrite( rfalDpoEntry* powerTbl, uint8_t powerTblEntries ); + +/*! + ***************************************************************************** + * \brief Dynamic power table Read + * + * Read the dynamic power table + * + * \param[out] tblBuf: location to the rfalDpoEntry[] to place the Table + * \param[in] tblBufEntries: number of entries available in tblBuf to place the power Table + * \param[out] tableEntries: returned number of entries actually written into tblBuf + * + * \return ERR_NONE : No error + * \return ERR_PARAM : if configTbl is invalid or parameters are invalid + ***************************************************************************** + */ +ReturnCode rfalDpoTableRead( rfalDpoEntry* tblBuf, uint8_t tblBufEntries, uint8_t* tableEntries ); + +/*! + ***************************************************************************** + * \brief Dynamic power adjust + * + * It measures the current output and adjusts the power accordingly to + * the dynamic power table + * + * \return ERR_NONE : No error + * \return ERR_PARAM : if configTbl is invalid or parameters are invalid + * \return ERR_WRONG_STATE : if the current state is valid for DPO Adjustment + ***************************************************************************** + */ +ReturnCode rfalDpoAdjust( void ); + +/*! + ***************************************************************************** + * \brief Get Current Dynamic power table entry + * + * Return current used DPO power table entry settings + * + * \return ERR_NONE : Current DpoEntry. This includes d_res, inc and dec + * + ***************************************************************************** + */ +rfalDpoEntry* rfalDpoGetCurrentTableEntry(void); + +/*! + ***************************************************************************** + * \brief Dynamic power set enabled state + * + * \param[in] enable: new active state + * + * Set state to enable or disable the Dynamic power adjustment + * + ***************************************************************************** + */ +void rfalDpoSetEnabled( bool enable ); + +/*! + ***************************************************************************** + * \brief Get the Dynamic power enabled state + * + * Get state of the Dynamic power adjustment + * + * \return true : enabled + * \return false : disabled + ***************************************************************************** + */ +bool rfalDpoIsEnabled(void); + +#endif /* RFAL_DPO_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_dpoTbl.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_dpoTbl.h new file mode 100644 index 0000000..f5c8981 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_dpoTbl.h @@ -0,0 +1,56 @@ + +/****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * $Revision: $ + * LANGUAGE: ISO C99 + */ + + +#ifndef ST25R3911_DYNAMICPOWER_H +#define ST25R3911_DYNAMICPOWER_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_dpo.h" + + +/* + ****************************************************************************** + * GLOBAL VARIABLES + ****************************************************************************** + */ + + /*! Default DPO table */ +const uint8_t rfalDpoDefaultSettings [] = { + 0x00, 255, 200, + 0x01, 210, 150, + 0x02, 160, 100, + 0x03, 110, 50, + 0x0E, 60, 0 +}; + +#endif /* ST25R3911_DYNAMICPOWER_H */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_features.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_features.h new file mode 100644 index 0000000..943da90 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_features.h @@ -0,0 +1,115 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Gustavo Patricio + * + * \brief RFAL Features/Capabilities Definition for ST25R3911 + */ + + +#ifndef RFAL_FEATURES_H +#define RFAL_FEATURES_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ + +#define RFAL_SUPPORT_MODE_POLL_NFCA true /*!< RFAL Poll NFCA mode support switch */ +#define RFAL_SUPPORT_MODE_POLL_NFCB true /*!< RFAL Poll NFCB mode support switch */ +#define RFAL_SUPPORT_MODE_POLL_NFCF true /*!< RFAL Poll NFCF mode support switch */ +#define RFAL_SUPPORT_MODE_POLL_NFCV true /*!< RFAL Poll NFCV mode support switch */ +#define RFAL_SUPPORT_MODE_POLL_ACTIVE_P2P true /*!< RFAL Poll AP2P mode support switch */ +#define RFAL_SUPPORT_MODE_LISTEN_NFCA false /*!< RFAL Listen NFCA mode support switch */ +#define RFAL_SUPPORT_MODE_LISTEN_NFCB false /*!< RFAL Listen NFCB mode support switch */ +#define RFAL_SUPPORT_MODE_LISTEN_NFCF false /*!< RFAL Listen NFCF mode support switch */ +#define RFAL_SUPPORT_MODE_LISTEN_ACTIVE_P2P true /*!< RFAL Listen AP2P mode support switch */ + +/*******************************************************************************/ +/*! RFAL supported Card Emulation (CE) */ +#define RFAL_SUPPORT_CE ( RFAL_SUPPORT_MODE_LISTEN_NFCA || RFAL_SUPPORT_MODE_LISTEN_NFCB || RFAL_SUPPORT_MODE_LISTEN_NFCF ) + +/*! RFAL supported Reader/Writer (RW) */ +#define RFAL_SUPPORT_RW ( RFAL_SUPPORT_MODE_POLL_NFCA || RFAL_SUPPORT_MODE_POLL_NFCB || RFAL_SUPPORT_MODE_POLL_NFCF || RFAL_SUPPORT_MODE_POLL_NFCV ) + +/*! RFAL support for Active P2P (AP2P) */ +#define RFAL_SUPPORT_AP2P ( RFAL_SUPPORT_MODE_POLL_ACTIVE_P2P || RFAL_SUPPORT_MODE_POLL_ACTIVE_P2P ) + + +/*******************************************************************************/ +#define RFAL_SUPPORT_BR_RW_106 true /*!< RFAL RW 106 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_RW_212 true /*!< RFAL RW 212 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_RW_424 true /*!< RFAL RW 424 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_RW_848 true /*!< RFAL RW 848 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_RW_1695 true /*!< RFAL RW 1695 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_RW_3390 true /*!< RFAL RW 3390 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_RW_6780 false /*!< RFAL RW 6780 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_RW_13560 false /*!< RFAL RW 6780 Bit Rate support switch */ + + +/*******************************************************************************/ +#define RFAL_SUPPORT_BR_AP2P_106 true /*!< RFAL AP2P 106 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_AP2P_212 true /*!< RFAL AP2P 212 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_AP2P_424 true /*!< RFAL AP2P 424 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_AP2P_848 false /*!< RFAL AP2P 848 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_AP2P_1695 false /*!< RFAL AP2P 1695 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_AP2P_3390 false /*!< RFAL AP2P 3390 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_AP2P_6780 false /*!< RFAL AP2P 6780 Bit Rate support switch */ + + +/*******************************************************************************/ +#define RFAL_SUPPORT_BR_CE_A_106 false /*!< RFAL CE A 106 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_CE_A_212 false /*!< RFAL CE A 212 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_CE_A_424 false /*!< RFAL CE A 424 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_CE_A_848 false /*!< RFAL CE A 848 Bit Rate support switch */ + + +/*******************************************************************************/ +#define RFAL_SUPPORT_BR_CE_B_106 false /*!< RFAL CE B 106 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_CE_B_212 false /*!< RFAL CE B 212 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_CE_B_424 false /*!< RFAL CE B 424 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_CE_B_848 false /*!< RFAL CE B 848 Bit Rate support switch */ + + +/*******************************************************************************/ +#define RFAL_SUPPORT_BR_CE_F_212 false /*!< RFAL CE F 212 Bit Rate support switch */ +#define RFAL_SUPPORT_BR_CE_F_424 false /*!< RFAL CE F 424 Bit Rate support switch */ + + +#endif /* RFAL_FEATURES_H */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_iso15693_2.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_iso15693_2.h new file mode 100644 index 0000000..da64117 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_iso15693_2.h @@ -0,0 +1,202 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_iso15693_2.h + * + * \author Ulrich Herrmann + * + * \brief Implementation of ISO-15693-2 + * + */ +/*! + * + */ + +#ifndef RFAL_ISO_15693_2_H +#define RFAL_ISO_15693_2_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" +#include "st_errno.h" + +/* +****************************************************************************** +* GLOBAL DATATYPES +****************************************************************************** +*/ +/*! Enum holding possible VCD codings */ +typedef enum +{ + ISO15693_VCD_CODING_1_4, + ISO15693_VCD_CODING_1_256 +}iso15693VcdCoding_t; + +/*! Enum holding possible VICC datarates */ + +/*! Configuration parameter used by #iso15693PhyConfigure */ +typedef struct +{ + iso15693VcdCoding_t coding; /*!< desired VCD coding */ + uint32_t speedMode; /*!< 0: normal mode, 1: 2^1 = x2 Fast mode, 2 : 2^2 = x4 mode, 3 : 2^3 = x8 mode - all rx pulse numbers and times are divided by 1,2,4,8 */ +}iso15693PhyConfig_t; + +/*! Parameters how the stream mode should work */ +struct iso15693StreamConfig { + uint8_t useBPSK; /*!< 0: subcarrier, 1:BPSK */ + uint8_t din; /*!< the divider for the in subcarrier frequency: fc/2^din */ + uint8_t dout; /*!< the divider for the in subcarrier frequency fc/2^dout */ + uint8_t report_period_length; /*!< the length of the reporting period 2^report_period_length*/ +}; +/* +****************************************************************************** +* GLOBAL CONSTANTS +****************************************************************************** +*/ + +#define ISO15693_REQ_FLAG_TWO_SUBCARRIERS 0x01U /*!< Flag indication that communication uses two subcarriers */ +#define ISO15693_REQ_FLAG_HIGH_DATARATE 0x02U /*!< Flag indication that communication uses high bitrate */ +#define ISO15693_MASK_FDT_LISTEN (65) /*!< t1min = 308,2us = 4192/fc = 65.5 * 64/fc */ + +/*! t1max = 323,3us = 4384/fc = 68.5 * 64/fc + * 12 = 768/fc unmodulated time of single subcarrior SoF */ +#define ISO15693_FWT (69 + 12) + + + + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +/*! + ***************************************************************************** + * \brief Initialize the ISO15693 phy + * + * \param[in] config : ISO15693 phy related configuration (See #iso15693PhyConfig_t) + * \param[out] needed_stream_config : return a pointer to the stream config + * needed for this iso15693 config. To be used for configure RF chip. + * + * \return ERR_IO : Error during communication. + * \return ERR_NONE : No error. + * + ***************************************************************************** + */ +extern ReturnCode iso15693PhyConfigure(const iso15693PhyConfig_t* config, + const struct iso15693StreamConfig ** needed_stream_config ); + +/*! + ***************************************************************************** + * \brief Return current phy configuration + * + * This function returns current Phy configuration previously + * set by #iso15693PhyConfigure + * + * \param[out] config : ISO15693 phy configuration. + * + * \return ERR_NONE : No error. + * + ***************************************************************************** + */ +extern ReturnCode iso15693PhyGetConfiguration(iso15693PhyConfig_t* config); + +/*! + ***************************************************************************** + * \brief Code an ISO15693 compatible frame + * + * This function takes \a length bytes from \a buffer, perform proper + * encoding and sends out the frame to the ST25R391x. + * + * \param[in] buffer : data to send, modified to adapt flags. + * \param[in] length : number of bytes to send. + * \param[in] sendCrc : If set to true, CRC is appended to the frame + * \param[in] sendFlags: If set to true, flag field is sent according to + * ISO15693. + * \param[in] picopassMode : If set to true, the coding will be according to Picopass + * \param[out] subbit_total_length : Return the complete bytes which need to + * be send for the current coding + * \param[in,out] offset : Set to 0 for first transfer, function will update it to + point to next byte to be coded + * \param[out] outbuf : buffer where the function will store the coded subbit stream + * \param[out] outBufSize : the size of the output buffer + * \param[out] actOutBufSize : the amount of data stored into the buffer at this call + * + * \return ERR_IO : Error during communication. + * \return ERR_AGAIN : Data was not coded all the way. Call function again with a new/emptied buffer + * \return ERR_NO_MEM : In case outBuf is not big enough. Needs to have at + least 5 bytes for 1of4 coding and 65 bytes for 1of256 coding + * \return ERR_NONE : No error. + * + ***************************************************************************** + */ +extern ReturnCode iso15693VCDCode(uint8_t* buffer, uint16_t length, bool sendCrc, bool sendFlags, bool picopassMode, + uint16_t *subbit_total_length, uint16_t *offset, + uint8_t* outbuf, uint16_t outBufSize, uint16_t* actOutBufSize); + + +/*! + ***************************************************************************** + * \brief Receive an ISO15693 compatible frame + * + * This function receives an ISO15693 frame from the ST25R391x, decodes the frame + * and writes the raw data to \a buffer. + * \note Buffer needs to be big enough to hold CRC also (+2 bytes) + * + * \param[in] inBuf : buffer with the hamming coded stream to be decoded + * \param[in] inBufLen : number of bytes to decode (=length of buffer). + * \param[out] outBuf : buffer where received data shall be written to. + * \param[in] outBufLen : Length of output buffer, should be approx twice the size of inBuf + * \param[out] outBufPos : The number of decoded bytes. Could be used in + * extended implementation to allow multiple calls + * \param[out] bitsBeforeCol : in case of ERR_COLLISION this value holds the + * number of bits in the current byte where the collision happened. + * \param[in] ignoreBits : number of bits in the beginning where collisions will be ignored + * \param[in] picopassMode : if set to true, the decoding will be according to Picopass + * + * \return ERR_COLLISION : collision occured, data uncorrect + * \return ERR_CRC : CRC error, data uncorrect + * \return ERR_TIMEOUT : timeout waiting for data. + * \return ERR_NONE : No error. + * + ***************************************************************************** + */ +extern ReturnCode iso15693VICCDecode(const uint8_t *inBuf, + uint16_t inBufLen, + uint8_t* outBuf, + uint16_t outBufLen, + uint16_t* outBufPos, + uint16_t* bitsBeforeCol, + uint16_t ignoreBits, + bool picopassMode ); + +#endif /* RFAL_ISO_15693_2_H */ + diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_isoDep.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_isoDep.h new file mode 100644 index 0000000..546d6fe --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_isoDep.h @@ -0,0 +1,866 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_isoDep.h + * + * \author Gustavo Patricio + * + * \brief Implementation of ISO-DEP protocol + * + * This implementation was based on the following specs: + * - ISO/IEC 14443-4 2nd Edition 2008-07-15 + * - NFC Forum Digital Protocol 1.1 2014-01-14 + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup ISO-DEP + * \brief RFAL ISO-DEP Module + * @{ + * + */ + +#ifndef RFAL_ISODEP_H_ +#define RFAL_ISODEP_H_ +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "rfal_nfcb.h" +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ + +#define RFAL_ISODEP_PROLOGUE_SIZE (3U) /*!< Length of Prologue Field for I-Block Format */ + +#define RFAL_ISODEP_PCB_LEN (1U) /*!< PCB length */ +#define RFAL_ISODEP_DID_LEN (1U) /*!< DID length */ +#define RFAL_ISODEP_NAD_LEN (1U) /*!< NAD length */ +#define RFAL_ISODEP_NO_DID (0x00U) /*!< DID value indicating the ISO-DEP layer not to use DID */ +#define RFAL_ISODEP_NO_NAD (0xFFU) /*!< NAD value indicating the ISO-DEP layer not to use NAD */ + +#define RFAL_ISODEP_FWI_MASK (0xF0U) /*!< Mask bits of FWI */ +#define RFAL_ISODEP_FWI_SHIFT (4U) /*!< Shift val of FWI */ +#define RFAL_ISODEP_FWI_DEFAULT (4U) /*!< Default value for FWI Digital 1.0 11.6.2.17 */ +#define RFAL_ISODEP_ADV_FEATURE (0x0FU) /*!< Indicate 256 Bytes FSD and Advanc Proto Feature support:NAD & DID */ + +#define RFAL_ISODEP_DID_MAX (14U) /*!< Maximum DID value */ + +#define RFAL_ISODEP_BRI_MASK (0x07U) /*!< Mask bits for Poll to Listen Send bitrate */ +#define RFAL_ISODEP_BSI_MASK (0x70U) /*!< Mask bits for Listen to Poll Send bitrate */ +#define RFAL_ISODEP_SAME_BITRATE_MASK (0x80U) /*!< Mask bit indicate only same bit rate D for both direction support */ +#define RFAL_ISODEP_BITRATE_RFU_MASK (0x08U) /*!< Mask bit for RFU */ + +/*! Maximum Frame Waiting Time = ((256 * 16/fc) * 2^FWImax) = ((256*16/fc)*2^14) = (67108864)/fc = 2^26 (1/fc) */ +#define RFAL_ISODEP_MAX_FWT ((uint32_t)1U<<26) + + + +#define RFAL_ISODEP_FSDI_DEFAULT RFAL_ISODEP_FSXI_256 /*!< Default Frame Size Integer in Poll mode */ +#define RFAL_ISODEP_FSX_KEEP (0xFFU) /*!< Flag to keep FSX from activation */ +#define RFAL_ISODEP_DEFAULT_FSCI RFAL_ISODEP_FSXI_256 /*!< FSCI default value to be used in Listen Mode */ +#define RFAL_ISODEP_DEFAULT_FSC RFAL_ISODEP_FSX_256 /*!< FSC default value (aligned RFAL_ISODEP_DEFAULT_FSCI) */ +#define RFAL_ISODEP_DEFAULT_SFGI (0U) /*!< SFGI Default value to be used in Listen Mode */ +#define RFAL_ISODEP_DEFAULT_FWI (8U) /*!< Default Listener FWI (Max) Digital 2.0 B7 & B3 */ + +#define RFAL_ISODEP_APDU_MAX_LEN RFAL_ISODEP_FSX_1024 /*!< Max APDU length */ + +#define RFAL_ISODEP_ATTRIB_RES_MBLI_NO_INFO (0x00U) /*!< MBLI indicating no information on its internal input buffer size */ +#define RFAL_ISODEP_ATTRIB_REQ_PARAM1_DEFAULT (0x00U) /*!< Default values of Param 1 of ATTRIB_REQ Digital 1.0 12.6.1.3-5 */ +#define RFAL_ISODEP_ATTRIB_HLINFO_LEN (32U) /*!< Maximum Size of Higher Layer Information */ +#define RFAL_ISODEP_ATS_HB_MAX_LEN (15U) /*!< Maximum length of Historical Bytes Digital 1.1 13.6.2.23 */ +#define RFAL_ISODEP_ATTRIB_REQ_MIN_LEN (9U) /*!< Minimum Length of ATTRIB_REQ command */ +#define RFAL_ISODEP_ATTRIB_RES_MIN_LEN (1U) /*!< Minimum Length of ATTRIB_RES response */ + +#define RFAL_ISODEP_SPARAM_VALUES_MAX_LEN (16U) /*!< Maximum Length of the value field on S(PARAMETERS) */ +#define RFAL_ISODEP_SPARAM_TAG_BLOCKINFO (0xA0U) /*!< S(PARAMETERS) tag Block information */ +#define RFAL_ISODEP_SPARAM_TAG_BRREQ (0xA1U) /*!< S(PARAMETERS) tag Bit rates Request */ +#define RFAL_ISODEP_SPARAM_TAG_BRIND (0xA2U) /*!< S(PARAMETERS) tag Bit rates Indication */ +#define RFAL_ISODEP_SPARAM_TAG_BRACT (0xA3U) /*!< S(PARAMETERS) tag Bit rates Activation */ +#define RFAL_ISODEP_SPARAM_TAG_BRACK (0xA4U) /*!< S(PARAMETERS) tag Bit rates Acknowledgement */ + +#define RFAL_ISODEP_SPARAM_TAG_SUP_PCD2PICC (0x80U) /*!< S(PARAMETERS) tag Supported bit rates from PCD to PICC */ +#define RFAL_ISODEP_SPARAM_TAG_SUP_PICC2PCD (0x81U) /*!< S(PARAMETERS) tag Supported bit rates from PICC to PCD */ +#define RFAL_ISODEP_SPARAM_TAG_SUP_FRAME (0x82U) /*!< S(PARAMETERS) tag Supported framing options PICC to PCD */ +#define RFAL_ISODEP_SPARAM_TAG_SEL_PCD2PICC (0x83U) /*!< S(PARAMETERS) tag Selected bit rate from PCD to PICC */ +#define RFAL_ISODEP_SPARAM_TAG_SEL_PICC2PCD (0x84U) /*!< S(PARAMETERS) tag Selected bit rate from PICC to PCD */ +#define RFAL_ISODEP_SPARAM_TAG_SEL_FRAME (0x85U) /*!< S(PARAMETERS) tag Selected framing options PICC to PCD */ + +#define RFAL_ISODEP_SPARAM_TAG_LEN (1) /*!< S(PARAMETERS) Tag Length */ +#define RFAL_ISODEP_SPARAM_TAG_BRREQ_LEN (0U) /*!< S(PARAMETERS) tag Bit rates Request Length */ +#define RFAL_ISODEP_SPARAM_TAG_PICC2PCD_LEN (2U) /*!< S(PARAMETERS) bit rates from PCD to PICC Length */ +#define RFAL_ISODEP_SPARAM_TAG_PCD2PICC_LEN (2U) /*!< S(PARAMETERS) bit rates from PICC to PCD Length */ +#define RFAL_ISODEP_SPARAM_TAG_BRACK_LEN (0U) /*!< S(PARAMETERS) tag Bit rates Acknowledgement Length */ + +#define RFAL_ISODEP_ATS_TA_DPL_212 (0x01U) /*!< ATS TA DSI 212 kbps support bit mask */ +#define RFAL_ISODEP_ATS_TA_DPL_424 (0x02U) /*!< ATS TA DSI 424 kbps support bit mask */ +#define RFAL_ISODEP_ATS_TA_DPL_848 (0x04U) /*!< ATS TA DSI 848 kbps support bit mask */ +#define RFAL_ISODEP_ATS_TA_DLP_212 (0x10U) /*!< ATS TA DSI 212 kbps support bit mask */ +#define RFAL_ISODEP_ATS_TA_DLP_424 (0x20U) /*!< ATS TA DRI 424 kbps support bit mask */ +#define RFAL_ISODEP_ATS_TA_DLP_848 (0x40U) /*!< ATS TA DRI 848 kbps support bit mask */ +#define RFAL_ISODEP_ATS_TA_SAME_D (0x80U) /*!< ATS TA same bit both directions bit mask */ +#define RFAL_ISODEP_ATS_TB_FWI_MASK (0xF0U) /*!< Mask bits for FWI (Frame Waiting Integer) in TB byte */ +#define RFAL_ISODEP_ATS_TB_SFGI_MASK (0x0FU) /*!< Mask bits for SFGI (Start-Up Frame Guard Integer) in TB byte */ + +#define RFAL_ISODEP_ATS_T0_TA_PRESENCE_MASK (0x10U) /*!< Mask bit for TA presence */ +#define RFAL_ISODEP_ATS_T0_TB_PRESENCE_MASK (0x20U) /*!< Mask bit for TB presence */ +#define RFAL_ISODEP_ATS_T0_TC_PRESENCE_MASK (0x40U) /*!< Mask bit for TC presence */ +#define RFAL_ISODEP_ATS_T0_FSCI_MASK (0x0FU) /*!< Mask bit for FSCI presence */ +#define RFAL_ISODEP_ATS_T0_OFFSET (0x01U) /*!< Offset of T0 in ATS Response */ + + +#define RFAL_ISODEP_MAX_I_RETRYS (2U) /*!< Number of retries for a I-Block Digital 1.1 15.2.5.4 */ +#define RFAL_ISODEP_MAX_R_RETRYS (3U) /*!< Number of retries for a R-Block Digital 1.1 A8 - nRETRY ACK/NAK: [2,5] */ +#define RFAL_ISODEP_MAX_S_RETRYS (3U) /*!< Number of retries for a S-Block Digital 1.1 A8 - nRETRY DESELECT: [0,5] WTX[2,5] */ +#define RFAL_ISODEP_RATS_RETRIES (1U) /*!< RATS retries upon fail Digital 1.1 A.6 - [0,1] */ + + +/*! Frame Size for Proximity Card Integer definitions */ +typedef enum +{ + RFAL_ISODEP_FSXI_16 = 0, /*!< Frame Size for Proximity Card Integer with 16 bytes */ + RFAL_ISODEP_FSXI_24 = 1, /*!< Frame Size for Proximity Card Integer with 24 bytes */ + RFAL_ISODEP_FSXI_32 = 2, /*!< Frame Size for Proximity Card Integer with 32 bytes */ + RFAL_ISODEP_FSXI_40 = 3, /*!< Frame Size for Proximity Card Integer with 40 bytes */ + RFAL_ISODEP_FSXI_48 = 4, /*!< Frame Size for Proximity Card Integer with 48 bytes */ + RFAL_ISODEP_FSXI_64 = 5, /*!< Frame Size for Proximity Card Integer with 64 bytes */ + RFAL_ISODEP_FSXI_96 = 6, /*!< Frame Size for Proximity Card Integer with 96 bytes */ + RFAL_ISODEP_FSXI_128 = 7, /*!< Frame Size for Proximity Card Integer with 128 bytes */ + RFAL_ISODEP_FSXI_256 = 8, /*!< Frame Size for Proximity Card Integer with 256 bytes */ + RFAL_ISODEP_FSXI_512 = 9, /*!< Frame Size for Proximity Card Integer with 512 bytes ISO14443-3 Amd2 2012 */ + RFAL_ISODEP_FSXI_1024 = 10, /*!< Frame Size for Proximity Card Integer with 1024 bytes ISO14443-3 Amd2 2012 */ + RFAL_ISODEP_FSXI_2048 = 11, /*!< Frame Size for Proximity Card Integer with 2048 bytes ISO14443-3 Amd2 2012 */ + RFAL_ISODEP_FSXI_4096 = 12 /*!< Frame Size for Proximity Card Integer with 4096 bytes ISO14443-3 Amd2 2012 */ +} rfalIsoDepFSxI; + +/*! Frame Size for Proximity Card definitions */ +typedef enum +{ + RFAL_ISODEP_FSX_16 = 16, /*!< Frame Size for Proximity Card with 16 bytes */ + RFAL_ISODEP_FSX_24 = 24, /*!< Frame Size for Proximity Card with 24 bytes */ + RFAL_ISODEP_FSX_32 = 32, /*!< Frame Size for Proximity Card with 32 bytes */ + RFAL_ISODEP_FSX_40 = 40, /*!< Frame Size for Proximity Card with 40 bytes */ + RFAL_ISODEP_FSX_48 = 48, /*!< Frame Size for Proximity Card with 48 bytes */ + RFAL_ISODEP_FSX_64 = 64, /*!< Frame Size for Proximity Card with 64 bytes */ + RFAL_ISODEP_FSX_96 = 96, /*!< Frame Size for Proximity Card with 96 bytes */ + RFAL_ISODEP_FSX_128 = 128, /*!< Frame Size for Proximity Card with 128 bytes */ + RFAL_ISODEP_FSX_256 = 256, /*!< Frame Size for Proximity Card with 256 bytes */ + RFAL_ISODEP_FSX_512 = 512, /*!< Frame Size for Proximity Card with 512 bytes ISO14443-3 Amd2 2012 */ + RFAL_ISODEP_FSX_1024 = 1024, /*!< Frame Size for Proximity Card with 1024 bytes ISO14443-3 Amd2 2012 */ + RFAL_ISODEP_FSX_2048 = 2048, /*!< Frame Size for Proximity Card with 2048 bytes ISO14443-3 Amd2 2012 */ + RFAL_ISODEP_FSX_4096 = 4096, /*!< Frame Size for Proximity Card with 4096 bytes ISO14443-3 Amd2 2012 */ +} rfalIsoDepFSx; + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + +/* + ****************************************************************************** + * GLOBAL DATA TYPES + ****************************************************************************** + */ + +/*! RATS format Digital 1.1 13.6.1 */ +typedef struct +{ + uint8_t CMD; /*!< RATS command byte: 0xE0 */ + uint8_t PARAM; /*!< Param indicating FSDI and DID */ +} rfalIsoDepRats; + + +/*! ATS response format Digital 1.1 13.6.2 */ +typedef struct +{ + uint8_t TL; /*!< Length Byte, including TL byte itself */ + uint8_t T0; /*!< Format Byte T0 indicating if TA, TB, TC */ + uint8_t TA; /*!< Interface Byte TA(1) */ + uint8_t TB; /*!< Interface Byte TB(1) */ + uint8_t TC; /*!< Interface Byte TC(1) */ + uint8_t HB[RFAL_ISODEP_ATS_HB_MAX_LEN]; /*!< Historical Bytes */ +} rfalIsoDepAts; + + +/*! PPS Request format (Protocol and Parameter Selection) ISO14443-4 5.3 */ +typedef struct +{ + uint8_t PPSS; /*!< Start Byte: [ 1101b | CID[4b] ] */ + uint8_t PPS0; /*!< Parameter 0:[ 000b | PPS1[1n] | 0001b ] */ + uint8_t PPS1; /*!< Parameter 1:[ 0000b | DSI[2b] | DRI[2b] ]*/ +} rfalIsoDepPpsReq; + + +/*! PPS Response format (Protocol and Parameter Selection) ISO14443-4 5.4 */ +typedef struct +{ + uint8_t PPSS; /*!< Start Byte: [ 1101b | CID[4b] ] */ +} rfalIsoDepPpsRes; + + +/*! ATTRIB Command Format Digital 1.1 15.6.1 */ +typedef struct +{ + uint8_t cmd; /*!< ATTRIB_REQ command byte */ + uint8_t nfcid0[RFAL_NFCB_NFCID0_LEN]; /*!< NFCID0 of the card to be selected */ + struct{ + uint8_t PARAM1; /*!< PARAM1 of ATTRIB command */ + uint8_t PARAM2; /*!< PARAM2 of ATTRIB command */ + uint8_t PARAM3; /*!< PARAM3 of ATTRIB command */ + uint8_t PARAM4; /*!< PARAM4 of ATTRIB command */ + }Param; /*!< Parameter of ATTRIB command */ + uint8_t HLInfo[RFAL_ISODEP_ATTRIB_HLINFO_LEN]; /*!< Higher Layer Information */ +} rfalIsoDepAttribCmd; + + +/*! ATTRIB Response Format Digital 1.1 15.6.2 */ +typedef struct +{ + uint8_t mbliDid; /*!< Contains MBLI and DID */ + uint8_t HLInfo[RFAL_ISODEP_ATTRIB_HLINFO_LEN]; /*!< Higher Layer Information */ +} rfalIsoDepAttribRes; + +/*! S(Parameters) Command Format ISO14443-4 (2016) Table 4 */ +typedef struct +{ + uint8_t tag; /*!< S(PARAMETERS) Tag field */ + uint8_t length; /*!< S(PARAMETERS) Length field */ + uint8_t value[RFAL_ISODEP_SPARAM_VALUES_MAX_LEN]; /*!< S(PARAMETERS) Value field */ +} rfalIsoDepSParameter; + + +/*! Activation info as Poller and Listener for NFC-A and NFC-B */ +typedef union {/* PRQA S 0750 # MISRA 19.2 - Both members of the union will not be used concurrently, device is only of type A or B at a time. Thus no problem can occur. */ + + /*! NFC-A information */ + union {/* PRQA S 0750 # MISRA 19.2 - Both members of the union will not be used concurrently, device is only PCD or PICC at a time. Thus no problem can occur. */ + struct { + rfalIsoDepAts ATS; /*!< ATS response (Poller mode) */ + uint8_t ATSLen; /*!< ATS response length (Poller mode) */ + }Listener; + struct { + rfalIsoDepRats RATS; /*!< RATS request (Listener mode) */ + }Poller; + }A; + + /*! NFC-B information */ + union {/* PRQA S 0750 # MISRA 19.2 - Both members of the union will not be used concurrently, device is only PCD or PICC at a time. Thus no problem can occur. */ + struct{ + rfalIsoDepAttribRes ATTRIB_RES; /*!< ATTRIB_RES (Poller mode) */ + uint8_t ATTRIB_RESLen; /*!< ATTRIB_RES length (Poller mode) */ + }Listener; + struct{ + rfalIsoDepAttribCmd ATTRIB; /*!< ATTRIB request (Listener mode) */ + uint8_t ATTRIBLen; /*!< ATTRIB request length (Listener mode) */ + }Poller; + }B; +}rfalIsoDepActivation; + + +/*! ISO-DEP device Info */ +typedef struct { + uint8_t FWI; /*!< Frame Waiting Integer */ + uint32_t FWT; /*!< Frame Waiting Time (1/fc) */ + uint32_t dFWT; /*!< Delta Frame Waiting Time (1/fc) */ + uint32_t SFGI; /*!< Start-up Frame Guard time Integer */ + uint32_t SFGT; /*!< Start-up Frame Guard Time (ms) */ + uint8_t FSxI; /*!< Frame Size Device/Card Integer (FSDI or FSCI) */ + uint16_t FSx; /*!< Frame Size Device/Card (FSD or FSC) */ + uint32_t MBL; /*!< Maximum Buffer Length (optional for NFC-B) */ + rfalBitRate DSI; /*!< Bit Rate coding from Listener (PICC) to Poller (PCD) */ + rfalBitRate DRI; /*!< Bit Rate coding from Poller (PCD) to Listener (PICC) */ + uint8_t DID; /*!< Device ID */ + uint8_t NAD; /*!< Node ADdress */ + bool supDID; /*!< DID supported flag */ + bool supNAD; /*!< NAD supported flag */ + bool supAdFt; /*!< Advanced Features supported flag */ +} rfalIsoDepInfo; + + +/*! ISO-DEP Device structure */ +typedef struct { + rfalIsoDepActivation activation; /*!< Activation Info */ + rfalIsoDepInfo info; /*!< ISO-DEP (ISO14443-4) device Info */ +} rfalIsoDepDevice; + + +/*! ATTRIB Response parameters */ +typedef struct +{ + uint8_t mbli; /*!< MBLI */ + uint8_t HLInfo[RFAL_ISODEP_ATTRIB_HLINFO_LEN]; /*!< Hi Layer Information */ + uint8_t HLInfoLen; /*!< Hi Layer Information Length */ +} rfalIsoDepAttribResParam; + + +/*! ATS Response parameter */ +typedef struct +{ + uint8_t fsci; /*!< Frame Size of Proximity Card Integer */ + uint8_t fwi; /*!< Frame Waiting Time Integer */ + uint8_t sfgi; /*!< Start-Up Frame Guard Time Integer */ + bool didSupport; /*!< DID Supported */ + uint8_t ta; /*!< Max supported bitrate both direction */ + uint8_t *hb; /*!< Historical Bytes data */ + uint8_t hbLen; /*!< Historical Bytes Length */ +} rfalIsoDepAtsParam; + + +/*! Structure of I-Block Buffer format from caller */ +typedef struct +{ + uint8_t prologue[RFAL_ISODEP_PROLOGUE_SIZE]; /*!< Prologue/SoD buffer */ + uint8_t inf[RFAL_FEATURE_ISO_DEP_IBLOCK_MAX_LEN]; /*!< INF/Payload buffer */ +} rfalIsoDepBufFormat; + + +/*! Structure of APDU Buffer format from caller */ +typedef struct +{ + uint8_t prologue[RFAL_ISODEP_PROLOGUE_SIZE]; /*!< Prologue/SoD buffer */ + uint8_t apdu[RFAL_FEATURE_ISO_DEP_APDU_MAX_LEN]; /*!< APDU/Payload buffer */ +} rfalIsoDepApduBufFormat; + + +/*! Listen Activation Parameters Structure */ +typedef struct +{ + rfalIsoDepBufFormat *rxBuf; /*!< Receive Buffer struct reference */ + uint16_t *rxLen; /*!< Received INF data length in Bytes */ + bool *isRxChaining; /*!< Received data is not complete */ + rfalIsoDepDevice *isoDepDev; /*!< ISO-DEP device info */ +} rfalIsoDepListenActvParam; + + +/*! Structure of parameters used on ISO DEP Transceive */ +typedef struct +{ + rfalIsoDepBufFormat *txBuf; /*!< Transmit Buffer struct reference */ + uint16_t txBufLen; /*!< Transmit Buffer INF field length in Bytes*/ + bool isTxChaining; /*!< Transmit data is not complete */ + rfalIsoDepBufFormat *rxBuf; /*!< Receive Buffer struct reference in Bytes */ + uint16_t *rxLen; /*!< Received INF data length in Bytes */ + bool *isRxChaining; /*!< Received data is not complete */ + uint32_t FWT; /*!< FWT to be used (ignored in Listen Mode) */ + uint32_t dFWT; /*!< Delta FWT to be used */ + uint16_t ourFSx; /*!< Our device Frame Size (FSD or FSC) */ + uint16_t FSx; /*!< Other device Frame Size (FSD or FSC) */ + uint8_t DID; /*!< Device ID (RFAL_ISODEP_NO_DID if no DID) */ +} rfalIsoDepTxRxParam; + + +/*! Structure of parameters used on ISO DEP APDU Transceive */ +typedef struct +{ + rfalIsoDepApduBufFormat *txBuf; /*!< Transmit Buffer struct reference */ + uint16_t txBufLen; /*!< Transmit Buffer INF field length in Bytes*/ + rfalIsoDepApduBufFormat *rxBuf; /*!< Receive Buffer struct reference in Bytes */ + uint16_t *rxLen; /*!< Received INF data length in Bytes */ + rfalIsoDepBufFormat *tmpBuf; /*!< Temp buffer for Rx I-Blocks (internal) */ + uint32_t FWT; /*!< FWT to be used (ignored in Listen Mode) */ + uint32_t dFWT; /*!< Delta FWT to be used */ + uint16_t FSx; /*!< Other device Frame Size (FSD or FSC) */ + uint16_t ourFSx; /*!< Our device Frame Size (FSD or FSC) */ + uint8_t DID; /*!< Device ID (RFAL_ISODEP_NO_DID if no DID) */ +} rfalIsoDepApduTxRxParam; + +/* + ****************************************************************************** + * GLOBAL FUNCTION PROTOTYPES + ****************************************************************************** + */ + + +/*! + ****************************************************************************** + * \brief Initialize the ISO-DEP protocol + * + * Initialize the ISO-DEP protocol layer with default config + ****************************************************************************** + */ +void rfalIsoDepInitialize( void ); + + +/*! + ****************************************************************************** + * \brief Initialize the ISO-DEP protocol + * + * Initialize the ISO-DEP protocol layer with additional parameters allowing + * to customise the protocol layer for specific behaviours + * + * \param[in] compMode : compliance mode to be performed + * \param[in] maxRetriesR : Number of retries for a R-Block + * \param[in] maxRetriesS : Number of retries for a S-Block + * \param[in] maxRetriesI : Number of retries for a I-Block + * \param[in] maxRetriesRATS : Number of retries for RATS + * + ****************************************************************************** + */ +void rfalIsoDepInitializeWithParams( rfalComplianceMode compMode, uint8_t maxRetriesR, uint8_t maxRetriesS, uint8_t maxRetriesI, uint8_t maxRetriesRATS ); + + +/*! + ***************************************************************************** + * \brief FSxI to FSx + * + * Convert Frame Size for proximity coupling Device Integer (FSxI) to + * Frame Size for proximity coupling Device (FSx) + * + * FSD - maximum frame size for NFC Forum Device in Poll Mode + * FSC - maximum frame size for NFC Forum Device in Listen Mode + * + * FSxI = FSDI or FSCI + * FSx = FSD or FSC + * + * The FSD/FSC value includes the header and CRC + * + * \param[in] FSxI : Frame Size for proximity coupling Device Integer + * + * \return fsx : Frame Size for proximity coupling Device (FSD or FSC) + * + ***************************************************************************** + */ +uint16_t rfalIsoDepFSxI2FSx( uint8_t FSxI ); + + +/*! + ***************************************************************************** + * \brief FWI to FWT + * + * Convert Frame Waiting time Integer (FWI) to Frame Waiting Time (FWT) in + * 1/fc units + * + * \param[in] fwi : Frame Waiting time Integer + * + * \return fwt : Frame Waiting Time in 1/fc units + * + ***************************************************************************** + */ +uint32_t rfalIsoDepFWI2FWT( uint8_t fwi ); + + +/*! + ***************************************************************************** + * \brief Check if the buffer data contains a valid RATS command + * + * Check if it is a well formed RATS command with 2 bytes + * This function does not check the validity of FSDI and DID + * + * \param[in] buf : reference to buffer containing the data to be checked + * \param[in] bufLen : length of data in the buffer in bytes + * + * \return true if the data indicates a RATS command; false otherwise + ***************************************************************************** + */ +bool rfalIsoDepIsRats( const uint8_t *buf, uint8_t bufLen ); + + +/*! + ***************************************************************************** + * \brief Check if the buffer data contains a valid ATTRIB command + * + * Check if it is a well formed ATTRIB command, but does not check the + * validity of the information inside + * + * \param[in] buf : reference to buffer containing the data to be checked + * \param[in] bufLen : length of data in the buffer in bytes + * + * \return true if the data indicates a ATTRIB command; false otherwise + ***************************************************************************** + */ +bool rfalIsoDepIsAttrib( const uint8_t *buf, uint8_t bufLen ); + + +/*! + ***************************************************************************** + * \brief Start Listen Activation Handling + * + * Start Listen Activation Handling and setup to receive first I-block which may + * contain complete or partial APDU after activation is completed + * + * Pass in RATS for T4AT, or ATTRIB for T4BT, to handle ATS or ATTRIB Response respectively + * The Activation Handling handles ATS and ATTRIB Response; and additionally PPS Response + * if a PPS is received for T4AT. + * The method uses the current RFAL state machine to determine if it is expecting RATS or ATTRIB + * + * Activation is completed if PPS Response is sent or if first PDU is received in T4T-A + * Activation is completed if ATTRIB Response is sent in T4T-B + * + * \ref rfalIsoDepListenGetActivationStatus provide status if activation is completed. + * \ref rfalIsoDepStartTransceive shall be called right after activation is completed + * + * \param[in] atsParam : reference to ATS parameters + * \param[in] attribResParam : reference to ATTRIB_RES parameters + * \param[in] buf : reference to buffer containing RATS or ATTRIB + * \param[in] bufLen : length in bytes of the given bufffer + * \param[in] actParam : reference to incoming reception information will be placed + * + * + * \warning Once the Activation has been completed the method + * rfalIsoDepGetTransceiveStatus() must be called. + * If activation has completed due to reception of a data block (not PPS) the + * buffer owned by the caller and passed on actParam must still contain this data. + * The first data will be processed (I-Block or S-DSL) by rfalIsoDepGetTransceiveStatus() + * inform the caller and then for the next transaction use rfalIsoDepStartTransceive() + * + * \return ERR_NONE : RATS/ATTRIB is valid and activation has started + * \return ERR_PARAM : Invalid parameters + * \return ERR_PROTO : Invalid request + * \return ERR_NOTSUPP : Feature not supported + ***************************************************************************** + */ +ReturnCode rfalIsoDepListenStartActivation( rfalIsoDepAtsParam *atsParam, const rfalIsoDepAttribResParam *attribResParam, uint8_t *buf, uint16_t bufLen, rfalIsoDepListenActvParam actParam ); + + +/*! + ***************************************************************************** + * \brief Get the current Activation Status + * + * \return ERR_NONE if Activation is already completed + * \return ERR_BUSY if Activation is ongoing + * \return ERR_LINK_LOSS if Remote Field is turned off + ***************************************************************************** + */ +ReturnCode rfalIsoDepListenGetActivationStatus( void ); + + +/*! + ***************************************************************************** + * \brief Get the ISO-DEP Communication Information + * + * Gets the maximum INF length in bytes based on current Frame Size + * for proximity coupling Device (FSD or FSC) excluding the header and CRC + * + * \return maximum INF length in bytes + ***************************************************************************** + */ +uint16_t rfalIsoDepGetMaxInfLen( void ); + + +/*! + ***************************************************************************** + * \brief ISO-DEP Start Transceive + * + * This method triggers a ISO-DEP Transceive containing a complete or + * partial APDU + * It transmits the given message and handles all protocol retransmitions, + * error handling and control messages + * + * The txBuf contains a complete or partial APDU (INF) to be transmitted + * The Prologue field will be manipulated by the Transceive + * + * If the buffer contains a partial APDU and is not the last block, + * then isTxChaining must be set to true + * + * \param[in] param: reference parameters to be used for the Transceive + * + * \return ERR_PARAM : Bad request + * \return ERR_WRONG_STATE : The module is not in a proper state + * \return ERR_NONE : The Transceive request has been started + ***************************************************************************** + */ +ReturnCode rfalIsoDepStartTransceive( rfalIsoDepTxRxParam param ); + + +/*! + ***************************************************************************** + * \brief Get the Transceive status + * + * Returns the status of the ISO-DEP Transceive + * + * \warning When the other device is performing chaining once a chained + * block is received the error ERR_AGAIN is sent. At this point + * caller must handle the received data immediately. + * When ERR_AGAIN is returned an ACK has already been sent to + * the other device and the next block might be incoming. + * If rfalWorker() is called frequently it will place the next + * block on the given buffer + * + * + * \return ERR_NONE : Transceive has been completed successfully + * \return ERR_BUSY : Transceive is ongoing + * \return ERR_PROTO : Protocol error occurred + * \return ERR_TIMEOUT : Timeout error occurred + * \return ERR_SLEEP_REQ : Deselect has been received and responded + * \return ERR_NOMEM : The received INF does not fit into the + * receive buffer + * \return ERR_LINK_LOSS : Communication is lost because Reader/Writer + * has turned off its field + * \return ERR_AGAIN : received one chaining block, continue to call + * this method to retrieve the remaining blocks + ***************************************************************************** + */ +ReturnCode rfalIsoDepGetTransceiveStatus( void ); + + +/*! + ***************************************************************************** + * \brief ISO-DEP Start APDU Transceive + * + * This method triggers a ISO-DEP Transceive containing a complete APDU + * It transmits the given message and handles all protocol retransmitions, + * error handling and control messages + * + * The txBuf contains a complete APDU to be transmitted + * The Prologue field will be manipulated by the Transceive + * + * \warning the txBuf will be modified during the transmission + * \warning the maximum RF frame which can be received is limited by param.tmpBuf + * + * \param[in] param: reference parameters to be used for the Transceive + * + * \return ERR_PARAM : Bad request + * \return ERR_WRONG_STATE : The module is not in a proper state + * \return ERR_NONE : The Transceive request has been started + ***************************************************************************** + */ +ReturnCode rfalIsoDepStartApduTransceive( rfalIsoDepApduTxRxParam param ); + + +/*! + ***************************************************************************** + * \brief Get the APDU Transceive status + * + * \return ERR_NONE : if Transceive has been completed successfully + * \return ERR_BUSY : if Transceive is ongoing + * \return ERR_PROTO : if a protocol error occurred + * \return ERR_TIMEOUT : if a timeout error occurred + * \return ERR_SLEEP_REQ : if Deselect is received and responded + * \return ERR_NOMEM : if the received INF does not fit into the + * receive buffer + * \return ERR_LINK_LOSS : if communication is lost because Reader/Writer + * has turned off its field + ***************************************************************************** + */ +ReturnCode rfalIsoDepGetApduTransceiveStatus( void ); + +/*! + ***************************************************************************** + * \brief ISO-DEP Send RATS + * + * This sends a RATS to make a NFC-A Listen Device to enter + * ISO-DEP layer (ISO14443-4) and checks if the received ATS is valid + * + * \param[in] FSDI : Frame Size Device Integer to be used + * \param[in] DID : Device ID to be used or RFAL_ISODEP_NO_DID for not use DID + * \param[out] ats : pointer to place the ATS Response + * \param[out] atsLen : pointer to place the ATS length + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, ATS received + ***************************************************************************** + */ +ReturnCode rfalIsoDepRATS( rfalIsoDepFSxI FSDI, uint8_t DID, rfalIsoDepAts *ats , uint8_t *atsLen ); + + +/*! + ***************************************************************************** + * \brief ISO-DEP Send PPS + * + * This sends a PPS to make a NFC-A Listen Device change the communications + * bit rate from 106kbps to one of the supported bit rates + * Additionally checks if the received PPS response is valid + * + * \param[in] DID : Device ID + * \param[in] DSI : DSI code the divisor from Listener (PICC) to Poller (PCD) + * \param[in] DRI : DRI code the divisor from Poller (PCD) to Listener (PICC) + * \param[out] ppsRes : pointer to place the PPS Response + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, PPS Response received + ***************************************************************************** + */ +ReturnCode rfalIsoDepPPS( uint8_t DID, rfalBitRate DSI, rfalBitRate DRI, rfalIsoDepPpsRes *ppsRes ); + + +/*! + ***************************************************************************** + * \brief ISO-DEP Send ATTRIB + * + * This sends a ATTRIB to make a NFC-B Listen Device to enter + * ISO-DEP layer (ISO14443-4) and checks if the received ATTRIB Response is valid + * + * \param[in] nfcid0 : NFCID0 to be used for the ATTRIB + * \param[in] PARAM1 : ATTRIB PARAM1 byte (communication parameters) + * \param[in] DSI : DSI code the divisor from Listener (PICC) to Poller (PCD) + * \param[in] DRI : DRI code the divisor from Poller (PCD) to Listener (PICC) + * \param[in] FSDI : PCD's Frame Size to be announced on the ATTRIB + * \param[in] PARAM3 : ATTRIB PARAM1 byte (protocol type) + * \param[in] DID : Device ID to be used or RFAL_ISODEP_NO_DID for not use DID + * \param[in] HLInfo : pointer to Higher layer INF (NULL if none) + * \param[in] HLInfoLen : Length HLInfo + * \param[in] fwt : Frame Waiting Time to be used (from SENSB_RES) + * \param[out] attribRes : pointer to place the ATTRIB Response + * \param[out] attribResLen : pointer to place the ATTRIB Response length + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, ATTRIB Response received + ***************************************************************************** + */ +ReturnCode rfalIsoDepATTRIB( const uint8_t* nfcid0, uint8_t PARAM1, rfalBitRate DSI, rfalBitRate DRI, rfalIsoDepFSxI FSDI, uint8_t PARAM3, uint8_t DID, const uint8_t* HLInfo, uint8_t HLInfoLen, uint32_t fwt, rfalIsoDepAttribRes *attribRes, uint8_t *attribResLen ); + + +/*! + ***************************************************************************** + * \brief Deselects PICC + * + * This function sends a deselect command to PICC and waits for it`s + * responce in a blocking way + * + * \return ERR_NONE : Deselect successfully sent and acknowledged by PICC + * \return ERR_TIMEOUT: No response rcvd from PICC + * + ***************************************************************************** + */ +ReturnCode rfalIsoDepDeselect( void ); + + +/*! + ***************************************************************************** + * \brief ISO-DEP Poller Handle NFC-A Activation + * + * This performs a NFC-A Activation into ISO-DEP layer (ISO14443-4) with the given + * parameters. It sends RATS and if the higher bit rates are supported by + * both devices it additionally sends PPS + * Once Activated all details of the device are provided on isoDepDev + * + * \param[in] FSDI : Frame Size Device Integer to be used + * \param[in] DID : Device ID to be used or RFAL_ISODEP_NO_DID for not use DID + * \param[in] maxBR : Max bit rate supported by the Poller + * \param[out] isoDepDev : ISO-DEP information of the activated Listen device + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, activation successful + ***************************************************************************** + */ +ReturnCode rfalIsoDepPollAHandleActivation( rfalIsoDepFSxI FSDI, uint8_t DID, rfalBitRate maxBR, rfalIsoDepDevice *isoDepDev ); + + +/*! + ***************************************************************************** + * \brief ISO-DEP Poller Handle NFC-B Activation + * + * This performs a NFC-B Activation into ISO-DEP layer (ISO14443-4) with the given + * parameters. It sends ATTRIB and calculates supported higher bit rates of both + * devices and performs activation. + * Once Activated all details of the device are provided on isoDepDev + * + * \param[in] FSDI : Frame Size Device Integer to be used + * \param[in] DID : Device ID to be used or RFAL_ISODEP_NO_DID for not use DID + * \param[in] maxBR : Max bit rate supported by the Poller + * \param[in] PARAM1 : ATTRIB PARAM1 byte (communication parameters) + * \param[in] nfcbDev : pointer to the NFC-B Device containing the SENSB_RES + * \param[in] HLInfo : pointer to Higher layer INF (NULL if none) + * \param[in] HLInfoLen : Length HLInfo + * \param[out] isoDepDev : ISO-DEP information of the activated Listen device + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, activation successful + ***************************************************************************** + */ +ReturnCode rfalIsoDepPollBHandleActivation( rfalIsoDepFSxI FSDI, uint8_t DID, rfalBitRate maxBR, uint8_t PARAM1, const rfalNfcbListenDevice *nfcbDev, const uint8_t* HLInfo, uint8_t HLInfoLen, rfalIsoDepDevice *isoDepDev ); + + +/*! + ***************************************************************************** + * \brief ISO-DEP Poller Handle S(Parameters) + * + * This checks if PICC supports S(PARAMETERS), retieves PICC's + * capabilities and sets the Bit Rate at the highest supported by both + * devices + * + * \param[out] isoDepDev : ISO-DEP information of the activated Listen device + * \param[in] maxTxBR : Maximum Tx bit rate supported by PCD + * \param[in] maxRxBR : Maximum Rx bit rate supported by PCD + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, S(PARAMETERS) selection successful + ***************************************************************************** + */ +ReturnCode rfalIsoDepPollHandleSParameters( rfalIsoDepDevice *isoDepDev, rfalBitRate maxTxBR, rfalBitRate maxRxBR ); + + +#endif /* RFAL_ISODEP_H_ */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_nfc.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfc.h new file mode 100644 index 0000000..e2cc059 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfc.h @@ -0,0 +1,406 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfc.h + * + * \brief RFAL NFC device + * + * This module provides the required features to behave as an NFC Poller + * or Listener device. It grants an easy to use interface for the following + * activities: Technology Detection, Collision Resolution, Activation, + * Data Exchange, and Deactivation + * + * This layer is influenced by (but not fully aligned with) the NFC Forum + * specifications, in particular: Activity 2.0 and NCI 2.0 + * + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup RF + * \brief RFAL RF Abstraction Layer + * @{ + * + */ + +#ifndef RFAL_NFC_H +#define RFAL_NFC_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" +#include "rfal_nfca.h" +#include "rfal_nfcb.h" +#include "rfal_nfcf.h" +#include "rfal_nfcv.h" +#include "rfal_st25tb.h" +#include "rfal_nfcDep.h" +#include "rfal_isoDep.h" + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ +#define RFAL_NFC_RF_BUF_LEN 255U /*!< No technology */ + +#define RFAL_NFC_TECH_NONE 0x0000U /*!< No technology */ +#define RFAL_NFC_POLL_TECH_A 0x0001U /*!< NFC-A technology Flag */ +#define RFAL_NFC_POLL_TECH_B 0x0002U /*!< NFC-B technology Flag */ +#define RFAL_NFC_POLL_TECH_F 0x0004U /*!< NFC-F technology Flag */ +#define RFAL_NFC_POLL_TECH_V 0x0008U /*!< NFC-V technology Flag */ +#define RFAL_NFC_POLL_TECH_AP2P 0x0010U /*!< AP2P technology Flag */ +#define RFAL_NFC_POLL_TECH_ST25TB 0x0020U /*!< ST25TB technology Flag */ +#define RFAL_NFC_LISTEN_TECH_A 0x1000U /*!< NFC-V technology Flag */ +#define RFAL_NFC_LISTEN_TECH_B 0x2000U /*!< NFC-V technology Flag */ +#define RFAL_NFC_LISTEN_TECH_F 0x4000U /*!< NFC-V technology Flag */ +#define RFAL_NFC_LISTEN_TECH_AP2P 0x8000U /*!< NFC-V technology Flag */ + + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ + +/*! Checks if a device is currently activated */ +#define rfalNfcIsDevActivated( st ) ( ((st)>= RFAL_NFC_STATE_ACTIVATED) && ((st)= RFAL_NFC_STATE_START_DISCOVERY) && ((st)= 1. + * + * \param[in] disParams : discovery configuration parameters + * + * \return ERR_WRONG_STATE : Incorrect state for this operation + * \return ERR_PARAM : Invalid parameters + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcDiscover( const rfalNfcDiscoverParam *disParams ); + +/*! + ***************************************************************************** + * \brief RFAL NFC Get State + * + * It returns the current state + * + * \return rfalNfcState : the current state + ***************************************************************************** + */ +rfalNfcState rfalNfcGetState( void ); + +/*! + ***************************************************************************** + * \brief RFAL NFC Get Devices Found + * + * It returns the location of the device list and the number of + * devices found. + * + * \param[out] devList : device list location + * \param[out] devCnt : number of devices found + * + * \return ERR_WRONG_STATE : Incorrect state for this operation + * Discovery still ongoing + * \return ERR_PARAM : Invalid parameters + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcGetDevicesFound( rfalNfcDevice **devList, uint8_t *devCnt ); + +/*! + ***************************************************************************** + * \brief RFAL NFC Get Active Device + * + * It returns the location of the device current Active device + * + * \param[out] dev : device info location + * + * \return ERR_WRONG_STATE : Incorrect state for this operation + * No device activated + * \return ERR_PARAM : Invalid parameters + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcGetActiveDevice( rfalNfcDevice **dev ); + +/*! + ***************************************************************************** + * \brief RFAL NFC Select Device + * + * It selects the device to be activated. + * It shall be called when more than one device has been identified to + * indiacte which device shall be actived + * + * \param[in] devIdx : device index to be activated + * + * \return ERR_WRONG_STATE : Incorrect state for this operation + * Not in select state + * \return ERR_PARAM : Invalid parameters + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcSelect( uint8_t devIdx ); + +/*! + ***************************************************************************** + * \brief RFAL NFC Start Data Exchange + * + * After a device has been activated, it starts a data exchange. + * It handles automatically which interface/protocol to be used and acts accordingly. + * + * In Listen mode the first frame/data shall be sent by the Reader/Initiator + * therefore this method must be called first with txDataLen set to zero + * to retrieve the rxData and rcvLen locations. + * + * + * \param[in] txData : data to be transmitted + * \param[in] txDataLen : size of the data to be transmitted + * \param[out] rxData : location of the received data after operation is completed + * \param[out] rvdLen : location of thelength of the received data + * \param[in] fwt : FWT to be used in case of RF interface. + * If ISO-DEP or NFC-DEP interface is used, this will be ignored + * + * \return ERR_WRONG_STATE : Incorrect state for this operation + * \return ERR_PARAM : Invalid parameters + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcDataExchangeStart( uint8_t *txData, uint16_t txDataLen, uint8_t **rxData, uint16_t **rvdLen, uint32_t fwt ); + +/*! + ***************************************************************************** + * \brief RFAL NFC Get Data Exchange Status + * + * Gets current Data Exchange status + * + * \return ERR_NONE : Transceive done with no error + * \return ERR_BUSY : Transceive ongoing + * \return ERR_AGAIN : received one chaining block, copy received data + * and continue to call this method to retrieve the + * remaining blocks + * \return ERR_XXXX : Error occurred + * \return ERR_TIMEOUT : No response + * \return ERR_FRAMING : Framing error detected + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_LINK_LOSS : Link Loss - External Field is Off + * \return ERR_RF_COLLISION : Collision detected + * \return ERR_IO : Internal error + ***************************************************************************** + */ +ReturnCode rfalNfcDataExchangeGetStatus( void ); + +/*! + ***************************************************************************** + * \brief RFAL NFC Deactivate + * + * It triggers the deactivation procedure to terminate communications with + * remote device. At the end the field will be turned off. + * + * \param[in] discovery : TRUE if after deactivation go back into discovery + * : FALSE if after deactivation remain in idle + * + * \return ERR_WRONG_STATE : Incorrect state for this operation + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcDeactivate( bool discovery ); + +#endif /* RFAL_NFC_H */ + + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcDep.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcDep.h new file mode 100644 index 0000000..a897555 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcDep.h @@ -0,0 +1,700 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfcDep.h + * + * \author Gustavo Patricio + * + * \brief Implementation of NFC-DEP protocol + * + * NFC-DEP is also known as NFCIP - Near Field Communication + * Interface and Protocol + * + * This implementation was based on the following specs: + * - NFC Forum Digital 1.1 + * - ECMA 340 3rd Edition 2013 + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup NFC-DEP + * \brief RFAL NFC-DEP Module + * @{ + */ + +#ifndef RFAL_NFCDEP_H_ +#define RFAL_NFCDEP_H_ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" + +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ +#define RFAL_NFCDEP_FRAME_SIZE_MAX_LEN 254U /*!< NFCIP Maximum Frame Size Digital 1.0 Table 91 */ +#define RFAL_NFCDEP_DEPREQ_HEADER_LEN 5U /*!< DEP_REQ header length: CMD_TYPE + CMD_CMD + PBF + DID + NAD */ + +/*! Length NFCIP DEP REQ or RES header (incl LEN) */ +#define RFAL_NFCDEP_DEP_HEADER ( RFAL_NFCDEP_LEN_LEN + RFAL_NFCDEP_CMDTYPE_LEN + RFAL_NFCDEP_CMD_LEN + RFAL_NFCDEP_DEP_PFB_LEN ) +#define RFAL_NFCDEP_HEADER ( RFAL_NFCDEP_CMDTYPE_LEN + RFAL_NFCDEP_CMD_LEN ) /*!< NFCIP header length */ +#define RFAL_NFCDEP_SB_LEN 1U /*!< SB length on NFCIP fram for NFC-A */ +#define RFAL_NFCDEP_LEN_LEN 1U /*!< LEN length on NFCIP frame */ +#define RFAL_NFCDEP_CMDTYPE_LEN 1U /*!< Length of the cmd type (REQ | RES) on NFCIP frame */ +#define RFAL_NFCDEP_CMD_LEN 1U /*!< Length of the cmd on NFCIP frame */ +#define RFAL_NFCDEP_DID_LEN 1U /*!< Length of did on NFCIP frame */ +#define RFAL_NFCDEP_DEP_PFB_LEN 1U /*!< Length of the PFB field on NFCIP frame */ + +#define RFAL_NFCDEP_DSL_RLS_LEN_NO_DID (RFAL_NFCDEP_LEN_LEN + RFAL_NFCDEP_CMDTYPE_LEN + RFAL_NFCDEP_CMD_LEN) /*!< Length of DSL_REQ and RLS_REQ with no DID */ +#define RFAL_NFCDEP_DSL_RLS_LEN_DID (RFAL_NFCDEP_DSL_RLS_LEN_NO_DID + RFAL_NFCDEP_DID_LEN) /*!< Length of DSL_REQ and RLS_REQ with DID */ + +#define RFAL_NFCDEP_FS_VAL_MIN 64U /*!< Minimum LR value */ +#define RFAL_NFCDEP_LR_VAL_MASK 0x03U /*!< Bit mask for a LR value */ +#define RFAL_NFCDEP_PP_LR_MASK 0x30U /*!< Bit mask for LR value in PP byte on a ATR REQ/RES */ +#define RFAL_NFCDEP_PP_LR_SHIFT 4U /*!< Position of LR value in PP byte on a ATR REQ/RES */ + +#define RFAL_NFCDEP_DID_MAX 14U /*!< Max DID value Digital 14.6.2.3 */ +#define RFAL_NFCDEP_DID_KEEP 0xFFU /*!< Keep DID value already configured */ +#define RFAL_NFCDEP_DID_NO 0x00U /*!< No DID shall be used */ +#define RFAL_NFCDEP_NAD_NO 0x00U /*!< No NAD shall be used */ + +#define RFAL_NFCDEP_OPER_RTOX_REQ_DIS 0x01U /*!< Operation config: RTOX REQ disable */ +#define RFAL_NFCDEP_OPER_RTOX_REQ_EN 0x00U /*!< Operation config: RTOX REQ enable */ + +#define RFAL_NFCDEP_OPER_ATN_DIS 0x00U /*!< Operation config: ATN disable */ +#define RFAL_NFCDEP_OPER_ATN_EN 0x02U /*!< Operation config: ATN enable */ + +#define RFAL_NFCDEP_OPER_EMPTY_DEP_DIS 0x04U /*!< Operation config: empty DEPs disable */ +#define RFAL_NFCDEP_OPER_EMPTY_DEP_EN 0x00U /*!< Operation config: empty DEPs enable */ + +#define RFAL_NFCDEP_OPER_FULL_MI_DIS 0x00U /*!< Operation config: full chaining DEPs disable */ +#define RFAL_NFCDEP_OPER_FULL_MI_EN 0x08U /*!< Operation config: full chaining DEPs enable */ + + +#define RFAL_NFCDEP_BRS_MAINTAIN 0xC0U /*!< Value signalling that BR is to be maintained (no PSL) */ +#define RFAL_NFCDEP_BRS_Dx_MASK 0x07U /*!< Value signalling that BR is to be maintained (no PSL) */ +#define RFAL_NFCDEP_BRS_DSI_POS 3U /*!< Value signalling that BR is to be maintained (no PSL) */ + +#define RFAL_NFCDEP_WT_DELTA (16U - RFAL_NFCDEP_WT_DELTA_ADJUST) /*!< NFC-DEP dWRT (adjusted) Digital 2.0 B.10 */ +#define RFAL_NFCDEP_WT_DELTA_ADJUST 4U /*!< dWRT value adjustment */ + + +#define RFAL_NFCDEP_ATR_REQ_NFCID3_POS 2U /*!< NFCID3 offset in ATR_REQ frame */ +#define RFAL_NFCDEP_NFCID3_LEN 10U /*!< NFCID3 Length */ + +#define RFAL_NFCDEP_LEN_MIN 3U /*!< Minimum length byte LEN value */ +#define RFAL_NFCDEP_LEN_MAX 255U /*!< Maximum length byte LEN value */ + +#define RFAL_NFCDEP_ATRRES_HEADER_LEN 2U /*!< ATR RES Header Len: CmdType: 0xD5 + Cod: 0x01 */ +#define RFAL_NFCDEP_ATRRES_MIN_LEN 17U /*!< Minimum length for an ATR RES */ +#define RFAL_NFCDEP_ATRRES_MAX_LEN 64U /*!< Maximum length for an ATR RES Digital 1.0 14.6.1 */ +#define RFAL_NFCDEP_ATRREQ_MIN_LEN 16U /*!< Minimum length for an ATR REQ */ +#define RFAL_NFCDEP_ATRREQ_MAX_LEN RFAL_NFCDEP_ATRRES_MAX_LEN /*!< Maximum length for an ATR REQ Digital 1.0 14.6.1 */ + +#define RFAL_NFCDEP_GB_MAX_LEN (RFAL_NFCDEP_ATRREQ_MAX_LEN - RFAL_NFCDEP_ATRREQ_MIN_LEN) /*!< Maximum length the General Bytes on ATR Digital 1.1 16.6.3 */ + +#define RFAL_NFCDEP_WT_INI_DEFAULT RFAL_NFCDEP_WT_INI_MAX /*!< WT Initiator default value Digital 1.0 14.6.3.8 */ +#define RFAL_NFCDEP_WT_INI_MIN 0U /*!< WT Initiator minimum value Digital 1.0 14.6.3.8 */ +#define RFAL_NFCDEP_WT_INI_MAX 14U /*!< WT Initiator maximum value Digital 1.0 14.6.3.8 A.10 */ +#define RFAL_NFCDEP_RWT_INI_MAX rfalNfcDepWT2RWT( RFAL_NFCDEP_WT_INI_MAX ) /*!< RWT Initiator maximum value */ + +#define RFAL_NFCDEP_WT_TRG_MAX_D10 8U /*!< WT target max Digital 1.0 14.6.3.8 A.10 */ +#define RFAL_NFCDEP_WT_TRG_MAX_D11 14U /*!< WT target max Digital 1.1 16.6.3.9 A.9 */ +#define RFAL_NFCDEP_WT_TRG_MAX RFAL_NFCDEP_WT_TRG_MAX_D11 /*!< WT target max Digital x.x */ +#define RFAL_NFCDEP_RWT_TRG_MAX rfalNfcDepWT2RWT( RFAL_NFCDEP_WT_TRG_MAX ) /*!< RWT Initiator maximum value */ + +/*! Maximum Frame Waiting Time = ((256 * 16/fc)*2^FWImax) = ((256*16/fc)*2^14) = (1048576 / 64)/fc = (100000h*64)/fc */ +#define RFAL_NFCDEP_MAX_FWT ((uint32_t)1U<<20) + +#define RFAL_NFCDEP_WT_MASK 0x0FU /*!< Bit mask for the Wait Time value */ + +#define RFAL_NFCDEP_BR_MASK_106 0x01U /*!< Enable mask bit rate 106 */ +#define RFAL_NFCDEP_BR_MASK_212 0x02U /*!< Enable mask bit rate 242 */ +#define RFAL_NFCDEP_BR_MASK_424 0x04U /*!< Enable mask bit rate 424 */ + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + +#define rfalNfcDepWT2RWT( wt ) ( (uint32_t)1U << (((uint32_t)(wt) & RFAL_NFCDEP_WT_MASK) + 12U) ) /*!< Converts WT value to RWT (1/fc) */ + +/*! Returns the BRS value from the given bit rate */ +#define rfalNfcDepDx2BRS( br ) ( (((uint8_t)(br) & RFAL_NFCDEP_BRS_Dx_MASK) << RFAL_NFCDEP_BRS_DSI_POS) | ((uint8_t)(br) & RFAL_NFCDEP_BRS_Dx_MASK) ) + +#define rfalNfcDepBRS2DRI( brs ) (uint8_t)( (uint8_t)(brs) & RFAL_NFCDEP_BRS_Dx_MASK ) /*!< Returns the DRI value from the given BRS byte */ +#define rfalNfcDepBRS2DSI( brs ) (uint8_t)( ((uint8_t)(brs) >> RFAL_NFCDEP_BRS_DSI_POS) & RFAL_NFCDEP_BRS_Dx_MASK ) /*!< Returns the DSI value from the given BRS byte */ + +#define rfalNfcDepPP2LR( PPx ) ( ((uint8_t)(PPx) & RFAL_NFCDEP_PP_LR_MASK ) >> RFAL_NFCDEP_PP_LR_SHIFT) /*!< Returns the LR value from the given PPx byte */ +#define rfalNfcDepLR2PP( LRx ) ( ((uint8_t)(LRx) << RFAL_NFCDEP_PP_LR_SHIFT) & RFAL_NFCDEP_PP_LR_MASK) /*!< Returns the PP byte with the given LRx value */ + +/*! Returns the Frame size value from the given LRx value */ +#define rfalNfcDepLR2FS( LRx ) (uint16_t)(MIN( (RFAL_NFCDEP_FS_VAL_MIN * ((uint16_t)(LRx) + 1U) ), RFAL_NFCDEP_FRAME_SIZE_MAX_LEN )) + +/*! + * Despite DIGITAL 1.0 14.6.2.1 stating that the last two bytes may filled with + * any value, some devices (Samsung Google Nexus) only accept when these are 0 */ +#define rfalNfcDepSetNFCID( dst, src, len ) ST_MEMSET( (dst), 0x00, RFAL_NFCDEP_NFCID3_LEN ); \ + if( (len) > 0U ) {ST_MEMCPY( (dst), (src), (len) );} + +/* + ****************************************************************************** + * GLOBAL ENUMERATIONS + ****************************************************************************** + */ + +/*! Enumeration of NFC-DEP bit rate in ATR Digital 1.0 Table 93 and 94 */ +enum{ + RFAL_NFCDEP_Bx_NO_HIGH_BR = 0x00, /*!< Peer supports no high bit rates */ + RFAL_NFCDEP_Bx_08_848 = 0x01, /*!< Peer also supports 848 */ + RFAL_NFCDEP_Bx_16_1695 = 0x02, /*!< Peer also supports 1695 */ + RFAL_NFCDEP_Bx_32_3390 = 0x04, /*!< Peer also supports 3390 */ + RFAL_NFCDEP_Bx_64_6780 = 0x08 /*!< Peer also supports 6780 */ +}; + +/*! Enumeration of NFC-DEP bit rate Dividor in PSL Digital 1.0 Table 100 */ +enum{ + RFAL_NFCDEP_Dx_01_106 = RFAL_BR_106, /*!< Divisor D = 1 : bit rate = 106 */ + RFAL_NFCDEP_Dx_02_212 = RFAL_BR_212, /*!< Divisor D = 2 : bit rate = 212 */ + RFAL_NFCDEP_Dx_04_424 = RFAL_BR_424, /*!< Divisor D = 4 : bit rate = 424 */ + RFAL_NFCDEP_Dx_08_848 = RFAL_BR_848, /*!< Divisor D = 8 : bit rate = 848 */ + RFAL_NFCDEP_Dx_16_1695 = RFAL_BR_1695, /*!< Divisor D = 16 : bit rate = 1695 */ + RFAL_NFCDEP_Dx_32_3390 = RFAL_BR_3390, /*!< Divisor D = 32 : bit rate = 3390 */ + RFAL_NFCDEP_Dx_64_6780 = RFAL_BR_6780 /*!< Divisor D = 64 : bit rate = 6780 */ +}; + +/*! Enumeration of NFC-DEP Length Reduction (LR) Digital 1.0 Table 91 */ +enum{ + RFAL_NFCDEP_LR_64 = 0x00, /*!< Maximum payload size is 64 bytes */ + RFAL_NFCDEP_LR_128 = 0x01, /*!< Maximum payload size is 128 bytes */ + RFAL_NFCDEP_LR_192 = 0x02, /*!< Maximum payload size is 192 bytes */ + RFAL_NFCDEP_LR_254 = 0x03 /*!< Maximum payload size is 254 bytes */ +}; + +/* + ****************************************************************************** + * GLOBAL DATA TYPES + ****************************************************************************** + */ + +/*! NFC-DEP callback to check if upper layer has deactivation pending */ +typedef bool (* rfalNfcDepDeactCallback)(void); + + +/*! Enumeration of the nfcip communication modes */ +typedef enum{ + RFAL_NFCDEP_COMM_PASSIVE, /*!< Passive communication mode */ + RFAL_NFCDEP_COMM_ACTIVE /*!< Active communication mode */ +} rfalNfcDepCommMode; + + +/*! Enumeration of the nfcip roles */ +typedef enum{ + RFAL_NFCDEP_ROLE_INITIATOR, /*!< Perform as Initiator */ + RFAL_NFCDEP_ROLE_TARGET /*!< Perform as Target */ +} rfalNfcDepRole; + + +/*! Struct that holds all NFCIP configs */ +typedef struct{ + + rfalNfcDepRole role; /*!< Current NFCIP role */ + rfalNfcDepCommMode commMode; /*!< Current NFCIP communication mode */ + uint8_t oper; /*!< Operation config similar to NCI 1.0 Table 81 */ + + uint8_t did; /*!< Current Device ID (DID) */ + uint8_t nad; /*!< Current Node Addressing (NAD) */ + uint8_t bs; /*!< Bit rate in Sending Direction */ + uint8_t br; /*!< Bit rate in Receiving Direction */ + uint8_t nfcid[RFAL_NFCDEP_NFCID3_LEN]; /*!< Pointer to the NFCID to be used */ + uint8_t nfcidLen; /*!< Length of the given NFCID in nfcid */ + uint8_t gb[RFAL_NFCDEP_GB_MAX_LEN]; /*!< Pointer General Bytes (GB) to be used */ + uint8_t gbLen; /*!< Length of the given GB in gb */ + uint8_t lr; /*!< Length Reduction (LR) to be used */ + uint8_t to; /*!< Timeout (TO) to be used */ + uint32_t fwt; /*!< Frame Waiting Time (FWT) to be used */ + uint32_t dFwt; /*!< Delta Frame Waiting Time (dFWT) to be used */ +} rfalNfcDepConfigs; + + +/*! ATR_REQ command Digital 1.1 16.6.2 */ +typedef struct { + uint8_t CMD1; /*!< Command format 0xD4 */ + uint8_t CMD2; /*!< Command Value */ + uint8_t NFCID3[RFAL_NFCDEP_NFCID3_LEN]; /*!< NFCID3 value */ + uint8_t DID; /*!< DID */ + uint8_t BSi; /*!< Sending Bitrate for Initiator */ + uint8_t BRi; /*!< Receiving Bitrate for Initiator */ + uint8_t PPi; /*!< Optional Parameters presence indicator */ + uint8_t GBi[RFAL_NFCDEP_GB_MAX_LEN]; /*!< General Bytes */ +} rfalNfcDepAtrReq; + + +/*! ATR_RES response Digital 1.1 16.6.3 */ +typedef struct { + uint8_t CMD1; /*!< Response Byte 0xD5 */ + uint8_t CMD2; /*!< Command Value */ + uint8_t NFCID3[RFAL_NFCDEP_NFCID3_LEN]; /*!< NFCID3 value */ + uint8_t DID; /*!< DID */ + uint8_t BSt; /*!< Sending Bitrate for Initiator */ + uint8_t BRt; /*!< Receiving Bitrate for Initiator */ + uint8_t TO; /*!< Timeout */ + uint8_t PPt; /*!< Optional Parameters presence indicator */ + uint8_t GBt[RFAL_NFCDEP_GB_MAX_LEN]; /*!< General Bytes */ +} rfalNfcDepAtrRes; + + +/*! Structure of transmit I-PDU Buffer format from caller */ +typedef struct +{ + uint8_t prologue[RFAL_NFCDEP_DEPREQ_HEADER_LEN]; /*!< Prologue space for NFC-DEP header*/ + uint8_t inf[RFAL_NFCDEP_FRAME_SIZE_MAX_LEN]; /*!< INF | Data area of the buffer */ +} rfalNfcDepBufFormat; + + +/*! Activation info as Initiator and Target */ +typedef union { /* PRQA S 0750 # MISRA 19.2 - Both members of the union will not be used concurrently , device is only initiatior or target a time. No problem can occur. */ + struct { + rfalNfcDepAtrRes ATR_RES; /*!< ATR RES (Initiator mode) */ + uint8_t ATR_RESLen; /*!< ATR RES length (Initiator mode) */ + }Target; /*!< Target */ + struct { + rfalNfcDepAtrReq ATR_REQ; /*!< ATR REQ (Target mode) */ + uint8_t ATR_REQLen; /*!< ATR REQ length (Target mode) */ + }Initiator; /*!< Initiator */ +} rfalNfcDepActivation; + + +/*! NFC-DEP device Info */ +typedef struct { + uint8_t GBLen; /*!< General Bytes length */ + uint8_t WT; /*!< WT to be used (ignored in Listen Mode) */ + uint32_t FWT; /*!< FWT to be used (1/fc)(ignored Listen Mode) */ + uint32_t dFWT; /*!< Delta FWT to be used (1/fc) */ + uint8_t LR; /*!< Length Reduction coding the max payload */ + uint16_t FS; /*!< Frame Size */ + rfalBitRate DSI; /*!< Bit Rate coding from Initiator to Target */ + rfalBitRate DRI; /*!< Bit Rate coding from Target to Initiator */ + uint8_t DID; /*!< Device ID (RFAL_NFCDEP_DID_NO if no DID) */ + uint8_t NAD; /*!< Node ADdress (RFAL_NFCDEP_NAD_NO if no NAD)*/ +} rfalNfcDepInfo; + + +/*! NFC-DEP Device structure */ +typedef struct { + rfalNfcDepActivation activation; /*!< Activation Info */ + rfalNfcDepInfo info; /*!< NFC-DEP device Info */ +} rfalNfcDepDevice; + + +/*! NFCIP Protocol structure for P2P Target + * + * operParam : derives from NFC-Forum NCI NFC-DEP Operation Parameter + * NCI 1.1 Table 86: NFC-DEP Operation Parameter + * and it's a bit mask composed as: + * [ 0000b + * | Chain SHALL use max. Transport Data Byte[1b] + * | I-PDU with no Transport Data SHALL NOT be sent [1b] + * | NFC-DEP Target SHALL NOT send RTOX request [1b] + * ] + * + */ +typedef struct{ + rfalNfcDepCommMode commMode; /*!< Initiator in Active P2P or Passive P2P*/ + uint8_t operParam; /*!< NFC-DEP Operation Parameter */ + uint8_t* nfcid; /*!< Initiator's NFCID2 or NFCID3 */ + uint8_t nfcidLen; /*!< Initiator's NFCID length (NFCID2/3) */ + uint8_t DID; /*!< Initiator's Device ID DID */ + uint8_t NAD; /*!< Initiator's Node ID NAD */ + uint8_t BS; /*!< Initiator's Bit Rates supported in Tx */ + uint8_t BitRate; /*!< Initiator's Bit Rates supported in Rx */ + uint8_t LR; /*!< Initiator's Length reduction */ + uint8_t* GB; /*!< Initiator's General Bytes (Gi) */ + uint8_t GBLen; /*!< Initiator's General Bytes length */ +} rfalNfcDepAtrParam; + + +/*! Structure of parameters to be passed in for nfcDepListenStartActivation */ +typedef struct +{ + rfalNfcDepBufFormat *rxBuf; /*!< Receive Buffer struct reference */ + uint16_t *rxLen; /*!< Receive INF data length in bytes */ + bool *isRxChaining; /*!< Received data is not complete */ + rfalNfcDepDevice *nfcDepDev; /*!< NFC-DEP device info */ +} rfalNfcDepListenActvParam; + + +/*! NFCIP Protocol structure for P2P Target + * + * operParam : derives from NFC-Forum NCI NFC-DEP Operation Parameter + * NCI 1.1 Table 86: NFC-DEP Operation Parameter + * and it's a bit mask composed as: + * [ 0000b + * | Chain SHALL use max. Transport Data Byte[1b] + * | I-PDU with no Transport Data SHALL NOT be sent [1b] + * | NFC-DEP Target SHALL NOT send RTOX request [1b] + * ] + * + */ +typedef struct{ + rfalNfcDepCommMode commMode; /*!< Target in Active P2P or Passive P2P */ + uint8_t nfcid3[RFAL_NFCDEP_NFCID3_LEN]; /*!< Target's NFCID3 */ + uint8_t bst; /*!< Target's Bit Rates supported in Tx */ + uint8_t brt; /*!< Target's Bit Rates supported in Rx */ + uint8_t to; /*!< Target's timeout (TO) value */ + uint8_t ppt; /*!< Target's Presence optional Params(PPt)*/ + uint8_t GBt[RFAL_NFCDEP_GB_MAX_LEN]; /*!< Target's General Bytes (Gt) */ + uint8_t GBtLen; /*!< Target's General Bytes length */ + uint8_t operParam; /*!< NFC-DEP Operation Parameter */ +} rfalNfcDepTargetParam; + + +/*! Structure of parameters to be passed in for nfcDepStartIpduTransceive */ +typedef struct +{ + rfalNfcDepBufFormat *txBuf; /*!< Transmit Buffer struct reference */ + uint16_t txBufLen; /*!< Transmit Buffer INF field length in bytes */ + bool isTxChaining; /*!< Transmit data is not complete */ + rfalNfcDepBufFormat *rxBuf; /*!< Receive Buffer struct reference */ + uint16_t *rxLen; /*!< Receive INF data length */ + bool *isRxChaining; /*!< Received data is not complete */ + uint32_t FWT; /*!< FWT to be used (ignored in Listen Mode) */ + uint32_t dFWT; /*!< Delta FWT to be used */ + uint16_t FSx; /*!< Other device Frame Size (FSD or FSC) */ + uint8_t DID; /*!< Device ID (RFAL_ISODEP_NO_DID if no DID) */ +} rfalNfcDepTxRxParam; + + +/* + * ***************************************************************************** + * GLOBAL VARIABLE DECLARATIONS + ****************************************************************************** + */ + + +/* + ****************************************************************************** + * GLOBAL FUNCTION PROTOTYPES + ****************************************************************************** + */ + +/*! + ****************************************************************************** + * \brief NFCIP Initialize + * + * This method resets all NFC-DEP inner states, counters and context and sets + * default values + * + ****************************************************************************** + */ +void rfalNfcDepInitialize( void ); + + +/*! + ****************************************************************************** + * \brief Set deactivating callback + * + * Sets the deactivating callback so that nfcip layer can check if upper layer + * has a deactivation pending, and not perform error recovery upon specific + * errors + * + * \param[in] pFunc : method pointer to deactivation flag check + ****************************************************************************** + */ +void rfalNfcDepSetDeactivatingCallback( rfalNfcDepDeactCallback pFunc ); + + +/*! + ****************************************************************************** + * \brief Calculate Response Waiting Time + * + * Calculates the Response Waiting Time (RWT) from the given Waiting Time (WT) + * + * \param[in] wt : the WT value to calculate RWT + * + * \return RWT value in 1/fc + ****************************************************************************** + */ +uint32_t rfalNfcDepCalculateRWT( uint8_t wt ); + + +/*! + ****************************************************************************** + * \brief NFC-DEP Initiator ATR (Attribute Request) + * + * This method configures the NFC-DEP layer with given parameters and then + * sends an ATR to the Target with and checks for a valid response response + * + * \param[in] param : parameters to initialize and compose the ATR + * \param[out] atrRes : location to store the ATR_RES + * \param[out] atrResLen : length of the ATR_RES received + * + * \return ERR_NONE : No error + * \return ERR_TIMEOUT : Timeout occurred + * \return ERR_PROTO : Protocol error occurred + ****************************************************************************** + */ +ReturnCode rfalNfcDepATR( const rfalNfcDepAtrParam* param, rfalNfcDepAtrRes *atrRes, uint8_t* atrResLen ); + + +/*! + ****************************************************************************** + * \brief NFC-DEP Initiator PSL (Parameter Selection) + * + * This method sends a PSL to the Target with the given parameters and checks + * for a valid response response + * + * The parameters must be coded according to Digital 1.1 16.7.1 + * + * \param[in] BRS : the selected Bit Rates for Initiator and Target + * \param[in] FSL : the maximum length of Commands and Responses + * + * \return ERR_NONE : No error + * \return ERR_TIMEOUT : Timeout occurred + * \return ERR_PROTO : Protocol error occurred + ****************************************************************************** + */ +ReturnCode rfalNfcDepPSL( uint8_t BRS, uint8_t FSL ); + + +/*! + ****************************************************************************** + * \brief NFC-DEP Initiator DSL (Deselect) + * + * This method checks if the NFCIP module is configured as initiator and if + * so sends a DSL REQ, waits the target's response and checks it + * + * In case of performing as target no action is taken + * + * \return ERR_NONE : No error + * \return ERR_TIMEOUT : Timeout occurred + * \return ERR_MAX_RERUNS : Timeout occurred + * \return ERR_PROTO : Protocol error occurred + ****************************************************************************** + */ +ReturnCode rfalNfcDepDSL( void ); + + +/*! + ****************************************************************************** + * \brief NFC-DEP Initiator RLS (Release) + * + * This method checks if the NFCIP module is configured as initiator and if + * so sends a RLS REQ, waits target's response and checks it + * + * In case of performing as target no action is taken + * + * \return ERR_NONE : No error + * \return ERR_TIMEOUT : Timeout occurred + * \return ERR_MAX_RERUNS : Timeout occurred + * \return ERR_PROTO : Protocol error occurred + ****************************************************************************** + */ +ReturnCode rfalNfcDepRLS( void ); + + +/*! + ***************************************************************************** + * \brief NFC-DEP Initiator Handle Activation + * + * This performs a Activation into NFC-DEP layer with the given + * parameters. It sends ATR_REQ and if the higher bit rates are supported by + * both devices it additionally sends PSL + * Once Activated all details of the device are provided on nfcDepDev + * + * \param[in] param : required parameters to initialize and send ATR_REQ + * \param[in] desiredBR : Desired bit rate supported by the Poller + * \param[out] nfcDepDev : NFC-DEP information of the activated Listen device + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, activation successful + ***************************************************************************** + */ +ReturnCode rfalNfcDepInitiatorHandleActivation( rfalNfcDepAtrParam* param, rfalBitRate desiredBR, rfalNfcDepDevice* nfcDepDev ); + + +/*! + ****************************************************************************** + * \brief Check if buffer contains valid ATR_REQ + * + * This method checks if the given ATR_REQ is valid + * + * + * \param[in] buf : buffer holding Initiator's received request + * \param[in] bufLen : size of the msg contained on the buf in Bytes + * \param[out] nfcid3 : pointer to where the NFCID3 may be outputed, + * nfcid3 has NFCF_SENSF_NFCID3_LEN as length + * Pass NULL if output parameter not desired + * + * \return true : Valid ATR_REQ received, the ATR_RES has been computed in txBuf + * \return false : Invalid protocol request + * + ****************************************************************************** + */ +bool rfalNfcDepIsAtrReq( const uint8_t* buf, uint16_t bufLen, uint8_t* nfcid3 ); + + +/*! + ****************************************************************************** + * \brief Check is Target has received ATR + * + * This method checks if the NFCIP module is configured as target and if a + * ATR REQ has been received ( whether is in activation or in data exchange) + * + * \return true : a ATR has already been received + * \return false : no ATR has been received + ****************************************************************************** + */ +bool rfalNfcDepTargetRcvdATR( void ); + +/*! + ***************************************************************************** + * \brief NFCDEP Start Listen Activation Handling + * + * Start Activation Handling and setup to receive first frame which may + * contain complete or partial DEP-REQ after activation is completed + * + * Pass in ATR_REQ for NFC-DEP to handle ATR_RES. The Activation Handling + * handles ATR_RES and PSL_RES if a PSL_REQ is received + * + * Activation is completed if PSL_RES is sent or if first I-PDU is received + * + * \ref rfalNfcDepListenGetActivationStatus() provide status of the + * ongoing activation + * + * \warning nfcDepGetTransceiveStatus() shall be called right after activation + * is completed (i.e. rfalNfcDepListenGetActivationStatus() return ERR_NONE) + * to check for first received frame. + * + * \param[in] param : Target parameters to be used + * \param[in] atrReq : reference to buffer containing ATR_REQ + * \param[in] atrReqLength: Length of ATR_REQ + * \param[out] rxParam : references to buffer, length and chaining indication + * for first complete LLCP to be received + * + * \return ERR_NONE : ATR_REQ is valid and activation ongoing + * \return ERR_PARAM : ATR_REQ or other params are invalid + * \return ERR_LINK_LOSS : Remote Field is turned off + ***************************************************************************** + */ +ReturnCode rfalNfcDepListenStartActivation( const rfalNfcDepTargetParam *param, const uint8_t *atrReq, uint16_t atrReqLength, rfalNfcDepListenActvParam rxParam ); + + +/*! + ***************************************************************************** + * \brief Get the current NFC-DEP Activation Status + * + * \return ERR_NONE : Activation has completed successfully + * \return ERR_BUSY : Activation is ongoing + * \return ERR_LINK_LOSS : Remote Field was turned off + ***************************************************************************** + */ +ReturnCode rfalNfcDepListenGetActivationStatus( void ); + +/*! + ***************************************************************************** + * \brief Start Transceive + * + * Transceives a complete or partial DEP block + * + * The txBuf contains complete or partial of DEP to be transmitted. + * The Prologue field of the I-PDU is handled internally + * + * If the buffer contains partial LLCP and is not the last block, then + * isTxChaining must be set to true + * + * \param[in] param: reference parameters to be used for the Transceive + * + * \return ERR_PARAM : Bad request + * \return ERR_WRONG_STATE : The module is not in a proper state + * \return ERR_NONE : The Transceive request has been started + ***************************************************************************** + */ +ReturnCode rfalNfcDepStartTransceive( rfalNfcDepTxRxParam *param ); + + +/*! + ***************************************************************************** + * \brief Return the Transceive status + * + * Returns the status of the NFC-DEP Transceive + * + * \warning When the other device is performing chaining once a chained + * block is received the error ERR_AGAIN is sent. At this point + * caller must handle the received data immediately. + * When ERR_AGAIN is returned an ACK has already been sent to + * the other device and the next block might be incoming. + * If rfalWorker() is called frequently it will place the next + * block on the given buffer + * + * \return ERR_NONE : Transceive has been completed successfully + * \return ERR_BUSY : Transceive is ongoing + * \return ERR_PROTO : Protocol error occurred + * \return ERR_TIMEOUT : Timeout error occurred + * \return ERR_SLEEP_REQ : Deselect has been received and responded + * \return ERR_NOMEM : The received I-PDU does not fit into the + * receive buffer + * \return ERR_LINK_LOSS : Communication is lost because Reader/Writer + * has turned off its field + * \return ERR_AGAIN : received one chaining block, continue to call + * this method to retrieve the remaining blocks + ***************************************************************************** + */ +ReturnCode rfalNfcDepGetTransceiveStatus( void ); + + +#endif /* RFAL_NFCDEP_H_ */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_nfca.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfca.h new file mode 100644 index 0000000..d834fce --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfca.h @@ -0,0 +1,391 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfca.h + * + * \author Gustavo Patricio + * + * \brief Provides several NFC-A convenience methods and definitions + * + * It provides a Poller (ISO14443A PCD) interface and as well as + * some NFC-A Listener (ISO14443A PICC) helpers. + * + * The definitions and helpers methods provided by this module are only + * up to ISO14443-3 layer + * + * + * An usage example is provided here: \ref exampleRfalNfca.c + * \example exampleRfalNfca.c + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup NFC-A + * \brief RFAL NFC-A Module + * @{ + * + */ + + +#ifndef RFAL_NFCA_H +#define RFAL_NFCA_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" +#include "rfal_t1t.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_NFCA_CASCADE_1_UID_LEN 4U /*!< UID length of cascade level 1 only tag */ +#define RFAL_NFCA_CASCADE_2_UID_LEN 7U /*!< UID length of cascade level 2 only tag */ +#define RFAL_NFCA_CASCADE_3_UID_LEN 10U /*!< UID length of cascade level 3 only tag */ + +#define RFAL_NFCA_SENS_RES_PLATFORM_MASK 0x0FU /*!< SENS_RES (ATQA) platform configuration mask Digital 1.1 Table 10 */ +#define RFAL_NFCA_SENS_RES_PLATFORM_T1T 0x0CU /*!< SENS_RES (ATQA) T1T platform configuration Digital 1.1 Table 10 */ + +#define RFAL_NFCA_SEL_RES_CONF_MASK 0x60U /*!< SEL_RES (SAK) platform configuration mask Digital 1.1 Table 19 */ +#define RFAL_NFCA_SEL_RES_CONF_T2T 0x00U /*!< SEL_RES (SAK) T2T configuration Digital 1.1 Table 19 */ +#define RFAL_NFCA_SEL_RES_CONF_T4T 0x20U /*!< SEL_RES (SAK) T4T configuration Digital 1.1 Table 19 */ +#define RFAL_NFCA_SEL_RES_CONF_NFCDEP 0x40U /*!< SEL_RES (SAK) NFC-DEP configuration Digital 1.1 Table 19 */ +#define RFAL_NFCA_SEL_RES_CONF_T4T_NFCDEP 0x60U /*!< SEL_RES (SAK) T4T and NFC-DEP configuration Digital 1.1 Table 19 */ + + +/*! NFC-A minimum FDT(listen) = ((n * 128 + (84)) / fc) with n_min = 9 Digital 1.1 6.10.1 + * = (1236)/fc + * Relax with 3etu: (3*128)/fc as with multiple NFC-A cards, response may take longer (JCOP cards) + * = (1236 + 384)/fc = 1620 / fc */ +#define RFAL_NFCA_FDTMIN 1620U +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + +/*! Checks if device is a T1T given its SENS_RES */ +#define rfalNfcaIsSensResT1T( sensRes ) ((((rfalNfcaSensRes*)(sensRes))->platformInfo & RFAL_NFCA_SENS_RES_PLATFORM_MASK) == RFAL_NFCA_SENS_RES_PLATFORM_T1T ) + +/*! Checks if device is a T2T given its SENS_RES */ +#define rfalNfcaIsSelResT2T( selRes ) ((((rfalNfcaSelRes*)(selRes))->sak & RFAL_NFCA_SEL_RES_CONF_MASK) == RFAL_NFCA_SEL_RES_CONF_T2T ) + +/*! Checks if device is a T4T given its SENS_RES */ +#define rfalNfcaIsSelResT4T( selRes ) ((((rfalNfcaSelRes*)(selRes))->sak & RFAL_NFCA_SEL_RES_CONF_MASK) == RFAL_NFCA_SEL_RES_CONF_T4T ) + +/*! Checks if device supports NFC-DEP protocol given its SENS_RES */ +#define rfalNfcaIsSelResNFCDEP( selRes ) ((((rfalNfcaSelRes*)(selRes))->sak & RFAL_NFCA_SEL_RES_CONF_MASK) == RFAL_NFCA_SEL_RES_CONF_NFCDEP ) + +/*! Checks if device supports ISO-DEP and NFC-DEP protocol given its SENS_RES */ +#define rfalNfcaIsSelResT4TNFCDEP( selRes ) ((((rfalNfcaSelRes*)(selRes))->sak & RFAL_NFCA_SEL_RES_CONF_MASK) == RFAL_NFCA_SEL_RES_CONF_T4T_NFCDEP ) + +/*! Checks if a NFC-A listener device supports multiple protocols (ISO-DEP and NFC-DEP) */ +#define rfalNfcaLisDevIsMultiProto( lisDev ) (((rfalNfcaListenDevice*)(lisDev))->type == RFAL_NFCA_T4T_NFCDEP ) + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! NFC-A Listen device types */ +typedef enum { + RFAL_NFCA_T1T = 0x01, /* Device configured for T1T Digital 1.1 Table 9 */ + RFAL_NFCA_T2T = 0x00, /* Device configured for T2T Digital 1.1 Table 19 */ + RFAL_NFCA_T4T = 0x20, /* Device configured for T4T Digital 1.1 Table 19 */ + RFAL_NFCA_NFCDEP = 0x40, /* Device configured for NFC-DEP Digital 1.1 Table 19 */ + RFAL_NFCA_T4T_NFCDEP = 0x60 /* Device configured for NFC-DEP and T4T Digital 1.1 Table 19 */ +} rfalNfcaListenDeviceType; + + +/*! SENS_RES (ATQA) format Digital 1.1 6.6.3 & Table 7 */ +typedef struct +{ + uint8_t anticollisionInfo; /*!< SENS_RES Anticollision Information */ + uint8_t platformInfo; /*!< SENS_RES Platform Information */ +} rfalNfcaSensRes; + + +/*! SDD_REQ (Anticollision) format Digital 1.1 6.7.1 & Table 11 */ +typedef struct +{ + uint8_t selCmd; /*!< SDD_REQ SEL_CMD: cascade Level */ + uint8_t selPar; /*!< SDD_REQ SEL_PAR: Byte Count[4b] | Bit Count[4b] (NVB: Number of Valid Bits)*/ +} rfalNfcaSddReq; + + +/*! SDD_RES (UID CLn) format Digital 1.1 6.7.2 & Table 15 */ +typedef struct +{ + uint8_t nfcid1[RFAL_NFCA_CASCADE_1_UID_LEN]; /*!< NFCID1 cascade level NFCID */ + uint8_t bcc; /*!< BCC Exclusive-OR over first 4 bytes of SDD_RES */ +} rfalNfcaSddRes; + + +/*! SEL_REQ (Select) format Digital 1.1 6.8.1 & Table 17 */ +typedef struct +{ + uint8_t selCmd; /*!< SDD_REQ SEL_CMD: cascade Level */ + uint8_t selPar; /*!< SDD_REQ SEL_PAR: Byte Count[4b] | Bit Count[4b] (NVB: Number of Valid Bits)*/ + uint8_t nfcid1[RFAL_NFCA_CASCADE_1_UID_LEN]; /*!< NFCID1 data */ + uint8_t bcc; /*!< Checksum calculated as exclusive-OR over the 4 bytes of NFCID1 CLn */ +} rfalNfcaSelReq; + + +/*! SEL_RES (SAK) format Digital 1.1 6.8.2 & Table 19 */ +typedef struct +{ + uint8_t sak; /*!< Select Acknowledge */ +} rfalNfcaSelRes; + + +/*! NFC-A listener device (PICC) struct */ +typedef struct +{ + rfalNfcaListenDeviceType type; /*!< NFC-A Listen device type */ + rfalNfcaSensRes sensRes; /*!< SENS_RES (ATQA) */ + rfalNfcaSelRes selRes; /*!< SEL_RES (SAK) */ + uint8_t nfcId1Len; /*!< NFCID1 Length */ + uint8_t nfcId1[RFAL_NFCA_CASCADE_3_UID_LEN]; /*!< NFCID1 (UID) */ +#ifdef RFAL_FEATURE_T1T + rfalT1TRidRes ridRes; /*!< RID_RES */ +#endif /* RFAL_FEATURE_T1T */ + bool isSleep; /*!< Device sleeping flag */ +} rfalNfcaListenDevice; + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/*! + ***************************************************************************** + * \brief Initialize NFC-A Poller mode + * + * This methods configures RFAL RF layer to perform as a + * NFC-A Poller/RW (ISO14443A PCD) including all default timings and bit rate + * to 106 kbps + + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcaPollerInitialize( void ); + + +/*! + ***************************************************************************** + * \brief NFC-A Poller Check Presence + * + * This method checks if a NFC-A Listen device (PICC) is present on the field + * by sending an ALL_REQ (WUPA) or SENS_REQ (REQA) + * + * \param[in] cmd : Indicate if to send an ALL_REQ or a SENS_REQ + * \param[out] sensRes : If received, the SENS_RES + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_RF_COLLISION : Collision detected one or more device in the field + * \return ERR_PAR : Parity error detected, one or more device in the field + * \return ERR_CRC : CRC error detected, one or more device in the field + * \return ERR_FRAMING : Framing error detected, one or more device in the field + * \return ERR_PROTO : Protocol error detected, one or more device in the field + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_NONE : No error, one or more device in the field + ***************************************************************************** + */ +ReturnCode rfalNfcaPollerCheckPresence( rfal14443AShortFrameCmd cmd, rfalNfcaSensRes *sensRes ); + + +/*! + ***************************************************************************** + * \brief NFC-A Poller Select + * + * This method selects a NFC-A Listener device (PICC) + * + * \param[in] nfcid1 : Listener device NFCID1 to be selected + * \param[in] nfcidLen : Length of the NFCID1 to be selected + * \param[out] selRes : pointer to place the SEL_RES + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, SEL_RES received + ***************************************************************************** + */ +ReturnCode rfalNfcaPollerSelect( const uint8_t *nfcid1, uint8_t nfcidLen, rfalNfcaSelRes *selRes ); + + +/*! + ***************************************************************************** + * \brief NFC-A Poller Sleep + * + * This method sends a SLP_REQ (HLTA) + * No response is expected afterwards Digital 1.1 6.9.2.1 + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcaPollerSleep( void ); + + +/*! + ***************************************************************************** + * \brief NFC-A Technology Detection + * + * This method performs NFC-A Technology Detection as defined in the spec + * given in the compliance mode + * + * \param[in] compMode : compliance mode to be performed + * \param[out] sensRes : location to store the SENS_RES, if received + * + * When compMode is set to ISO compliance a SLP_REQ (HLTA) is not sent + * after detection. When set to EMV a ALL_REQ (WUPA) is sent instead of + * a SENS_REQ (REQA) + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_NONE : No error, one or more device in the field + ***************************************************************************** + */ +ReturnCode rfalNfcaPollerTechnologyDetection( rfalComplianceMode compMode, rfalNfcaSensRes *sensRes ); + + +/*! + ***************************************************************************** + * \brief NFC-A Poller Collision Resolution + * + * Collision resolution for one NFC-A Listener device/card (PICC) as + * defined in Activity 1.1 9.3.4 + * + * This method executes anti collision loop and select the device with higher NFCID1 + * + * When devLimit = 0 it is configured to perform collision detection only. Once a collision + * is detected the collision resolution is aborted immidiatly. If only one device is found + * with no collisions, it will properly resolved. + * + * \param[in] devLimit : device limit value (CON_DEVICES_LIMIT) + * \param[out] collPending : pointer to collision pending flag (INT_COLL_PEND) + * \param[out] selRes : location to store the last Select Response from listener device (PICC) + * \param[out] nfcId1 : location to store the NFCID1 (UID), ensure RFAL_NFCA_CASCADE_3_UID_LEN + * \param[out] nfcId1Len : pointer to length of NFCID1 (UID) + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_PROTO : Card length invalid + * \return ERR_IGNORE : conDevLimit is 0 and there is a collision + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcaPollerSingleCollisionResolution( uint8_t devLimit, bool *collPending, rfalNfcaSelRes *selRes, uint8_t *nfcId1, uint8_t *nfcId1Len ); + + +/*! + ***************************************************************************** + * \brief NFC-A Poller Full Collision Resolution + * + * Performs a full Collision resolution as defined in Activity 1.0 or 1.1 9.3.4 + * + * \param[in] compMode : compliance mode to be performed + * \param[in] devLimit : device limit value, and size nfcaDevList + * \param[out] nfcaDevList : NFC-A listener device info + * \param[out] devCnt : Devices found counter + * + * When compMode is set to ISO compliance it assumes that the device is + * not sleeping and therefore no ALL_REQ (WUPA) is sent at the beginning. + * + * When compMode is set to NFC compliance an additional ALL_REQ (WUPA) is sent at + * the beginning and a proprietary behaviour also takes place. Once a device has been + * resolved an additional SLP_REQ (HLTA) is sent regardless if there was a collision + * (except if the number of devices found already equals the limit). + * This proprietary behaviour ensures proper activation of certain devices that suffer + * from influence of Type B commands as foreseen in ISO14443-3 5.2.3 + * + * + * When devLimit = 0 it is configured to perform collision detection only. Once a collision + * is detected the collision resolution is aborted immidiatly. If only one device is found + * with no collisions, it will properly resolved. + * + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcaPollerFullCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcaListenDevice *nfcaDevList, uint8_t *devCnt ); + + +/*! + ***************************************************************************** + * \brief NFC-A Listener is SLP_REQ + * + * Checks if the given buffer contains valid NFC-A SLP_REQ (HALT) + * + * \param[in] buf: buffer containing data + * \param[in] bufLen: length of the data in buffer to be checked + * + * \return true if data in buf contains a SLP_REQ ; false otherwise + ***************************************************************************** + */ +bool rfalNfcaListenerIsSleepReq( const uint8_t *buf, uint16_t bufLen ); + +#endif /* RFAL_NFCA_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcb.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcb.h new file mode 100644 index 0000000..ea4cab0 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcb.h @@ -0,0 +1,398 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfcb.h + * + * \author Gustavo Patricio + * + * \brief Implementation of NFC-B (ISO14443B) helpers + * + * It provides a NFC-B Poller (ISO14443B PCD) interface and + * also provides some NFC-B Listener (ISO14443B PICC) helpers + * + * The definitions and helpers methods provided by this module are only + * up to ISO14443-3 layer (excluding ATTRIB) + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup NFC-B + * \brief RFAL NFC-B Module + * @{ + * + */ + + +#ifndef RFAL_NFCB_H +#define RFAL_NFCB_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_NFCB_FWTSENSB 7680U /*!< NFC-B FWT(SENSB) Digital 2.0 B.3 */ +#define RFAL_NFCB_DFWT 49152U /*!< NFC-B dFWT Delta 2.0 7.9.1.3 & B.3 */ +#define RFAL_NFCB_DTPOLL_10 rfalConvMsTo1fc(20) /*!< NFC-B Delta Tb Poll Digital 1.0 A.2 */ +#define RFAL_NFCB_DTPOLL_20 rfalConvMsTo1fc(17) /*!< NFC-B Delta Tb Poll Digital 2.1 B.3 */ + +#define RFAL_NFCB_AFI 0x00U /*!< NFC-B default Application Family Digital 1.1 7.6.1.1 */ +#define RFAL_NFCB_PARAM 0x00U /*!< NFC-B default SENSB_REQ PARAM */ +#define RFAL_NFCB_CRC_LEN 2U /*!< NFC-B CRC length and CRC_B(AID) Digital 1.1 Table 28 */ +#define RFAL_NFCB_NFCID0_LEN 4U /*!< Length of NFC-B NFCID0 */ +#define RFAL_NFCB_CMD_LEN 1U /*!< Length of NFC-B Command */ + +#define RFAL_NFCB_SENSB_RES_LEN 12U /*!< Standard length of SENSB_RES without SFGI byte */ +#define RFAL_NFCB_SENSB_RES_EXT_LEN 13U /*!< Extended length of SENSB_RES with SFGI byte */ + +#define RFAL_NFCB_SENSB_REQ_ADV_FEATURE 0x20U /*!< Bit mask for Advance Feature in SENSB_REQ */ +#define RFAL_NFCB_SENSB_RES_FSCI_MASK 0x0FU /*!< Bit mask for FSCI value in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_FSCI_SHIFT 4U /*!< Shift for FSCI value in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_PROTO_RFU_MASK 0x08U /*!< Bit mask for Protocol Type RFU in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_PROTO_TR2_MASK 0x03U /*!< Bit mask for Protocol Type TR2 in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_PROTO_TR2_SHIFT 1U /*!< Shift for Protocol Type TR2 in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_PROTO_ISO_MASK 0x01U /*!< Bit mask Protocol Type ISO14443 Compliant in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_FWI_MASK 0x0FU /*!< Bit mask for FWI value in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_FWI_SHIFT 4U /*!< Bit mask for FWI value in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_ADC_MASK 0x0CU /*!< Bit mask for ADC value in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_ADC_ADV_FEATURE_MASK 0x08U /*!< Bit mask for ADC.Advanced Proto Features in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_ADC_PROPRIETARY_MASK 0x04U /*!< Bit mask for ADC.Proprietary Application in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_FO_DID_MASK 0x01U /*!< Bit mask for DID in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_FO_NAD_MASK 0x02U /*!< Bit mask for DID in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_FO_MASK 0x03U /*!< Bit mask for FO value in SENSB_RES (NAD and DID) */ +#define RFAL_NFCB_SENSB_RES_SFGI_MASK 0x0FU /*!< Bit mask for SFGI in SENSB_RES */ +#define RFAL_NFCB_SENSB_RES_SFGI_SHIFT 4U /*!< Shift for SFGI in SENSB_RES */ + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ + +/*! Get device's FSCI given its SENSB_RES Digital 1.1 7.6.2 */ +#define rfalNfcbGetFSCI( sensbRes ) ((((rfalNfcbSensbRes*)(sensbRes))->protInfo.FsciProType >> RFAL_NFCB_SENSB_RES_FSCI_SHIFT) & RFAL_NFCB_SENSB_RES_FSCI_MASK ) + +/*! Checks if the given NFC-B device indicates ISO-DEP support */ +#define rfalNfcbIsIsoDepSupported( dev ) ( (((rfalNfcbListenDevice*)(dev))->sensbRes.protInfo.FsciProType & RFAL_NFCB_SENSB_RES_PROTO_ISO_MASK) != 0U ) + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! SENSB_REQ and ALLB_REQ param Digital 1.1 7.6.1 */ +typedef enum +{ + RFAL_NFCB_SENS_CMD_ALLB_REQ = 0x08, /*!< ALLB_REQ (WUPB) */ + RFAL_NFCB_SENS_CMD_SENSB_REQ = 0x00 /*!< SENSB_REQ (REQB) */ +} rfalNfcbSensCmd; + + +/*! Number of Slots (NI) codes used for NFC-B anti collision Digital 1.1 Table 26 */ +typedef enum +{ + RFAL_NFCB_SLOT_NUM_1 = 0, /*!< N=0 : 1 slot */ + RFAL_NFCB_SLOT_NUM_2 = 1, /*!< N=1 : 2 slots */ + RFAL_NFCB_SLOT_NUM_4 = 2, /*!< N=2 : 4 slots */ + RFAL_NFCB_SLOT_NUM_8 = 3, /*!< N=3 : 8 slots */ + RFAL_NFCB_SLOT_NUM_16 = 4 /*!< N=4 : 16 slots */ +}rfalNfcbSlots; + + +/*! SENSB_RES (ATQB) Application Data Format Digital 1.1 Table 28 */ +typedef struct +{ + uint8_t AFI; /*!< Application Family Identifier */ + uint8_t CRC_B[RFAL_NFCB_CRC_LEN]; /*!< CRC_B of AID */ + uint8_t numApps; /*!< Number of Applications */ +} rfalNfcbSensbResAppData; + + +/*! SENSB_RES Protocol Info format Digital 1.1 Table 29 */ +typedef struct +{ + uint8_t BRC; /*!< Bit Rate Capability */ + uint8_t FsciProType; /*!< Frame Size Card Integer [4b] | Protocol Type[4 bits] */ + uint8_t FwiAdcFo; /*!< Frame Waiting Integer [4b] | Application Data Coding [2b] | Frame Options [2b] */ + uint8_t SFGI; /*!< Optional: Start-Up Frame Guard Time Integer[4b] | RFU [4b] */ +} rfalNfcbSensbResProtocolInfo; + + +/*! SENSB_RES format Digital 1.1 7.6.2 */ +typedef struct +{ + uint8_t cmd; /*!< SENSB_RES: 50h */ + uint8_t nfcid0[RFAL_NFCB_NFCID0_LEN]; /*!< NFC Identifier (PUPI)*/ + rfalNfcbSensbResAppData appData; /*!< Application Data */ + rfalNfcbSensbResProtocolInfo protInfo; /*!< Protocol Information */ +} rfalNfcbSensbRes; + + +/*! NFC-B listener device (PICC) struct */ +typedef struct +{ + uint8_t sensbResLen; /*!< SENSB_RES length */ + rfalNfcbSensbRes sensbRes; /*!< SENSB_RES */ + bool isSleep; /*!< Device sleeping flag */ +}rfalNfcbListenDevice; + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/*! + ***************************************************************************** + * \brief Initialize NFC-B Poller mode + * + * This methods configures RFAL RF layer to perform as a + * NFC-B Poller/RW (ISO14443B PCD) including all default timings + * + * It sets NFC-B parameters (AFI, PARAM) to default values + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcbPollerInitialize( void ); + + +/*! + ***************************************************************************** + * \brief Set NFC-B Poller parameters + * + * This methods configures RFAL RF layer to perform as a + * NFCA Poller/RW (ISO14443A PCD) including all default timings + * + * Additionally configures NFC-B specific parameters to be used on the + * following communications + * + * \param[in] AFI : Application Family Identifier to be used + * \param[in] PARAM : PARAM to be used, it announces whether Advanced + * Features or Extended SENSB_RES is supported + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcbPollerInitializeWithParams( uint8_t AFI, uint8_t PARAM ); + + +/*! + ***************************************************************************** + * \brief NFC-B Poller Check Presence + * + * This method checks if a NFC-B Listen device (PICC) is present on the field + * by sending an ALLB_REQ (WUPB) or SENSB_REQ (REQB) + * + * \param[in] cmd : Indicate if to send an ALL_REQ or a SENS_REQ + * \param[in] slots : The number of slots to be announced + * \param[out] sensbRes : If received, the SENSB_RES + * \param[out] sensbResLen : If received, the SENSB_RES length + * + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_RF_COLLISION : Collision detected one or more device in the field + * \return ERR_PAR : Parity error detected, one or more device in the field + * \return ERR_CRC : CRC error detected, one or more device in the field + * \return ERR_FRAMING : Framing error detected, one or more device in the field + * \return ERR_PROTO : Protocol error detected, invalid SENSB_RES received + * \return ERR_NONE : No error, SENSB_RES received + ***************************************************************************** + */ +ReturnCode rfalNfcbPollerCheckPresence( rfalNfcbSensCmd cmd, rfalNfcbSlots slots, rfalNfcbSensbRes *sensbRes, uint8_t *sensbResLen ); + + +/*! + ***************************************************************************** + * \brief NFC-B Poller Sleep + * + * This function is used to send the SLPB_REQ (HLTB) command to put the PICC with + * the given NFCID0 to state HALT so that they do not reply to further SENSB_REQ + * commands (only to ALLB_REQ) + * + * \param[in] nfcid0 : NFCID of the device to be put to Sleep + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcbPollerSleep( const uint8_t* nfcid0 ); + + +/*! + ***************************************************************************** + * \brief NFC-B Poller Slot Marker + * + * This method selects a NFC-B Slot marker frame + * + * \param[in] slotCode : Slot Code [1-15] + * \param[out] sensbRes : If received, the SENSB_RES + * \param[out] sensbResLen : If received, the SENSB_RES length + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, SEL_RES received + ***************************************************************************** + */ +ReturnCode rfalNfcbPollerSlotMarker( uint8_t slotCode, rfalNfcbSensbRes *sensbRes, uint8_t *sensbResLen ); + +/*! + ***************************************************************************** + * \brief NFC-B Technology Detection + * + * This method performs NFC-B Technology Detection as defined in the spec + * given in the compliance mode + * + * \param[in] compMode : compliance mode to be performed + * \param[out] sensbRes : location to store the SENSB_RES, if received + * \param[out] sensbResLen : length of the SENSB_RES, if received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_NONE : No error, one or more device in the field + ***************************************************************************** + */ +ReturnCode rfalNfcbPollerTechnologyDetection( rfalComplianceMode compMode, rfalNfcbSensbRes *sensbRes, uint8_t *sensbResLen ); + +/*! + ***************************************************************************** + * \brief NFC-B Poller Collision Resolution + * + * NFC-B Collision resolution Listener device/card (PICC) as + * defined in Activity 1.1 9.3.5 + * + * This function is used to perform collision resolution for detection in case + * of multiple NFC Forum Devices with Technology B detected. + * Target with valid SENSB_RES will be stored in devInfo and nfcbDevCount incremented. + * + * \param[in] compMode : compliance mode to be performed + * \param[in] devLimit : device limit value, and size nfcbDevList + * \param[out] nfcbDevList : NFC-B listener device info + * \param[out] devCnt : devices found counter + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcbPollerCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcbListenDevice *nfcbDevList, uint8_t *devCnt ); + +/*! + ***************************************************************************** + * \brief NFC-B Poller Collision Resolution Slotted + * + * NFC-B Collision resolution Listener device/card (PICC). The sequence can + * be configured to be according to NFC Forum Activity 1.1 9.3.5, ISO10373 + * or EMVCo + * + * This function is used to perform collision resolution for detection in case + * of multiple NFC Forum Devices with Technology B are detected. + * Target with valid SENSB_RES will be stored in devInfo and nfcbDevCount incremented. + * + * This method provides the means to perform a collision resolution loop with specific + * initial and end number of slots. This allows to user to start the loop already with + * greater number of slots, and or limit the end number of slots. At the end a flag + * indicating whether there were collisions pending is returned. + * + * If RFAL_COMPLIANCE_MODE_ISO is used \a initSlots must be set to RFAL_NFCB_SLOT_NUM_1 + * + * + * \param[in] compMode : compliance mode to be performed + * \param[in] devLimit : device limit value, and size nfcbDevList + * \param[in] initSlots : number of slots to open initially + * \param[in] endSlots : number of slots when to stop collision resolution + * \param[out] nfcbDevList : NFC-B listener device info + * \param[out] devCnt : devices found counter + * \param[out] colPending : flag indicating whether collision are still pending + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcbPollerSlottedCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcbSlots initSlots, rfalNfcbSlots endSlots, rfalNfcbListenDevice *nfcbDevList, uint8_t *devCnt, bool *colPending ); + + +/*! + ***************************************************************************** + * \brief NFC-B TR2 code to FDT + * + * Converts the TR2 code as defined in Digital 1.1 Table 33 Minimum + * TR2 Coding to Frame Delay Time (FDT) in 1/Fc + * + * \param[in] tr2Code : TR2 code as defined in Digital 1.1 Table 33 + * + * \return FDT in 1/Fc + ***************************************************************************** + */ +uint32_t rfalNfcbTR2ToFDT( uint8_t tr2Code ); + + +#endif /* RFAL_NFCB_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcf.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcf.h new file mode 100644 index 0000000..936f941 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcf.h @@ -0,0 +1,370 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfcf.h + * + * \author Gustavo Patricio + * + * \brief Implementation of NFC-F Poller (FeliCa PCD) device + * + * The definitions and helpers methods provided by this module are + * aligned with NFC-F (FeliCa - JIS X6319-4) + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup NFC-F + * \brief RFAL NFC-F Module + * @{ + * + */ + + +#ifndef RFAL_NFCF_H +#define RFAL_NFCF_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_NFCF_NFCID2_LEN 8U /*!< NFCID2 (FeliCa IDm) length */ +#define RFAL_NFCF_SENSF_RES_LEN_MIN 16U /*!< SENSF_RES minimum length */ +#define RFAL_NFCF_SENSF_RES_LEN_MAX 18U /*!< SENSF_RES maximum length */ +#define RFAL_NFCF_SENSF_RES_PAD0_LEN 2U /*!< SENSF_RES PAD0 length */ +#define RFAL_NFCF_SENSF_RES_PAD1_LEN 2U /*!< SENSF_RES PAD1 length */ +#define RFAL_NFCF_SENSF_RES_RD_LEN 2U /*!< SENSF_RES Request Data length */ +#define RFAL_NFCF_SENSF_RES_BYTE1 1U /*!< SENSF_RES first byte value */ +#define RFAL_NFCF_SENSF_SC_LEN 2U /*!< Felica SENSF_REQ System Code length */ +#define RFAL_NFCF_SENSF_PARAMS_SC1_POS 0U /*!< System Code byte1 position in the SENSF_REQ */ +#define RFAL_NFCF_SENSF_PARAMS_SC2_POS 1U /*!< System Code byte2 position in the SENSF_REQ */ +#define RFAL_NFCF_SENSF_PARAMS_RC_POS 2U /*!< Request Code position in the SENSF_REQ */ +#define RFAL_NFCF_SENSF_PARAMS_TSN_POS 3U /*!< Time Slot Number position in the SENSF_REQ */ +#define RFAL_NFCF_POLL_MAXCARDS 16U /*!< Max number slots/cards 16 */ + + +#define RFAL_NFCF_CMD_POS 0U /*!< Command/Responce code length */ +#define RFAL_NFCF_CMD_LEN 1U /*!< Command/Responce code length */ +#define RFAL_NFCF_LENGTH_LEN 1U /*!< LEN field length */ +#define RFAL_NFCF_HEADER_LEN (RFAL_NFCF_LENGTH_LEN + RFAL_NFCF_CMD_LEN) /*!< Header length*/ + + +#define RFAL_NFCF_SENSF_NFCID2_BYTE1_POS 0U /*!< NFCID2 byte1 position */ +#define RFAL_NFCF_SENSF_NFCID2_BYTE2_POS 1U /*!< NFCID2 byte2 position */ + +#define RFAL_NFCF_SENSF_NFCID2_PROT_TYPE_LEN 2U /*!< NFCID2 length for byte 1 and byte 2 indicating NFC-DEP or T3T support */ +#define RFAL_NFCF_SENSF_NFCID2_BYTE1_NFCDEP 0x01U /*!< NFCID2 byte1 NFC-DEP support Digital 1.0 Table 44 */ +#define RFAL_NFCF_SENSF_NFCID2_BYTE2_NFCDEP 0xFEU /*!< NFCID2 byte2 NFC-DEP support Digital 1.0 Table 44 */ + +#define RFAL_NFCF_SYSTEMCODE 0xFFFFU /*!< SENSF_RES Default System Code Digital 1.0 6.6.1.1 */ + +#define RFAL_NFCF_BLOCK_LEN 16U /*!< NFCF T3T Block size T3T 1.0 4.1 */ +#define RFAL_NFCF_CHECKUPDATE_RES_ST1_POS 9U /*!< Check|Update Res Status Flag 1 position T3T 1.0 Table 8 */ +#define RFAL_NFCF_CHECKUPDATE_RES_ST2_POS 10U /*!< Check|Update Res Status Flag 2 position T3T 1.0 Table 8 */ +#define RFAL_NFCF_CHECKUPDATE_RES_NOB_POS 11U /*!< Check|Update Res Number of Blocks position T3T 1.0 Table 8 */ + +#define RFAL_NFCF_STATUS_FLAG_SUCCESS 0x00U /*!< Check response Number of Blocks position T3T 1.0 Table 11 */ +#define RFAL_NFCF_STATUS_FLAG_ERROR 0xFFU /*!< Check response Number of Blocks position T3T 1.0 Table 11 */ + +#define RFAL_NFCF_BLOCKLISTELEM_LEN 0x80U /*!< Block List Element Length bit (2|3 bytes) T3T 1.0 5.6.1 */ + +#define RFAL_NFCF_SERVICECODE_RDONLY 0x000BU /*!< NDEF Service Code as Read-Only T3T 1.0 7.2.1 */ +#define RFAL_NFCF_SERVICECODE_RDWR 0x0009U /*!< NDEF Service Code as Read and Write T3T 1.0 7.2.1 */ + + +/*! NFC-F Felica command set JIS X6319-4 9.1 */ +enum +{ + RFAL_NFCF_CMD_POLLING = 0x00, /*!< SENSF_REQ (Felica Poll/REQC command to identify a card ) */ + RFAL_NFCF_CMD_POLLING_RES = 0x01, /*!< SENSF_RES (Felica Poll/REQC command response ) */ + RFAL_NFCF_CMD_REQUEST_SERVICE = 0x02, /*!< verify the existence of Area and Service */ + RFAL_NFCF_CMD_REQUEST_RESPONSE = 0x04, /*!< verify the existence of a card */ + RFAL_NFCF_CMD_READ_WITHOUT_ENCRYPTION = 0x06, /*!< read Block Data from a Service that requires no authentication */ + RFAL_NFCF_CMD_READ_WITHOUT_ENCRYPTION_RES = 0x07, /*!< read Block Data response from a Service with no authentication */ + RFAL_NFCF_CMD_WRITE_WITHOUT_ENCRYPTION = 0x08, /*!< write Block Data to a Service that requires no authentication */ + RFAL_NFCF_CMD_WRITE_WITHOUT_ENCRYPTION_RES = 0x09, /*!< write Block Data response to a Service with no authentication */ + RFAL_NFCF_CMD_REQUEST_SYSTEM_CODE = 0x0c, /*!< acquire the System Code registered to a card */ + RFAL_NFCF_CMD_AUTHENTICATION1 = 0x10, /*!< authenticate a card */ + RFAL_NFCF_CMD_AUTHENTICATION2 = 0x12, /*!< allow a card to authenticate a Reader/Writer */ + RFAL_NFCF_CMD_READ = 0x14, /*!< read Block Data from a Service that requires authentication */ + RFAL_NFCF_CMD_WRITE = 0x16, /*!< write Block Data to a Service that requires authentication */ +}; + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + +/*! Checks if the given NFC-F device indicates NFC-DEP support */ +#define rfalNfcfIsNfcDepSupported( dev ) ( (((rfalNfcfListenDevice*)(dev))->sensfRes.NFCID2[RFAL_NFCF_SENSF_NFCID2_BYTE1_POS] == RFAL_NFCF_SENSF_NFCID2_BYTE1_NFCDEP) && \ + (((rfalNfcfListenDevice*)(dev))->sensfRes.NFCID2[RFAL_NFCF_SENSF_NFCID2_BYTE2_POS] == RFAL_NFCF_SENSF_NFCID2_BYTE2_NFCDEP) ) + + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + + +/*! NFC-F SENSF_RES format Digital 1.1 8.6.2 */ +typedef struct +{ + uint8_t CMD; /*!< Command Code: 01h */ + uint8_t NFCID2[RFAL_NFCF_NFCID2_LEN]; /*!< NFCID2 */ + uint8_t PAD0[RFAL_NFCF_SENSF_RES_PAD0_LEN]; /*!< PAD0 */ + uint8_t PAD1[RFAL_NFCF_SENSF_RES_PAD1_LEN]; /*!< PAD1 */ + uint8_t MRTIcheck; /*!< MRTIcheck */ + uint8_t MRTIupdate; /*!< MRTIupdate */ + uint8_t PAD2; /*!< PAD2 */ + uint8_t RD[RFAL_NFCF_SENSF_RES_RD_LEN]; /*!< Request Data */ +} rfalNfcfSensfRes; + + +/*! NFC-F poller device (PCD) struct */ +typedef struct +{ + uint8_t NFCID2[RFAL_NFCF_NFCID2_LEN]; /*!< NFCID2 */ +} rfalNfcfPollDevice; + +/*! NFC-F listener device (PICC) struct */ +typedef struct +{ + uint8_t sensfResLen; /*!< SENF_RES length */ + rfalNfcfSensfRes sensfRes; /*!< SENF_RES */ +} rfalNfcfListenDevice; + +typedef uint16_t rfalNfcfServ; /*!< NFC-F Service Code */ + +/*! NFC-F Block List Element (2 or 3 bytes element) T3T 1.0 5.6.1 */ +typedef struct +{ + uint8_t conf; /*!< Access Mode | Serv Code List Order */ + uint16_t blockNum; /*!< Block Number */ +}rfalNfcfBlockListElem; + +/*! Check Update Service list and Block list parameter */ +typedef struct +{ + uint8_t numServ; /*!< Number of Services */ + rfalNfcfServ *servList; /*!< Service Code List */ + uint8_t numBlock; /*!< Number of Blocks */ + rfalNfcfBlockListElem *blockList; /*!< Block Number List */ +}rfalNfcfServBlockListParam; + + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/*! + ***************************************************************************** + * \brief Initialize NFC-F Poller mode + * + * This methods configures RFAL RF layer to perform as a + * NFC-F Poller/RW (FeliCa PCD) including all default timings + * + * \param[in] bitRate : NFC-F bitrate to be initialize (212 or 424) + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Incorrect bitrate + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcfPollerInitialize( rfalBitRate bitRate ); + + +/*! + ***************************************************************************** + * \brief NFC-F Poller Check Presence + * + * This function sends a Poll/SENSF command according to NFC Activity spec + * It detects if a NCF-F device is within range + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_NONE : No error and some NFC-F device was detected + * + ***************************************************************************** + */ +ReturnCode rfalNfcfPollerCheckPresence( void ); + + +/*! + ***************************************************************************** + * \brief NFC-F Poller Poll + * + * This function sends to all PICCs in field the POLL command with the given + * number of slots. + * + * \param[in] slots : the number of slots to be performed + * \param[in] sysCode : as given in FeliCa poll command + * \param[in] reqCode : FeliCa communication parameters + * \param[out] cardList : Parameter of type rfalFeliCaPollRes which will hold the cards found + * \param[out] devCnt : actual number of cards found + * \param[out] collisions : number of collisions encountered + * + * \warning the list cardList has to be as big as the number of slots for the Poll + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_NONE : No error and some NFC-F device was detected + * + ***************************************************************************** + */ +ReturnCode rfalNfcfPollerPoll( rfalFeliCaPollSlots slots, uint16_t sysCode, uint8_t reqCode, rfalFeliCaPollRes *cardList, uint8_t *devCnt, uint8_t *collisions ); + + +/*! + ***************************************************************************** + * \brief NFC-F Poller Full Collision Resolution + * + * Performs a full Collision resolution as defined in Activity 1.1 9.3.4 + * + * \param[in] compMode : compliance mode to be performed + * \param[in] devLimit : device limit value, and size nfcaDevList + * \param[out] nfcfDevList : NFC-F listener devices list + * \param[out] devCnt : Devices found counter + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcfPollerCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcfListenDevice *nfcfDevList, uint8_t *devCnt ); + + +/*! + ***************************************************************************** + * \brief NFC-F Poller Check/Read + * + * It computes a Check / Read command accoring to T3T 1.0 and JIS X6319-4 and + * sends it to PICC. If sucessfully, the rxBuf will contain the the number of + * blocks in the first byte followed by the blocks data. + * + * \param[in] nfcid2 : nfcid2 of the device + * \param[in] servBlock : parameter containing the list of Services and + * Blocks to be addressed by this command + * \param[out] rxBuf : buffer to place check/read data + * \param[in] rxBufLen : size of the rxBuf + * \param[out] rcvdLen : length of data placed in rxBuf + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_REQUEST : The request was executed with error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcfPollerCheck( const uint8_t* nfcid2, const rfalNfcfServBlockListParam *servBlock, uint8_t *rxBuf, uint16_t rxBufLen, uint16_t *rcvdLen ); + + +/*! + ***************************************************************************** + * \brief NFC-F Poller Update/Write + * + * It computes a Update / Write command accoring to T3T 1.0 and JIS X6319-4 and + * sends it to PICC. + * + * \param[in] nfcid2 : nfcid2 of the device + * \param[in] servBlock : parameter containing the list of Services and + * Blocks to be addressed by this command + * \param[in] txBuf : buffer where the request will be composed + * \param[in] txBufLen : size of txBuf + * \param[in] blockData : data to written on the given block(s) + * \param[out] rxBuf : buffer to place check/read data + * \param[in] rxBufLen : size of the rxBuf + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_REQUEST : The request was executed with error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalNfcfPollerUpdate( const uint8_t* nfcid2, const rfalNfcfServBlockListParam *servBlock, uint8_t *txBuf, uint16_t txBufLen, const uint8_t *blockData, uint8_t *rxBuf, uint16_t rxBufLen); + +/*! + ***************************************************************************** + * \brief NFC-F Listener is T3T Request + * + * This method checks if the given data is a valid T3T command (Read or Write) + * and in case a valid request has been received it may output the request's NFCID2 + * + * \param[in] buf : buffer holding Initiator's received command + * \param[in] bufLen : length of received command in bytes + * \param[out] nfcid2 : pointer to where the NFCID2 may be outputed, + * nfcid2 has NFCF_SENSF_NFCID2_LEN as length + * Pass NULL if output parameter not desired + * + * \return true : Valid T3T command (Read or Write) received + * \return false : Invalid protocol request + * + ***************************************************************************** + */ +bool rfalNfcfListenerIsT3TReq( const uint8_t* buf, uint16_t bufLen, uint8_t* nfcid2 ); + + +#endif /* RFAL_NFCF_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcv.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcv.h new file mode 100644 index 0000000..36875b1 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_nfcv.h @@ -0,0 +1,772 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfcv.h + * + * \author Gustavo Patricio + * + * \brief Implementation of NFC-V Poller (ISO15693) device + * + * The definitions and helpers methods provided by this module + * are aligned with NFC-V Digital 2.1 + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup NFC-V + * \brief RFAL NFC-V Module + * @{ + * + */ + +#ifndef RFAL_NFCV_H +#define RFAL_NFCV_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_NFCV_UID_LEN 8U /*!< NFC-V UID length */ +#define RFAL_NFCV_MAX_BLOCK_LEN 32U /*!< Max Block size: can be of up to 256 bits ISO 15693 2000 5 */ +#define RFAL_NFCV_BNO_LEN 1U /*!< NFC-V Block Number length */ +#define RFAL_NFCV_CRC_LEN 2U /*!< NFC-V CRC length */ +#define RFAL_NFCV_MAX_GEN_DATA_LEN (RFAL_NFCV_MAX_BLOCK_LEN + RFAL_NFCV_BNO_LEN + RFAL_NFCV_UID_LEN) /*!
© COPYRIGHT 2016 STMicroelectronics
+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_rf.h + * + * \author Gustavo Patricio + * + * \brief RF Abstraction Layer (RFAL) + * + * RFAL (RF Abstraction Layer) provides several functionalities required to + * perform RF/NFC communications.
The RFAL encapsulates the different + * RF ICs (ST25R3911, ST25R391x, etc) into a common and easy to use interface. + * + * It provides interfaces to configure the RF IC, set/get timings, modes, bit rates, + * specific handlings, execute listen mode, etc. + * + * Furthermore it provides a common interface to perform a Transceive operations. + * The Transceive can be executed in a blocking or non blocking way.
+ * Additionally few specific Transceive methods are available to cope with the + * specifics of these particular operations. + * + * The most common interfaces are: + *
  rfalInitialize() + *
  rfalSetFDTPoll() + *
  rfalSetFDTListen() + *
  rfalSetGT() + *
  rfalSetBitRate() + *
  rfalSetMode() + *
  rfalFieldOnAndStartGT() + *
  rfalFieldOff() + *
  rfalStartTransceive() + *
  rfalGetTransceiveStatus() + *
  rfalTransceiveBlockingTxRx() + * + * An usage example is provided here: \ref exampleRfalPoller.c + * \example exampleRfalPoller.c + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-HAL + * \brief RFAL Hardware Abstraction Layer + * @{ + * + * \addtogroup RF + * \brief RFAL RF Abstraction Layer + * @{ + * + */ + +#ifndef RFAL_RF_H +#define RFAL_RF_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" +#include "st_errno.h" +#include "rfal_features.h" + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ +#define RFAL_VERSION (uint32_t)0x02000aU /*!< RFAL Current Version: v2.0.10 */ + +#define RFAL_FWT_NONE 0xFFFFFFFFU /*!< Disabled FWT: Wait forever for a response */ +#define RFAL_GT_NONE RFAL_TIMING_NONE /*!< Disabled GT: No GT will be applied after Field On */ + +#define RFAL_TIMING_NONE 0x00U /*!< Timing disabled | Don't apply */ + +#define RFAL_1FC_IN_4096FC (uint32_t)4096U /*!< Number of 1/fc cycles in one 4096/fc */ +#define RFAL_1FC_IN_512FC (uint32_t)512U /*!< Number of 1/fc cycles in one 512/fc */ +#define RFAL_1FC_IN_64FC (uint32_t)64U /*!< Number of 1/fc cycles in one 64/fc */ +#define RFAL_1FC_IN_8FC (uint32_t)8U /*!< Number of 1/fc cycles in one 8/fc */ +#define RFAL_US_IN_MS (uint32_t)1000U /*!< Number of us in one ms */ +#define RFAL_1MS_IN_1FC (uint32_t)13560U /*!< Number of 1/fc cycles in 1ms */ +#define RFAL_BITS_IN_BYTE (uint16_t)8U /*!< Number of bits in one byte */ + +#define RFAL_CRC_LEN 2U /*!< RF CRC LEN */ + +/*! Default TxRx flags: Tx CRC automatic, Rx CRC removed, NFCIP1 mode off, AGC On, Tx Parity automatic, Rx Parity removed */ +#define RFAL_TXRX_FLAGS_DEFAULT ( (uint32_t)RFAL_TXRX_FLAGS_CRC_TX_AUTO | (uint32_t)RFAL_TXRX_FLAGS_CRC_RX_REMV | (uint32_t)RFAL_TXRX_FLAGS_NFCIP1_OFF | (uint32_t)RFAL_TXRX_FLAGS_AGC_ON | (uint32_t)RFAL_TXRX_FLAGS_PAR_RX_REMV | (uint32_t)RFAL_TXRX_FLAGS_PAR_TX_AUTO | (uint32_t)RFAL_TXRX_FLAGS_NFCV_FLAG_AUTO) + + + +#define RFAL_LM_MASK_NFCA (1U<<(uint8_t)RFAL_MODE_LISTEN_NFCA) /*!< Bitmask for Listen Mode enabling Listen NFCA */ +#define RFAL_LM_MASK_NFCB (1U<<(uint8_t)RFAL_MODE_LISTEN_NFCB) /*!< Bitmask for Listen Mode enabling Listen NFCB */ +#define RFAL_LM_MASK_NFCF (1U<<(uint8_t)RFAL_MODE_LISTEN_NFCF) /*!< Bitmask for Listen Mode enabling Listen NFCF */ +#define RFAL_LM_MASK_ACTIVE_P2P (1U<<(uint8_t)RFAL_MODE_LISTEN_ACTIVE_P2P) /*!< Bitmask for Listen Mode enabling Listen AP2P */ + +#define RFAL_LM_SENS_RES_LEN 2U /*!< NFC-A SENS_RES (ATQA) length */ +#define RFAL_LM_SENSB_RES_LEN 13U /*!< NFC-B SENSB_RES (ATQB) length */ +#define RFAL_LM_SENSF_RES_LEN 19U /*!< NFC-F SENSF_RES length */ +#define RFAL_LM_SENSF_SC_LEN 2U /*!< NFC-F System Code length */ + +#define RFAL_NFCID3_LEN 10U /*!< NFCID3 length */ +#define RFAL_NFCID2_LEN 8U /*!< NFCID2 length */ +#define RFAL_NFCID1_TRIPLE_LEN 10U /*!< NFCID1 length */ +#define RFAL_NFCID1_DOUBLE_LEN 7U /*!< NFCID1 length */ +#define RFAL_NFCID1_SIMPLE_LEN 4U /*!< NFCID1 length */ + + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ + +/*! Returns the maximum supported bit rate for RW mode. Caller must check if mode is supported before, as even if mode is not supported will return the min */ +#define rfalGetMaxBrRW() ( ((RFAL_SUPPORT_BR_RW_6780) ? RFAL_BR_6780 : ((RFAL_SUPPORT_BR_RW_3390) ? RFAL_BR_3390 : ((RFAL_SUPPORT_BR_RW_1695) ? RFAL_BR_1695 : ((RFAL_SUPPORT_BR_RW_848) ? RFAL_BR_848 : ((RFAL_SUPPORT_BR_RW_424) ? RFAL_BR_424 : ((RFAL_SUPPORT_BR_RW_212) ? RFAL_BR_212 : RFAL_BR_106 ) ) ) ) ) ) ) + +/*! Returns the maximum supported bit rate for AP2P mode. Caller must check if mode is supported before, as even if mode is not supported will return the min */ +#define rfalGetMaxBrAP2P() ( ((RFAL_SUPPORT_BR_AP2P_848) ? RFAL_BR_848 : ((RFAL_SUPPORT_BR_AP2P_424) ? RFAL_BR_424 : ((RFAL_SUPPORT_BR_AP2P_212) ? RFAL_BR_212 : RFAL_BR_106 ) ) ) ) + +/*! Returns the maximum supported bit rate for CE-A mode. Caller must check if mode is supported before, as even if mode is not supported will return the min */ +#define rfalGetMaxBrCEA() ( ((RFAL_SUPPORT_BR_CE_A_848) ? RFAL_BR_848 : ((RFAL_SUPPORT_BR_CE_A_424) ? RFAL_BR_424 : ((RFAL_SUPPORT_BR_CE_A_212) ? RFAL_BR_212 : RFAL_BR_106 ) ) ) ) + +/*! Returns the maximum supported bit rate for CE-B mode. Caller must check if mode is supported before, as even if mode is not supported will return the min */ +#define rfalGetMaxBrCEB() ( ((RFAL_SUPPORT_BR_CE_B_848) ? RFAL_BR_848 : ((RFAL_SUPPORT_BR_CE_B_424) ? RFAL_BR_424 : ((RFAL_SUPPORT_BR_CE_B_212) ? RFAL_BR_212 : RFAL_BR_106 ) ) ) ) + +/*! Returns the maximum supported bit rate for CE-F mode. Caller must check if mode is supported before, as even if mode is not supported will return the min */ +#define rfalGetMaxBrCEF() ( ((RFAL_SUPPORT_BR_CE_F_424) ? RFAL_BR_424 : RFAL_BR_212 ) ) + + +#define rfalIsModeActiveComm( md ) ( ((md) == RFAL_MODE_POLL_ACTIVE_P2P) || ((md) == RFAL_MODE_LISTEN_ACTIVE_P2P) ) /*!< Checks if mode md is Active Communication */ +#define rfalIsModePassiveComm( md ) ( !rfalIsModeActiveComm(md) ) /*!< Checks if mode md is Passive Communication */ +#define rfalIsModePassiveListen( md ) ( ((md) == RFAL_MODE_LISTEN_NFCA) || ((md) == RFAL_MODE_LISTEN_NFCB) || ((md) == RFAL_MODE_LISTEN_NFCF) ) /*!< Checks if mode md is Passive Listen */ +#define rfalIsModePassivePoll( md ) ( rfalIsModePassiveComm(md) && !rfalIsModePassiveListen(md) ) /*!< Checks if mode md is Passive Poll */ + + +#define rfalConv1fcTo8fc( t ) (uint32_t)( (uint32_t)(t) / RFAL_1FC_IN_8FC ) /*!< Converts the given t from 1/fc to 8/fc */ +#define rfalConv8fcTo1fc( t ) (uint32_t)( (uint32_t)(t) * RFAL_1FC_IN_8FC ) /*!< Converts the given t from 8/fc to 1/fc */ + +#define rfalConv1fcTo64fc( t ) (uint32_t)( (uint32_t)(t) / RFAL_1FC_IN_64FC ) /*!< Converts the given t from 1/fc to 64/fc */ +#define rfalConv64fcTo1fc( t ) (uint32_t)( (uint32_t)(t) * RFAL_1FC_IN_64FC ) /*!< Converts the given t from 64/fc to 1/fc */ + +#define rfalConv1fcTo512fc( t ) (uint32_t)( (uint32_t)(t) / RFAL_1FC_IN_512FC ) /*!< Converts the given t from 1/fc to 512/fc */ +#define rfalConv512fcTo1fc( t ) (uint32_t)( (uint32_t)(t) * RFAL_1FC_IN_512FC ) /*!< Converts the given t from 512/fc to 1/fc */ + +#define rfalConv1fcTo4096fc( t ) (uint32_t)( (uint32_t)(t) / RFAL_1FC_IN_4096FC ) /*!< Converts the given t from 1/fc to 4096/fc */ +#define rfalConv4096fcTo1fc( t ) (uint32_t)( (uint32_t)(t) * RFAL_1FC_IN_4096FC ) /*!< Converts the given t from 4096/fc to 1/fc */ + +#define rfalConv1fcToMs( t ) (uint32_t)( (uint32_t)(t) / RFAL_1MS_IN_1FC ) /*!< Converts the given t from 1/fc to ms */ +#define rfalConvMsTo1fc( t ) (uint32_t)( (uint32_t)(t) * RFAL_1MS_IN_1FC ) /*!< Converts the given t from ms to 1/fc */ + +#define rfalConv1fcToUs( t ) (uint32_t)( ((uint32_t)(t) * RFAL_US_IN_MS) / RFAL_1MS_IN_1FC) /*!< Converts the given t from 1/fc to us */ +#define rfalConvUsTo1fc( t ) (uint32_t)( ((uint32_t)(t) * RFAL_1MS_IN_1FC) / RFAL_US_IN_MS) /*!< Converts the given t from us to 1/fc */ + +#define rfalConv64fcToMs( t ) (uint32_t)( (uint32_t)(t) / (RFAL_1MS_IN_1FC / RFAL_1FC_IN_64FC) ) /*!< Converts the given t from 64/fc to ms */ +#define rfalConvMsTo64fc( t ) (uint32_t)( (uint32_t)(t) * (RFAL_1MS_IN_1FC / RFAL_1FC_IN_64FC) ) /*!< Converts the given t from ms to 64/fc */ + +#define rfalConvBitsToBytes( n ) (uint16_t)( ((uint16_t)(n)+(RFAL_BITS_IN_BYTE-1U)) / (RFAL_BITS_IN_BYTE) ) /*!< Converts the given n from bits to bytes */ +#define rfalConvBytesToBits( n ) (uint32_t)( (uint32_t)(n) * (RFAL_BITS_IN_BYTE) ) /*!< Converts the given n from bytes to bits */ + + + +/*! Computes a Transceive context \a ctx with default flags and the lengths + * in bytes with the given arguments + * \a ctx : Transceive context to be assigned + * \a tB : txBuf the pointer to the buffer to be sent + * \a tBL : txBuf length in bytes + * \a rB : rxBuf the pointer to the buffer to place the received frame + * \a rBL : rxBuf length in bytes + * \a rBL : rxBuf length in bytes + * \a t : FWT to be used on this transceive in 1/fc + */ +#define rfalCreateByteTxRxContext( ctx, tB, tBL, rB, rBL, rdL, t ) \ + (ctx).txBuf = (uint8_t*)(tB); \ + (ctx).txBufLen = (uint16_t)rfalConvBytesToBits(tBL); \ + (ctx).rxBuf = (uint8_t*)(rB); \ + (ctx).rxBufLen = (uint16_t)rfalConvBytesToBits(rBL); \ + (ctx).rxRcvdLen = (uint16_t*)(rdL); \ + (ctx).flags = (uint32_t)RFAL_TXRX_FLAGS_DEFAULT; \ + (ctx).fwt = (uint32_t)(t); + + +/*! Computes a Transceive context \a ctx using lengths in bytes + * with the given flags and arguments + * \a ctx : Transceive context to be assigned + * \a tB : txBuf the pointer to the buffer to be sent + * \a tBL : txBuf length in bytes + * \a rB : rxBuf the pointer to the buffer to place the received frame + * \a rBL : rxBuf length in bytes + * \a rBL : rxBuf length in bytes + * \a t : FWT to be used on this transceive in 1/fc + */ +#define rfalCreateByteFlagsTxRxContext( ctx, tB, tBL, rB, rBL, rdL, fl, t ) \ + (ctx).txBuf = (uint8_t*)(tB); \ + (ctx).txBufLen = (uint16_t)rfalConvBytesToBits(tBL); \ + (ctx).rxBuf = (uint8_t*)(rB); \ + (ctx).rxBufLen = (uint16_t)rfalConvBytesToBits(rBL); \ + (ctx).rxRcvdLen = (uint16_t*)(rdL); \ + (ctx).flags = (uint32_t)(fl); \ + (ctx).fwt = (uint32_t)(t); + + +#define rfalLogE(...) platformLog(__VA_ARGS__) /*!< Macro for the error log method */ +#define rfalLogW(...) platformLog(__VA_ARGS__) /*!< Macro for the warning log method */ +#define rfalLogI(...) platformLog(__VA_ARGS__) /*!< Macro for the info log method */ +#define rfalLogD(...) platformLog(__VA_ARGS__) /*!< Macro for the debug log method */ + + +/* +****************************************************************************** +* GLOBAL ENUMS +****************************************************************************** +*/ + +/* RFAL Guard Time (GT) default values */ +#define RFAL_GT_NFCA rfalConvMsTo1fc(5U) /*!< GTA Digital 2.0 6.10.4.1 & B.2 */ +#define RFAL_GT_NFCB rfalConvMsTo1fc(5U) /*!< GTB Digital 2.0 7.9.4.1 & B.3 */ +#define RFAL_GT_NFCF rfalConvMsTo1fc(20U) /*!< GTF Digital 2.0 8.7.4.1 & B.4 */ +#define RFAL_GT_NFCV rfalConvMsTo1fc(5U) /*!< GTV Digital 2.0 9.7.5.1 & B.5 */ +#define RFAL_GT_PICOPASS rfalConvMsTo1fc(1U) /*!< GT Picopass */ +#define RFAL_GT_AP2P rfalConvMsTo1fc(5U) /*!< TIRFG Ecma 340 11.1.1 */ +#define RFAL_GT_AP2P_ADJUSTED rfalConvMsTo1fc(5U+25U) /*!< Adjusted GT for greater interoperability (Sony XPERIA P, Nokia N9, Huawei P2) */ + +/* RFAL Frame Delay Time (FDT) Listen default values */ +#define RFAL_FDT_LISTEN_NFCA_POLLER 1172U /*!< FDTA,LISTEN,MIN (n=9) Last bit: Logic "1" - tnn,min/2 Digital 1.1 6.10 ; EMV CCP Spec Book D v2.01 4.8.1.3 */ +#define RFAL_FDT_LISTEN_NFCB_POLLER 1008U /*!< TR0B,MIN Digital 1.1 7.1.3 & A.3 ; EMV CCP Spec Book D v2.01 4.8.1.3 & Table A.5 */ +#define RFAL_FDT_LISTEN_NFCF_POLLER 2672U /*!< TR0F,LISTEN,MIN Digital 1.1 8.7.1.1 & A.4 */ +#define RFAL_FDT_LISTEN_NFCV_POLLER 4310U /*!< FDTV,LISTEN,MIN t1 min Digital 2.1 B.5 ; ISO15693-3 2009 9.1 */ +#define RFAL_FDT_LISTEN_PICOPASS_POLLER 3400U /*!< ISO15693 t1 min - observed adjustment */ +#define RFAL_FDT_LISTEN_AP2P_POLLER 64U /*!< FDT AP2P No actual FDTListen is required as fields switch and collision avoidance */ +#define RFAL_FDT_LISTEN_NFCA_LISTENER 1172U /*!< FDTA,LISTEN,MIN Digital 1.1 6.10 */ +#define RFAL_FDT_LISTEN_NFCB_LISTENER 1024U /*!< TR0B,MIN Digital 1.1 7.1.3 & A.3 ; EMV CCP Spec Book D v2.01 4.8.1.3 & Table A.5 */ +#define RFAL_FDT_LISTEN_NFCF_LISTENER 2688U /*!< TR0F,LISTEN,MIN Digital 1.1 8.7.1.1 & A.4 */ +#define RFAL_FDT_LISTEN_AP2P_LISTENER 64U /*!< FDT AP2P No actual FDTListen exists as fields switch and collision avoidance */ + +/* RFAL Frame Delay Time (FDT) Poll default values */ +#define RFAL_FDT_POLL_NFCA_POLLER 6780U /*!< FDTA,POLL,MIN Digital 1.1 6.10.3.1 & A.2 */ +#define RFAL_FDT_POLL_NFCA_T1T_POLLER 384U /*!< RRDDT1T,MIN,B1 Digital 1.1 10.7.1 & A.5 */ +#define RFAL_FDT_POLL_NFCB_POLLER 6780U /*!< FDTB,POLL,MIN = TR2B,MIN,DEFAULT Digital 1.1 7.9.3 & A.3 ; EMVCo 3.0 FDTB,PCD,MIN Table A.5 */ +#define RFAL_FDT_POLL_NFCF_POLLER 2672U /*!< FDTF,POLL,MIN Digital 1.1 8.7.3 & A.4 */ +#define RFAL_FDT_POLL_NFCV_POLLER 4192U /*!< FDTV,POLL Digital 2.1 9.7.3.1 & B.5 */ +#define RFAL_FDT_POLL_PICOPASS_POLLER 1790U /*!< FDT Max */ +#define RFAL_FDT_POLL_AP2P_POLLER 0U /*!< FDT AP2P No actual FDTPoll exists as fields switch and collision avoidance */ + + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! RFAL modes */ +typedef enum { + RFAL_MODE_NONE = 0, /*!< No mode selected/defined */ + RFAL_MODE_POLL_NFCA = 1, /*!< Mode to perform as NFCA (ISO14443A) Poller (PCD) */ + RFAL_MODE_POLL_NFCA_T1T = 2, /*!< Mode to perform as NFCA T1T (Topaz) Poller (PCD) */ + RFAL_MODE_POLL_NFCB = 3, /*!< Mode to perform as NFCB (ISO14443B) Poller (PCD) */ + RFAL_MODE_POLL_B_PRIME = 4, /*!< Mode to perform as B' Calypso (Innovatron) (PCD) */ + RFAL_MODE_POLL_B_CTS = 5, /*!< Mode to perform as CTS Poller (PCD) */ + RFAL_MODE_POLL_NFCF = 6, /*!< Mode to perform as NFCF (FeliCa) Poller (PCD) */ + RFAL_MODE_POLL_NFCV = 7, /*!< Mode to perform as NFCV (ISO15963) Poller (PCD) */ + RFAL_MODE_POLL_PICOPASS = 8, /*!< Mode to perform as PicoPass / iClass Poller (PCD) */ + RFAL_MODE_POLL_ACTIVE_P2P = 9, /*!< Mode to perform as Active P2P (ISO18092) Initiator */ + RFAL_MODE_LISTEN_NFCA = 10, /*!< Mode to perform as NFCA (ISO14443A) Listener (PICC) */ + RFAL_MODE_LISTEN_NFCB = 11, /*!< Mode to perform as NFCA (ISO14443B) Listener (PICC) */ + RFAL_MODE_LISTEN_NFCF = 12, /*!< Mode to perform as NFCA (ISO15963) Listener (PICC) */ + RFAL_MODE_LISTEN_ACTIVE_P2P = 13 /*!< Mode to perform as Active P2P (ISO18092) Target */ +} rfalMode; + + +/*! RFAL Bit rates */ +typedef enum { + RFAL_BR_106 = 0, /*!< Bit Rate 106 kbit/s (fc/128) */ + RFAL_BR_212 = 1, /*!< Bit Rate 212 kbit/s (fc/64) */ + RFAL_BR_424 = 2, /*!< Bit Rate 424 kbit/s (fc/32) */ + RFAL_BR_848 = 3, /*!< Bit Rate 848 kbit/s (fc/16) */ + RFAL_BR_1695 = 4, /*!< Bit Rate 1695 kbit/s (fc/8) */ + RFAL_BR_3390 = 5, /*!< Bit Rate 3390 kbit/s (fc/4) */ + RFAL_BR_6780 = 6, /*!< Bit Rate 6780 kbit/s (fc/2) */ + RFAL_BR_13560 = 7, /*!< Bit Rate 13560 kbit/s (fc) */ + RFAL_BR_52p97 = 0xEB, /*!< Bit Rate 52.97 kbit/s (fc/256) Fast Mode VICC->VCD */ + RFAL_BR_26p48 = 0xEC, /*!< Bit Rate 26,48 kbit/s (fc/512) NFCV VICC->VCD & VCD->VICC 1of4 */ + RFAL_BR_1p66 = 0xED, /*!< Bit Rate 1,66 kbit/s (fc/8192) NFCV VCD->VICC 1of256 */ + RFAL_BR_KEEP = 0xFF /*!< Value indicating to keep the same previous bit rate */ +} rfalBitRate; + + +/*! RFAL Compliance modes for upper modules */ +typedef enum { + RFAL_COMPLIANCE_MODE_NFC, /*!< Perform with NFC Forum 1.1 compliance */ + RFAL_COMPLIANCE_MODE_EMV, /*!< Perform with EMVCo compliance */ + RFAL_COMPLIANCE_MODE_ISO /*!< Perform with ISO10373 compliance */ +}rfalComplianceMode; + + +/*! RFAL main states flags */ +typedef enum { + RFAL_STATE_IDLE = 0, + RFAL_STATE_INIT = 1, + RFAL_STATE_MODE_SET = 2, + + RFAL_STATE_TXRX = 3, + RFAL_STATE_LM = 4, + RFAL_STATE_WUM = 5 + +} rfalState; + +/*! RFAL transceive states */ +typedef enum { + RFAL_TXRX_STATE_IDLE = 0, + RFAL_TXRX_STATE_INIT = 1, + RFAL_TXRX_STATE_START = 2, + + RFAL_TXRX_STATE_TX_IDLE = 11, + RFAL_TXRX_STATE_TX_WAIT_GT = 12, + RFAL_TXRX_STATE_TX_WAIT_FDT = 13, + RFAL_TXRX_STATE_TX_TRANSMIT = 14, + RFAL_TXRX_STATE_TX_WAIT_WL = 15, + RFAL_TXRX_STATE_TX_RELOAD_FIFO = 16, + RFAL_TXRX_STATE_TX_WAIT_TXE = 17, + RFAL_TXRX_STATE_TX_DONE = 18, + RFAL_TXRX_STATE_TX_FAIL = 19, + + RFAL_TXRX_STATE_RX_IDLE = 81, + RFAL_TXRX_STATE_RX_WAIT_EON = 82, + RFAL_TXRX_STATE_RX_WAIT_RXS = 83, + RFAL_TXRX_STATE_RX_WAIT_RXE = 84, + RFAL_TXRX_STATE_RX_READ_FIFO = 85, + RFAL_TXRX_STATE_RX_ERR_CHECK = 86, + RFAL_TXRX_STATE_RX_READ_DATA = 87, + RFAL_TXRX_STATE_RX_WAIT_EOF = 88, + RFAL_TXRX_STATE_RX_DONE = 89, + RFAL_TXRX_STATE_RX_FAIL = 90, + +} rfalTransceiveState; + + +/*! RFAL transceive flags */ +enum { + RFAL_TXRX_FLAGS_CRC_TX_AUTO = (0U<<0), /*!< CRC will be generated automatic upon transmission */ + RFAL_TXRX_FLAGS_CRC_TX_MANUAL = (1U<<0), /*!< CRC was calculated manually, included in txBuffer */ + RFAL_TXRX_FLAGS_CRC_RX_KEEP = (1U<<1), /*!< Upon Reception keep the CRC in rxBuffer (reflected on rcvd length) */ + RFAL_TXRX_FLAGS_CRC_RX_REMV = (0U<<1), /*!< Upon Reception remove the CRC from rxBuffer */ + RFAL_TXRX_FLAGS_NFCIP1_ON = (1U<<2), /*!< Enable NFCIP1 mode: Add SB(F0) and LEN bytes during Tx and skip SB(F0) byte during Rx */ + RFAL_TXRX_FLAGS_NFCIP1_OFF = (0U<<2), /*!< Disable NFCIP1 mode: do not append protocol bytes while Tx nor skip while Rx */ + RFAL_TXRX_FLAGS_AGC_OFF = (1U<<3), /*!< Disable Automatic Gain Control, improving multiple devices collision detection */ + RFAL_TXRX_FLAGS_AGC_ON = (0U<<3), /*!< Enable Automatic Gain Control, improving single device reception */ + RFAL_TXRX_FLAGS_PAR_RX_KEEP = (1U<<4), /*!< Disable Parity and CRC check and keep the Parity and CRC bits in the received buffer */ + RFAL_TXRX_FLAGS_PAR_RX_REMV = (0U<<0), /*!< Enable Parity check and remove the parity bits from the received buffer */ + RFAL_TXRX_FLAGS_PAR_TX_NONE = (1U<<5), /*!< Disable automatic Parity generation (ISO14443A) and use the one provided in the buffer*/ + RFAL_TXRX_FLAGS_PAR_TX_AUTO = (0U<<5), /*!< Enable automatic Parity generation (ISO14443A) */ + RFAL_TXRX_FLAGS_NFCV_FLAG_MANUAL = (1U<<6), /*!< Disable automatic adaption of flag byte (ISO15693) according to current comm params */ + RFAL_TXRX_FLAGS_NFCV_FLAG_AUTO = (0U<<6), /*!< Enable automatic adaption of flag byte (ISO115693) according to current comm params */ +}; + + +/*! RFAL error handling */ +typedef enum { + RFAL_ERRORHANDLING_NONE = 0, /*!< No special error handling will be performed */ + RFAL_ERRORHANDLING_NFC = 1, /*!< Error handling set to perform as NFC complaint device */ + RFAL_ERRORHANDLING_EMVCO = 2 /*!< Error handling set to perform as EMVCo complaint device */ +} rfalEHandling; + + +/*! Struct that holds all context to be used on a Transceive */ +typedef struct { + uint8_t* txBuf; /*!< (In) Buffer where outgoing message is located */ + uint16_t txBufLen; /*!< (In) Length of the outgoing message in bits */ + + uint8_t* rxBuf; /*!< (Out) Buffer where incoming message will be placed */ + uint16_t rxBufLen; /*!< (In) Maximum length of the incoming message in bits */ + uint16_t* rxRcvdLen; /*!< (Out) Actual received length in bits */ + + uint32_t flags; /*!< (In) TransceiveFlags indication special handling */ + uint32_t fwt; /*!< (In) Frame Waiting Time in 1/fc */ +} rfalTransceiveContext; + + +/*! System callback to indicate an event that requires a system reRun */ +typedef void (* rfalUpperLayerCallback)(void); + +/*! Callback to be executed before a Transceive */ +typedef void (* rfalPreTxRxCallback)(void); + +/*! Callback to be executed after a Transceive */ +typedef void (* rfalPostTxRxCallback)(void); + + +/*******************************************************************************/ +/* ISO14443A */ +/*******************************************************************************/ + +/*! RFAL ISO 14443A Short Frame Command */ +typedef enum +{ + RFAL_14443A_SHORTFRAME_CMD_WUPA = 0x52, /*!< ISO14443A WUPA / NFC-A ALL_REQ */ + RFAL_14443A_SHORTFRAME_CMD_REQA = 0x26 /*!< ISO14443A REQA / NFC-A SENS_REQ */ +} rfal14443AShortFrameCmd; + +/*******************************************************************************/ + + +/*******************************************************************************/ +/* FeliCa */ +/*******************************************************************************/ + +#define RFAL_FELICA_LEN_LEN 1U /*!< FeliCa LEN byte length */ +#define RFAL_FELICA_POLL_REQ_LEN (RFAL_FELICA_LEN_LEN + 1U + 2U + 1U + 1U) /*!< FeliCa Poll Request length (LEN + CMD + SC + RC + TSN) */ +#define RFAL_FELICA_POLL_RES_LEN (RFAL_FELICA_LEN_LEN + 1U + 8U + 8U + 2U) /*!< Maximum FeliCa Poll Response length (LEN + CMD + NFCID2 + PAD + RD) */ +#define RFAL_FELICA_POLL_MAX_SLOTS 16U /*!< Maximum number of slots (TSN) on FeliCa Poll */ + + +/*! NFC-F RC (Request Code) codes NFC Forum Digital 1.1 Table 42 */ +enum +{ + RFAL_FELICA_POLL_RC_NO_REQUEST = 0x00, /*!< RC: No System Code information requested */ + RFAL_FELICA_POLL_RC_SYSTEM_CODE = 0x01, /*!< RC: System Code information requested */ + RFAL_FELICA_POLL_RC_COM_PERFORMANCE = 0x02 /*!< RC: Advanced protocol features supported */ +}; + + +/*! NFC-F TSN (Time Slot Number) codes NFC Forum Digital 1.1 Table 43 */ +typedef enum +{ + RFAL_FELICA_1_SLOT = 0, /*!< TSN with number of Time Slots: 1 */ + RFAL_FELICA_2_SLOTS = 1, /*!< TSN with number of Time Slots: 2 */ + RFAL_FELICA_4_SLOTS = 3, /*!< TSN with number of Time Slots: 4 */ + RFAL_FELICA_8_SLOTS = 7, /*!< TSN with number of Time Slots: 8 */ + RFAL_FELICA_16_SLOTS = 15 /*!< TSN with number of Time Slots: 16 */ +} rfalFeliCaPollSlots; + + +/*! NFCF Poll Response NFC Forum Digital 1.1 Table 44 */ +typedef uint8_t rfalFeliCaPollRes[RFAL_FELICA_POLL_RES_LEN]; + + +/*******************************************************************************/ + + +/*******************************************************************************/ +/* Listen Mode */ +/*******************************************************************************/ + +/*! RFAL Listen Mode NFCID Length */ +typedef enum +{ + RFAL_LM_NFCID_LEN_04 = 4, /*!< Listen mode indicates 4 byte NFCID */ + RFAL_LM_NFCID_LEN_07 = 7, /*!< Listen mode indicates 7 byte NFCID */ + RFAL_LM_NFCID_LEN_10 = 10, /*!< Listen mode indicates 10 byte NFCID */ +} rfalLmNfcidLen; + + +/*! RFAL Listen Mode States */ +typedef enum +{ + RFAL_LM_STATE_NOT_INIT = 0x00, /*!< Not Initialized state */ + RFAL_LM_STATE_POWER_OFF = 0x01, /*!< Power Off state */ + RFAL_LM_STATE_IDLE = 0x02, /*!< Idle state Activity 1.1 5.2 */ + RFAL_LM_STATE_READY_A = 0x03, /*!< Ready A state Activity 1.1 5.3 5.4 & 5.5 */ + RFAL_LM_STATE_READY_B = 0x04, /*!< Ready B state Activity 1.1 5.11 5.12 */ + RFAL_LM_STATE_READY_F = 0x05, /*!< Ready F state Activity 1.1 5.15 */ + RFAL_LM_STATE_ACTIVE_A = 0x06, /*!< Active A state Activity 1.1 5.6 */ + RFAL_LM_STATE_CARDEMU_4A = 0x07, /*!< Card Emulation 4A state Activity 1.1 5.10 */ + RFAL_LM_STATE_CARDEMU_4B = 0x08, /*!< Card Emulation 4B state Activity 1.1 5.14 */ + RFAL_LM_STATE_CARDEMU_3 = 0x09, /*!< Card Emulation 3 state Activity 1.1 5.18 */ + RFAL_LM_STATE_TARGET_A = 0x0A, /*!< Target A state Activity 1.1 5.9 */ + RFAL_LM_STATE_TARGET_F = 0x0B, /*!< Target F state Activity 1.1 5.17 */ + RFAL_LM_STATE_SLEEP_A = 0x0C, /*!< Sleep A state Activity 1.1 5.7 */ + RFAL_LM_STATE_SLEEP_B = 0x0D, /*!< Sleep B state Activity 1.1 5.13 */ + RFAL_LM_STATE_READY_Ax = 0x0E, /*!< Ready A* state Activity 1.1 5.3 5.4 & 5.5 */ + RFAL_LM_STATE_ACTIVE_Ax = 0x0F, /*!< Active A* state Activity 1.1 5.6 */ + RFAL_LM_STATE_SLEEP_AF = 0x10, /*!< Sleep AF state Activity 1.1 5.19 */ +} rfalLmState; + + +/*! RFAL Listen Mode Passive A configs */ +typedef struct +{ + rfalLmNfcidLen nfcidLen; /*!< NFCID Len (00: 4bytes ; 01: 7bytes) */ + uint8_t nfcid[RFAL_NFCID1_TRIPLE_LEN]; /*!< NFCID */ + uint8_t SENS_RES[RFAL_LM_SENS_RES_LEN]; /*!< NFC-106k; SENS_REQ Response */ + uint8_t SEL_RES; /*!< SEL_RES (SAK) with complete NFCID1 (UID) */ +} rfalLmConfPA; + + +/*! RFAL Listen Mode Passive B configs */ +typedef struct +{ + uint8_t SENSB_RES[RFAL_LM_SENSB_RES_LEN]; /*!< SENSF_RES */ +} rfalLmConfPB; + + +/*! RFAL Listen Mode Passive F configs */ +typedef struct +{ + uint8_t SC[RFAL_LM_SENSF_SC_LEN]; /*!< System Code to listen for */ + uint8_t SENSF_RES[RFAL_LM_SENSF_RES_LEN]; /*!< SENSF_RES */ +} rfalLmConfPF; + +/*******************************************************************************/ + + +/*******************************************************************************/ +/* Wake-Up Mode */ +/*******************************************************************************/ + +#define RFAL_WUM_REFERENCE_AUTO 0xFFU /*!< Indicates new reference is set by the driver*/ + +/*! RFAL Wake-Up Mode States */ +typedef enum +{ + RFAL_WUM_STATE_NOT_INIT = 0x00, /*!< Not Initialized state */ + RFAL_WUM_STATE_ENABLED = 0x01, /*!< Wake-Up mode is enabled */ + RFAL_WUM_STATE_ENABLED_WOKE = 0x02, /*!< Wake-Up mode enabled and has received IRQ(s)*/ +} rfalWumState; + +/*! RFAL Wake-Up Period/Timer */ +typedef enum +{ + RFAL_WUM_PERIOD_10MS = 0x00, /*!< Wake-Up timer 10ms */ + RFAL_WUM_PERIOD_20MS = 0x01, /*!< Wake-Up timer 20ms */ + RFAL_WUM_PERIOD_30MS = 0x02, /*!< Wake-Up timer 30ms */ + RFAL_WUM_PERIOD_40MS = 0x03, /*!< Wake-Up timer 40ms */ + RFAL_WUM_PERIOD_50MS = 0x04, /*!< Wake-Up timer 50ms */ + RFAL_WUM_PERIOD_60MS = 0x05, /*!< Wake-Up timer 60ms */ + RFAL_WUM_PERIOD_70MS = 0x06, /*!< Wake-Up timer 70ms */ + RFAL_WUM_PERIOD_80MS = 0x07, /*!< Wake-Up timer 80ms */ + RFAL_WUM_PERIOD_100MS = 0x10, /*!< Wake-Up timer 100ms */ + RFAL_WUM_PERIOD_200MS = 0x11, /*!< Wake-Up timer 200ms */ + RFAL_WUM_PERIOD_300MS = 0x12, /*!< Wake-Up timer 300ms */ + RFAL_WUM_PERIOD_400MS = 0x13, /*!< Wake-Up timer 400ms */ + RFAL_WUM_PERIOD_500MS = 0x14, /*!< Wake-Up timer 500ms */ + RFAL_WUM_PERIOD_600MS = 0x15, /*!< Wake-Up timer 600ms */ + RFAL_WUM_PERIOD_700MS = 0x16, /*!< Wake-Up timer 700ms */ + RFAL_WUM_PERIOD_800MS = 0x17, /*!< Wake-Up timer 800ms */ +} rfalWumPeriod; + + +/*! RFAL Wake-Up Period/Timer */ +typedef enum +{ + RFAL_WUM_AA_WEIGHT_4 = 0x00, /*!< Wake-Up Auto Average Weight 4 */ + RFAL_WUM_AA_WEIGHT_8 = 0x01, /*!< Wake-Up Auto Average Weight 8 */ + RFAL_WUM_AA_WEIGHT_16 = 0x02, /*!< Wake-Up Auto Average Weight 16 */ + RFAL_WUM_AA_WEIGHT_32 = 0x03, /*!< Wake-Up Auto Average Weight 32 */ +} rfalWumAAWeight; + + +/*! RFAL Wake-Up Mode configuration */ +typedef struct +{ + rfalWumPeriod period; /*!< Wake-Up Timer period;how often measurement(s) is performed */ + bool irqTout; /*!< IRQ at every timeout will refresh the measurement(s) */ + bool swTagDetect;/*!< Use SW Tag Detection instead of HW Wake-Up mode */ + + struct{ + bool enabled; /*!< Inductive Amplitude measurement enabled */ + uint8_t delta; /*!< Delta between the reference and measurement to wake-up */ + uint8_t reference; /*!< Reference to be used;RFAL_WUM_REFERENCE_AUTO sets it auto */ + bool autoAvg; /*!< Use the HW Auto Averaging feature */ + bool aaInclMeas; /*!< When AutoAvg is enabled, include IRQ measurement */ + rfalWumAAWeight aaWeight; /*!< When AutoAvg is enabled, last measure weight */ + }indAmp; /*!< Inductive Amplitude Configuration */ + struct{ + bool enabled; /*!< Inductive Phase measurement enabled */ + uint8_t delta; /*!< Delta between the reference and measurement to wake-up */ + uint8_t reference; /*!< Reference to be used;RFAL_WUM_REFERENCE_AUTO sets it auto */ + bool autoAvg; /*!< Use the HW Auto Averaging feature */ + bool aaInclMeas; /*!< When AutoAvg is enabled, include IRQ measurement */ + rfalWumAAWeight aaWeight; /*!< When AutoAvg is enabled, last measure weight */ + }indPha; /*!< Inductive Phase Configuration */ + struct{ + bool enabled; /*!< Capacitive measurement enabled */ + uint8_t delta; /*!< Delta between the reference and measurement to wake-up */ + uint8_t reference; /*!< Reference to be used;RFAL_WUM_REFERENCE_AUTO sets it auto */ + bool autoAvg; /*!< Use the HW Auto Averaging feature */ + bool aaInclMeas; /*!< When AutoAvg is enabled, include IRQ measurement */ + rfalWumAAWeight aaWeight; /*!< When AutoAvg is enabled, last measure weight */ + }cap; /*!< Capacitive Configuration */ +} rfalWakeUpConfig; + + +/*******************************************************************************/ + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + + +/*! + ***************************************************************************** + * \brief RFAL Initialize + * + * Initializes RFAL layer and the ST25R391x + * Ensures that ST25R391x is properly connected and returns error if any problem + * is detected + * + * \warning rfalAnalogConfigInitialize() should be called before so that + * the Analog config table has been previously initialized. + * + * \return ERR_HW_MISMATCH : Expected HW do not match or communication error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalInitialize( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Calibrate + * + * Performs necessary calibration of RF chip in case it is indicated by current + * register settings. E.g. antenna calibration and regulator calibration + * + * \return ERR_WRONG_STATE : RFAL not initialized + * \return ERR_NONE : No error + * + ***************************************************************************** + */ +ReturnCode rfalCalibrate( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Adjust Regulators + * + * Adjusts ST25R391x regulators + * + * \param[out] result : the result of the calibrate antenna in mV + * NULL if result not requested + * + * \return ERR_WRONG_STATE : RFAL not initialized + * \return ERR_NONE : No error + * + ***************************************************************************** + */ +ReturnCode rfalAdjustRegulators( uint16_t* result ); + + +/*! + ***************************************************************************** + * \brief RFAL Set System Callback + * + * Sets a callback for the driver to call when an event has occurred that + * may require the system to be notified + * + * \param[in] pFunc : method pointer for the upper layer callback + * + ***************************************************************************** + */ +void rfalSetUpperLayerCallback( rfalUpperLayerCallback pFunc ); + + +/*! + ***************************************************************************** + * \brief RFAL Set Pre Tx Callback + * + * Sets a callback for the driver to call before a Transceive + * + * \param[in] pFunc : method pointer for the Pre Tx callback + * + ***************************************************************************** + */ +void rfalSetPreTxRxCallback( rfalPreTxRxCallback pFunc ); + +/*! + ***************************************************************************** + * \brief RFAL Set Post Tx Callback + * + * Sets a callback for the driver to call after a Transceive + * + * \param[in] pFunc : method pointer for the Post Tx callback + * + ***************************************************************************** + */ +void rfalSetPostTxRxCallback( rfalPostTxRxCallback pFunc ); + +/*! + ***************************************************************************** + * \brief RFAL Deinitialize + * + * Deinitializes RFAL layer and the ST25R391x + * + * \return ERR_NONE : No error + * + ***************************************************************************** + */ +ReturnCode rfalDeinitialize( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Set Mode + * + * Sets the mode that RFAL will operate on the following communications. + * Proper initializations will be performed on the ST25R391x + * + * \warning bit rate value RFAL_BR_KEEP is not allowed, only in rfalSetBitRate() + * + * \warning the mode will be applied immediately on the RFchip regardless of + * any ongoing operations like Transceive, ListenMode + * + * \param[in] mode : mode for the RFAL/RFchip to perform + * \param[in] txBR : transmit bit rate + * \param[in] rxBR : receive bit rate + * + * \see rfalIsGTDone + * \see rfalMode + * + * \return ERR_WRONG_STATE : RFAL not initialized + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : No error + * + ***************************************************************************** + */ +ReturnCode rfalSetMode( rfalMode mode, rfalBitRate txBR, rfalBitRate rxBR ); + + +/*! + ***************************************************************************** + * \brief RFAL Get Mode + * + * Gets the mode that RFAL is set to operate + * + * \see rfalMode + * + * \return rfalMode : The current RFAL mode + ***************************************************************************** + */ +rfalMode rfalGetMode( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Set Bit Rate + * + * Sets the Tx and Rx bit rates with the given values + * The bit rate change is applied on the RF chip remaining in the same + * mode previous defined with rfalSetMode() + * + * If no mode is defined bit rates will not be applied and an error + * is returned + * + * \param[in] txBR : transmit bit rate + * \param[in] rxBR : receive bit rate + * + * \see rfalSetMode + * \see rfalMode + * \see rfalBitRate + * + * \return ERR_WRONG_STATE : RFAL not initialized + * \return ERR_PARAM : Invalid parameter + * \return ERR_NOT_IMPLEMENTED : Mode not implemented + * \return ERR_NONE : No error + * + ***************************************************************************** + */ +ReturnCode rfalSetBitRate( rfalBitRate txBR, rfalBitRate rxBR ); + + +/*! + ***************************************************************************** + * \brief RFAL Get Bit Rate + * + * Gets the Tx and Rx current bit rates + * + * If RFAL is not initialized or mode not set the bit rates return will + * be invalid RFAL_BR_KEEP + * + * \param[out] txBR : RFAL's current Tx Bit Rate + * \param[out] rxBR : RFAL's current Rx Bit Rate + * + * \see rfalSetBitRate + * \see rfalBitRate + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalGetBitRate( rfalBitRate *txBR, rfalBitRate *rxBR ); + + +/*! + ***************************************************************************** + * \brief Set Error Handling Mode + * + * Sets the error handling mode to be used by the RFAL + * + * \param[in] eHandling : the error handling mode + * + ***************************************************************************** + */ +void rfalSetErrorHandling( rfalEHandling eHandling ); + + +/*! + ***************************************************************************** + * \brief Get Error Handling Mode + * + * Gets the error handling mode currently used by the RFAL + * + * \return rfalEHandling : Current error handling mode + ***************************************************************************** + */ +rfalEHandling rfalGetErrorHandling( void ); + + +/*! + ***************************************************************************** + * \brief Set Observation Mode + * + * Sets ST25R391x observation modes for RF debug purposes + * + * \param[in] txMode : the observation mode to be used during transmission + * \param[in] rxMode : the observation mode to be used during reception + * + * \warning The Observation Mode is an advanced feature and should be set + * according to the documentation of the part number in use. + * Please refer to the corresponding Datasheet or Application Note(s) + ***************************************************************************** + */ +void rfalSetObsvMode( uint8_t txMode, uint8_t rxMode ); + + +/*! + ***************************************************************************** + * \brief Get Observation Mode + * + * Gets ST25R391x the current configured observation modes + * + * \param[in] txMode : the current observation mode configured for transmission + * \param[in] rxMode : the current observation mode configured for reception + * + ***************************************************************************** + */ +void rfalGetObsvMode( uint8_t* txMode, uint8_t* rxMode ); + + +/*! + ***************************************************************************** + * \brief Disable Observation Mode + * + * Disables the ST25R391x observation mode + ***************************************************************************** + */ +void rfalDisableObsvMode( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Set FDT Poll + * + * Sets the Frame Delay Time (FDT) to be used on the following + * communications. + * + * FDT Poll is the minimum time following a Poll Frame during + * which no subsequent Poll Frame can be sent (without a response from + * the Listener in between) + * FDTx,PP,MIN - Digital 1.1 6.10.2 & 7.9.2 & 8.7.2 + * + * \param[in] FDTPoll : Frame Delay Time in 1/fc cycles + * + ***************************************************************************** + */ +void rfalSetFDTPoll( uint32_t FDTPoll ); + + +/*! + ***************************************************************************** + * \brief RFAL Set FDT Poll + * + * Gets the current Frame Delay Time (FDT) + * + * FDT Poll is the minimum time following a Poll Frame during + * which no subsequent Poll Frame can be sent (without a response from + * the Listener in between) + * FDTx,PP,MIN - Digital 1.1 6.10.2 & 7.9.2 & 8.7.2 + * + * \return FDT : current FDT value in 1/fc cycles + * + ***************************************************************************** + */ +uint32_t rfalGetFDTPoll( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Set FDT Listen + * + * Sets the Frame Delay Time (FDT) Listen minimum to be used on the + * following communications. + * + * FDT Listen is the minimum time between a Poll Frame and a Listen Frame + * FDTx,LISTEN,MIN - Digital 1.1 6.10.1 & 7.9.1 & 8.7.1 + * + * \param[in] FDTListen : Frame Delay Time in 1/fc cycles + * + ***************************************************************************** + */ +void rfalSetFDTListen( uint32_t FDTListen ); + + +/*! + ***************************************************************************** + * \brief RFAL Set FDT Listen + * + * Gets the Frame Delay Time (FDT) Listen minimum + * + * FDT Listen is the minimum time between a Poll Frame and a Listen Frame + * FDTx,LISTEN,MIN - Digital 1.1 6.10.1 & 7.9.1 & 8.7.1 + * + * \return FDT : current FDT value in 1/fc cycles + * + ***************************************************************************** + */ +uint32_t rfalGetFDTListen( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Get GT + * + * Gets the current Guard Time (GT) + * + * GT is the minimum time when a device in Listen Mode is exposed to an + * unmodulated carrier + * + * \return GT : Guard Time in 1/fc cycles + * + ***************************************************************************** + */ +uint32_t rfalGetGT( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Set GT + * + * Sets the Guard Time (GT) to be used on the following communications. + * + * GT is the minimum time when a device in Listen Mode is exposed to an + * unmodulated carrier + * + * \param[in] GT : Guard Time in 1/fc cycles + * RFAL_GT_NONE if no GT should be applied + * + ***************************************************************************** + */ +void rfalSetGT( uint32_t GT ); + + +/*! + ***************************************************************************** + * \brief RFAL Is GT expired + * + * Checks whether the GT timer has expired + * + * \return true : GT has expired or not running + * \return false : GT is still running + * + ***************************************************************************** + */ +bool rfalIsGTExpired( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Turn Field On and Start GT + * + * Turns the Field On, performing Initial Collision Avoidance + * + * After Field On, if GT was set before, it starts the GT timer to be + * used on the following communications. + * + * \return ERR_RF_COLLISION : External field detected + * \return ERR_NONE : Field turned On + * + ***************************************************************************** + */ +ReturnCode rfalFieldOnAndStartGT( void ); + + +/*! + ***************************************************************************** + * \brief RFAL Turn Field Off + * + * Turns the Field Off + * + * \return ERR_NONE : Field turned Off + ***************************************************************************** + */ +ReturnCode rfalFieldOff( void ); + + + +/***************************************************************************** + * Transceive * + *****************************************************************************/ + +/*! + ***************************************************************************** + * \brief RFAL Set transceive context + * + * Set the context that will be used for the following Transceive + * Output and input buffers have to be passed and all other details prior to + * the Transceive itself has been started + * + * This method only sets the context, once set rfalWorker has + * to be executed until is done + * + * \param[in] ctx : the context for the following Transceive + * + * \see rfalWorker + * \see rfalGetTransceiveStatus + * + * \return ERR_NONE : Done with no error + * \return ERR_WRONG_STATE : Not initialized properly + * \return ERR_PARAM : Invalid parameter or configuration + ***************************************************************************** + */ +ReturnCode rfalStartTransceive( const rfalTransceiveContext *ctx ); + + +/*! + ***************************************************************************** + * \brief Get Transceive State + * + * Gets current Transceive internal State + * + * \return rfalTransceiveState : the current Transceive internal State + ***************************************************************************** + */ +rfalTransceiveState rfalGetTransceiveState( void ); + + +/*! + ***************************************************************************** + * \brief Get Transceive Status + * + * Gets current Transceive status + * + * \return ERR_NONE : Transceive done with no error + * \return ERR_BUSY : Transceive ongoing + * \return ERR_XXXX : Error occurred + * \return ERR_TIMEOUT : No response + * \return ERR_FRAMING : Framing error detected + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_LINK_LOSS : Link Loss - External Field is Off + * \return ERR_RF_COLLISION : Collision detected + * \return ERR_IO : Internal error + ***************************************************************************** + */ +ReturnCode rfalGetTransceiveStatus( void ); + + +/*! + ***************************************************************************** + * \brief Is Transceive in Tx + * + * Checks if Transceive is in Transmission state + * + * \return true Transmission ongoing + * \return false Not in transmission state + ***************************************************************************** + */ +bool rfalIsTransceiveInTx( void ); + + +/*! + ***************************************************************************** + * \brief Is Transceive in Rx + * + * Checks if Transceive is in Reception state + * + * \return true Transmission done/reception ongoing + * \return false Not in reception state + ***************************************************************************** + */ +bool rfalIsTransceiveInRx( void ); + + +/*! + ***************************************************************************** + * \brief Get Transceive RSSI + * + * Gets the RSSI value of the last executed Transceive in mV + * + * \param[out] rssi : RSSI value + * + * \return ERR_NOTSUPP : Feature not supported + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalGetTransceiveRSSI( uint16_t *rssi ); + + +/*! + ***************************************************************************** + * \brief RFAL Worker + * + * This runs RFAL layer, which drives the actual Transceive procedure + * It MUST be executed frequently in order to execute the RFAL internal + * states and perform the requested operations + * + ***************************************************************************** + */ +void rfalWorker( void ); + + +/***************************************************************************** + * ISO1443A * + *****************************************************************************/ + +/*! + ***************************************************************************** + * \brief Transceives an ISO14443A ShortFrame + * + * Sends REQA to detect if there is any PICC in the field + * + * \param[in] txCmd: Command to be sent: + * 0x52 WUPA / ALL_REQ + * 0x26 REQA / SENS_REQ + * + * \param[in] txCmd : type of short frame to be sent REQA or WUPA + * \param[out] rxBuf : buffer to place the response + * \param[in] rxBufLen : length of rxBuf + * \param[out] rxRcvdLen: received length + * \param[in] fwt : Frame Waiting Time in 1/fc + * + * \warning If fwt is set to RFAL_FWT_NONE it will make endlessly for + * a response, which on a blocking method may not be the + * desired usage + * + * \return ERR_NONE if there is response + * \return ERR_TIMEOUT if there is no response + * \return ERR_COLLISION collision has occurred + * + ***************************************************************************** + */ +ReturnCode rfalISO14443ATransceiveShortFrame( rfal14443AShortFrameCmd txCmd, uint8_t* rxBuf, uint8_t rxBufLen, uint16_t* rxRcvdLen, uint32_t fwt ); + + +/*! + ***************************************************************************** + * \brief Sends an ISO14443A Anticollision Frame + * + * This is use to perform ISO14443A anti-collision. + * \note Anticollision is sent without CRC + * + * + * \param[in] buf : reference to ANTICOLLISION command (with known UID if any) to be sent (also out param) + * reception will be place on this buf after bytesToSend + * \param[in] bytesToSend: reference number of full bytes to be sent (including CMD byte and SEL_PAR) + * if a collision occurs will contain the number of clear bytes + * \param[in] bitsToSend : reference to number of bits (0-7) to be sent; and received (also out param) + * if a collision occurs will indicate the number of clear bits (also out param) + * \param[out] rxLength : reference to the return the received length + * \param[in] fwt : Frame Waiting Time in 1/fc + * + * \return ERR_NONE if there is no error + ***************************************************************************** + */ +ReturnCode rfalISO14443ATransceiveAnticollisionFrame( uint8_t *buf, uint8_t *bytesToSend, uint8_t *bitsToSend, uint16_t *rxLength, uint32_t fwt ); + + +/***************************************************************************** + * FeliCa * + *****************************************************************************/ + +/*! + ***************************************************************************** + * \brief FeliCa Poll + * + * Sends a Poll Request and collects all Poll Responses according to the + * given slots + * + * + * \param[in] slots : number of slots for the Poll Request + * \param[in] sysCode : system code (SC) for the Poll Request + * \param[in] reqCode : request code (RC) for the Poll Request + * \param[out] pollResList : list of all responses + * \param[in] pollResListSize : number of responses that can be placed in pollResList + * \param[out] devicesDetected : number of cards found + * \param[out] collisionsDetected: number of collisions detected + * + * \return ERR_NONE if there is no error + * \return ERR_TIMEOUT if there is no response + ***************************************************************************** + */ +ReturnCode rfalFeliCaPoll( rfalFeliCaPollSlots slots, uint16_t sysCode, uint8_t reqCode, rfalFeliCaPollRes* pollResList, uint8_t pollResListSize, uint8_t *devicesDetected, uint8_t *collisionsDetected ); + + +/***************************************************************************** + * ISO15693 * + *****************************************************************************/ + +/*! + ***************************************************************************** + * \brief Sends an ISO15693 Anticollision Frame + * + * This send the Anticollision|Inventory frame (INVENTORY_REQ) + * + * \warning rxBuf must be able to contain the payload and CRC + * + * \param[in] txBuf : Buffer where outgoing message is located + * \param[in] txBufLen : Length of the outgoing message in bytes + * \param[out] rxBuf : Buffer where incoming message will be placed + * \param[in] rxBufLen : Maximum length of the incoming message in bytes + * \param[out] actLen : Actual received length in bits + * + * \return ERR_NONE : Transceive done with no error + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_IO : Internal error + ***************************************************************************** + */ +ReturnCode rfalISO15693TransceiveAnticollisionFrame( uint8_t *txBuf, uint8_t txBufLen, uint8_t *rxBuf, uint8_t rxBufLen, uint16_t *actLen ); + + +/*! + ***************************************************************************** + * \brief Sends an ISO15693 Anticollision EOF + * + * This sends the Anticollision|Inventory EOF used as a slot marker + * + * \warning rxBuf must be able to contain the payload and CRC + * + * \param[out] rxBuf : Buffer where incoming message will be placed + * \param[in] rxBufLen : Maximum length of the incoming message in bytes + * \param[out] actLen : Actual received length in bits + * + * \return ERR_NONE : Transceive done with no error + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_IO : Internal error + ***************************************************************************** + */ +ReturnCode rfalISO15693TransceiveEOFAnticollision( uint8_t *rxBuf, uint8_t rxBufLen, uint16_t *actLen ); + + +/*! + ***************************************************************************** + * \brief Sends an ISO15693 EOF + * + * This is method sends an ISO15693 (EoF) used for a Write operation + * + * \warning rxBuf must be able to contain the payload and CRC + * + * \param[out] rxBuf : Buffer where incoming message will be placed + * \param[in] rxBufLen : Maximum length of the incoming message in bytes + * \param[out] actLen : Actual received length in bytes + * + * \return ERR_NONE : Transceive done with no error + * \return ERR_IO : Internal error + ***************************************************************************** + */ +ReturnCode rfalISO15693TransceiveEOF( uint8_t *rxBuf, uint8_t rxBufLen, uint16_t *actLen ); + + +/*! + ***************************************************************************** + * \brief Transceive Blocking Tx + * + * This is method triggers a Transceive and executes it blocking until the + * Tx has been completed + * + * \param[in] txBuf : Buffer where outgoing message is located + * \param[in] txBufLen : Length of the outgoing message in bytes + * \param[out] rxBuf : Buffer where incoming message will be placed + * \param[in] rxBufLen : Maximum length of the incoming message in bytes + * \param[out] actLen : Actual received length in bits + * \param[in] flags : TransceiveFlags indication special handling + * \param[in] fwt : Frame Waiting Time in 1/fc + * + * \return ERR_NONE : Transceive done with no error + * \return ERR_BUSY : Transceive ongoing + * \return ERR_XXXX : Error occurred + * \return ERR_LINK_LOSS : Link Loss - External Field is Off + * \return ERR_RF_COLLISION : Collision detected + * \return ERR_IO : Internal error + ***************************************************************************** + */ +ReturnCode rfalTransceiveBlockingTx( uint8_t* txBuf, uint16_t txBufLen, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t* actLen, uint32_t flags, uint32_t fwt ); + +/*! + ***************************************************************************** + * \brief Transceive Blocking Rx + * + * This is method executes the reception of an ongoing Transceive triggered + * before by rfalTransceiveBlockingTx() + * + * \return ERR_NONE : Transceive done with no error + * \return ERR_BUSY : Transceive ongoing + * \return ERR_XXXX : Error occurred + * \return ERR_TIMEOUT : No response + * \return ERR_FRAMING : Framing error detected + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_LINK_LOSS : Link Loss - External Field is Off + * \return ERR_RF_COLLISION : Collision detected + * \return ERR_IO : Internal error + ***************************************************************************** + */ +ReturnCode rfalTransceiveBlockingRx( void ); + +/*! + ***************************************************************************** + * \brief Transceive Blocking + * + * This is method triggers a Transceive and executes it blocking until it + * has been completed + * + * \param[in] txBuf : Buffer where outgoing message is located + * \param[in] txBufLen : Length of the outgoing message in bytes + * \param[out] rxBuf : Buffer where incoming message will be placed + * \param[in] rxBufLen : Maximum length of the incoming message in bytes + * \param[out] actLen : Actual received length in bytes + * \param[in] flags : TransceiveFlags indication special handling + * \param[in] fwt : Frame Waiting Time in 1/fc + * + * \return ERR_NONE : Transceive done with no error + * \return ERR_BUSY : Transceive ongoing + * \return ERR_XXXX : Error occurred + * \return ERR_TIMEOUT : No response + * \return ERR_FRAMING : Framing error detected + * \return ERR_PAR : Parity error detected + * \return ERR_CRC : CRC error detected + * \return ERR_LINK_LOSS : Link Loss - External Field is Off + * \return ERR_RF_COLLISION : Collision detected + * \return ERR_IO : Internal error + ***************************************************************************** + */ +ReturnCode rfalTransceiveBlockingTxRx( uint8_t* txBuf, uint16_t txBufLen, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t* actLen, uint32_t flags, uint32_t fwt ); + + + +/***************************************************************************** + * Listen Mode * + *****************************************************************************/ + +/*! + ***************************************************************************** + * \brief Is external Field On + * + * Checks if external field (other peer/device) is on/detected + * + * \return true External field is On + * \return false No external field is detected + * + ***************************************************************************** + */ +bool rfalIsExtFieldOn( void ); + + +/*! + ***************************************************************************** + * \brief Listen Mode start + * + * Configures RF Chip to go into listen mode enabling the given technologies + * + * + * \param[in] lmMask: mask with the enabled/disabled listen modes + * use: RFAL_LM_MASK_NFCA ; RFAL_LM_MASK_NFCB ; + * RFAL_LM_MASK_NFCF ; RFAL_LM_MASK_ACTIVE_P2P + * \param[in] confA: pointer to Passive A configurations (NULL if disabled) + * \param[in] confB: pointer to Passive B configurations (NULL if disabled) + * \param[in] confF: pointer to Passive F configurations (NULL if disabled) + * \param[in] rxBuf: buffer to place incoming data + * \param[in] rxBufLen: length in bits of rxBuf + * \param[in] rxLen: pointer to write the data length in bits placed into rxBuf + * + * + * \return ERR_PARAM Invalid parameter + * \return ERR_REQUEST Invalid listen mode mask + * \return ERR_NONE Done with no error + * + ***************************************************************************** + */ +ReturnCode rfalListenStart( uint32_t lmMask, const rfalLmConfPA *confA, const rfalLmConfPB *confB, const rfalLmConfPF *confF, uint8_t *rxBuf, uint16_t rxBufLen, uint16_t *rxLen ); + + +/*! + ***************************************************************************** + * \brief Listen Mode start Sleeping + * + * + ***************************************************************************** + */ +ReturnCode rfalListenSleepStart( rfalLmState sleepSt, uint8_t *rxBuf, uint16_t rxBufLen, uint16_t *rxLen ); + + +/*! + ***************************************************************************** + * \brief Listen Mode Stop + * + * Disables the listen mode on the RF Chip + * + * \warning the listen mode will be disabled immediately on the RFchip regardless + * of any ongoing operations like Transceive + * + * \return ERR_NONE Done with no error + * + ***************************************************************************** + */ +ReturnCode rfalListenStop( void ); + + +/*! + ***************************************************************************** + * \brief Listen Mode get state + * + * Sets the new state of the Listen Mode and applies the necessary changes + * on the RF Chip + * + * \param[out] dataFlag: indicates that Listen Mode has rcvd data and caller + * must process it. The received message is located + * at the rxBuf passed on rfalListenStart(). + * rfalListenSetState() will clear this flag + * if NULL output parameter will no be written/returned + * \param[out] lastBR: bit rate detected of the last initiator request + * if NULL output parameter will no be written/returned + * + * \return rfalLmState RFAL_LM_STATE_NOT_INIT : LM not initialized properly + * Any Other : LM State + * + ***************************************************************************** + */ +rfalLmState rfalListenGetState( bool *dataFlag, rfalBitRate *lastBR ); + + +/*! + ***************************************************************************** + * \brief Listen Mode set state + * + * Sets the new state of the Listen Mode and applies the necessary changes + * on the RF Chip + * + * \param[in] newSt : New state to go to + * + * \return ERR_WRONG_STATE : Not initialized properly + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : Done with no error + * + ***************************************************************************** + */ +ReturnCode rfalListenSetState( rfalLmState newSt ); + + +/***************************************************************************** + * Wake-Up Mode * + *****************************************************************************/ + +/*! + ***************************************************************************** + * \brief Wake-Up Mode Start + * + * Sets the RF Chip in Low Power Wake-Up Mode according to the given + * configuration. + * + * \param[in] config : Generic Wake-Up configuration provided by lower + * layers. If NULL will automatically configure the + * Wake-Up mode + * + * \return ERR_WRONG_STATE : Not initialized properly + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : Done with no error + * + ***************************************************************************** + */ +ReturnCode rfalWakeUpModeStart( const rfalWakeUpConfig *config ); + + +/*! + ***************************************************************************** + * \brief Wake-Up Has Woke + * + * Returns true if the Wake-Up mode is enabled and it has already received + * the indication from the RF Chip that the surrounding environment has changed + * and flagged at least one wake-Up interrupt + * + * \return true : Wake-Up mode enabled and has received a wake-up IRQ + * \return false : no Wake-Up IRQ has been received + * + ***************************************************************************** + */ +bool rfalWakeUpModeHasWoke( void ); + + +/*! + ***************************************************************************** + * \brief Wake-Up Mode Stop + * + * Stops the Wake-Up Mode + * + * \return ERR_WRONG_STATE : Not initialized properly + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : Done with no error + * + ***************************************************************************** + */ +ReturnCode rfalWakeUpModeStop( void ); + + +#endif /* RFAL_RF_H */ + + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_st25tb.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_st25tb.h new file mode 100644 index 0000000..12a18a8 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_st25tb.h @@ -0,0 +1,355 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_st25tb.h + * + * \author Gustavo Patricio + * + * \brief Implementation of ST25TB interface + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup ST25TB + * \brief RFAL ST25TB Module + * @{ + * + */ + + +#ifndef RFAL_ST25TB_H +#define RFAL_ST25TB_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" +#include "rfal_nfcb.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_ST25TB_CHIP_ID_LEN 1U /*!< ST25TB chip ID length */ +#define RFAL_ST25TB_CRC_LEN 2U /*!< ST25TB CRC length */ +#define RFAL_ST25TB_UID_LEN 8U /*!< ST25TB Unique ID length */ +#define RFAL_ST25TB_BLOCK_LEN 4U /*!< ST25TB Data Block length */ + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ + + + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ +typedef uint8_t rfalSt25tbUID[RFAL_ST25TB_UID_LEN]; /*!< ST25TB UID type */ +typedef uint8_t rfalSt25tbBlock[RFAL_ST25TB_BLOCK_LEN]; /*!< ST25TB Block type */ + + +/*! ST25TB listener device (PICC) struct */ +typedef struct +{ + uint8_t chipID; /*!< Device's session Chip ID */ + rfalSt25tbUID UID; /*!< Device's UID */ + bool isDeselected; /*!< Device deselect flag */ +}rfalSt25tbListenDevice; + + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/*! + ***************************************************************************** + * \brief Initialize ST25TB Poller mode + * + * This methods configures RFAL RF layer to perform as a + * ST25TB Poller/RW including all default timings + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerInitialize( void ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Check Presence + * + * This method checks if a ST25TB Listen device (PICC) is present on the field + * by sending an Initiate command + * + * \param[out] chipId : if successfully retrieved, the device's chip ID + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_RF_COLLISION : Collision detected one or more device in the field + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerCheckPresence( uint8_t *chipId ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Collision Resolution + * + * This method performs ST25TB Collision resolution, selects the each device, + * retrieves its UID and then deselects. + * In case only one device is identified the ST25TB device is left in select + * state. + * + * \param[in] devLimit : device limit value, and size st25tbDevList + * \param[out] st25tbDevList : ST35TB listener device info + * \param[out] devCnt : Devices found counter + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_RF_COLLISION : Collision detected one or more device in the field + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerCollisionResolution( uint8_t devLimit, rfalSt25tbListenDevice *st25tbDevList, uint8_t *devCnt ); + +/*! + ***************************************************************************** + * \brief ST25TB Poller Initiate + * + * This method sends an Initiate command + * + * If a single device responds the chip ID will be retrieved + * + * \param[out] chipId : chip ID of the device + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerInitiate( uint8_t *chipId ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Pcall + * + * This method sends a Pcall command + * If successful the device's chip ID will be retrieved + * + * \param[out] chipId : Chip ID of the device + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerPcall( uint8_t *chipId ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Slot Marker + * + * This method sends a Slot Marker + * + * If a single device responds the chip ID will be retrieved + * + * \param[in] slotNum : Slot Number + * \param[out] chipIdRes : Chip ID of the device + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerSlotMarker( uint8_t slotNum, uint8_t *chipIdRes ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Select + * + * This method sends a ST25TB Select command with the given chip ID. + * + * If the device is already in Selected state and receives an incorrect chip + * ID, it goes into Deselected state + * + * \param[in] chipId : chip ID of the device to be selected + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerSelect( uint8_t chipId ); + + +/*! + ***************************************************************************** + * \brief ST25TB Get UID + * + * This method sends a Get_UID command + * + * If a single device responds the chip UID will be retrieved + * + * \param[out] UID : UID of the found device + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerGetUID( rfalSt25tbUID *UID ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Read Block + * + * This method reads a block of the ST25TB + * + * \param[in] blockAddress : address of the block to be read + * \param[out] blockData : location to place the data read from block + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerReadBlock( uint8_t blockAddress, rfalSt25tbBlock *blockData ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Write Block + * + * This method writes a block of the ST25TB + * + * \param[in] blockAddress : address of the block to be written + * \param[in] blockData : data to be written on the block + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerWriteBlock( uint8_t blockAddress, const rfalSt25tbBlock *blockData ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Completion + * + * This method sends a completion command to the ST25TB. After the + * completion the card no longer will reply to any command. + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected, invalid SENSB_RES received + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerCompletion( void ); + + +/*! + ***************************************************************************** + * \brief ST25TB Poller Reset to Inventory + * + * This method sends a Reset to Inventory command to the ST25TB. + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_TIMEOUT : Timeout error, no listener device detected + * \return ERR_PROTO : Protocol error detected, invalid SENSB_RES received + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalSt25tbPollerResetToInventory( void ); + + +#endif /* RFAL_ST25TB_H */ + +/** + * @} + * + * @} + * + * @} + */ + diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_st25xv.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_st25xv.h new file mode 100644 index 0000000..0927e0a --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_st25xv.h @@ -0,0 +1,729 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_st25xv.h + * + * \author Gustavo Patricio + * + * \brief NFC-V ST25 NFC-V Tag specific features + * + * This module provides support for ST's specific features available on + * NFC-V (ISO15693) tag families: ST25D, ST25TV, M24LR + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup ST25xV + * \brief RFAL ST25xV Module + * @{ + * + */ + +#ifndef RFAL_ST25xV_H +#define RFAL_ST25xV_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_nfc.h" +#include "rfal_rf.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + + +#define RFAL_NFCV_BLOCKNUM_M24LR_LEN 2U /*!< Block Number length of MR24LR tags: 16 bits */ +#define RFAL_NFCV_ST_IC_MFG_CODE 0x02 /*!< ST IC Mfg code (used for custom commands) */ + +/*! + ***************************************************************************** + * \brief NFC-V Poller Read Single Block (M24LR) + * + * Reads a Single Block from a M24LR tag which has the number of blocks + * bigger than 256 (M24LR16 ; M24LR64) + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * default: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] blockNum : Number of the block to read (16 bits) + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerM24LRReadSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Read Single Block (M24LR) + * + * Reads a Single Block from a M24LR tag which has the number of blocks + * bigger than 256 (M24LR16 ; M24LR64) using ST Fast mode + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * default: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] blockNum : Number of the block to read (16 bits) + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerM24LRFastReadSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Write Single Block (M24LR) + * + * Writes a Single Block from a M24LR tag which has the number of blocks + * bigger than 256 (M24LR16 ; M24LR64) + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be written + * if not provided Select mode will be used + * \param[in] blockNum : Number of the block to write (16 bits) + * \param[in] wrData : data to be written on the given block + * \param[in] blockLen : number of bytes of a block + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerM24LRWriteSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, const uint8_t* wrData, uint8_t blockLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Read Multiple Blocks (M24LR) + * + * Reads Multiple Blocks from a device from a M24LR tag which has the number of blocks + * bigger than 256 (M24LR16 ; M24LR64) + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] firstBlockNum : first block to be read (16 bits) + * \param[in] numOfBlocks : number of block to read + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerM24LRReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint16_t firstBlockNum, uint8_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Read Multiple Blocks (M24LR) + * + * Reads Multiple Blocks from a device from a M24LR tag which has the number of blocks + * bigger than 256 (M24LR16 ; M24LR64) using ST Fast mode + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] firstBlockNum : first block to be read (16 bits) + * \param[in] numOfBlocks : number of block to read + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerM24LRFastReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint16_t firstBlockNum, uint8_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Read Single Block + * + * Reads a Single Block from a device (VICC) using ST Fast mode + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] blockNum : Number of the block to read + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastReadSingleBlock( uint8_t flags, const uint8_t* uid, uint8_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Read Multiple Blocks + * + * Reads Multiple Blocks from a device (VICC) using ST Fast mode + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] firstBlockNum : first block to be read + * \param[in] numOfBlocks : number of block to read + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint8_t firstBlockNum, uint8_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Extended Read Single Block + * + * Reads a Single Block from a device (VICC) supporting extended commands using ST Fast mode + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] blockNum : Number of the block to read (16 bits) + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastExtendedReadSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Extended Read Multiple Blocks + * + * Reads Multiple Blocks from a device (VICC) supporting extended commands using ST Fast mode + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] firstBlockNum : first block to be read (16 bits) + * \param[in] numOfBlocks : number of consecutive blocks to read (16 bits) + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastExtReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint16_t firstBlockNum, uint16_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Read Configuration + * + * Reads static configuration registers at the Pointer address + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] pointer : Pointer address + * \param[out] regValue : Register value + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerReadConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t* regValue ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Write Configuration + * + * Writes static configuration registers at the Pointer address + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] pointer : Pointer address + * \param[in] regValue : Register value + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerWriteConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t regValue ); + + +/*! + ***************************************************************************** + * \brief NFC-V Poller Read Dynamic Configuration + * + * Reads dynamic registers at the Pointer address + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] pointer : Pointer address + * \param[out] regValue : Register value + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerReadDynamicConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t* regValue ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Write Dynamic Configuration + * + * Writes dynamic registers at the Pointer address + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] pointer : Pointer address + * \param[in] regValue : Register value + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerWriteDynamicConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t regValue ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Read Dynamic Configuration + * + * Reads dynamic registers at the Pointer address using ST Fast mode + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] pointer : Pointer address + * \param[out] regValue : Register value + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastReadDynamicConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t* regValue ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Write Dynamic Configuration + * + * Writes dynamic registers at the Pointer address using ST Fast mode + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] pointer : Pointer address + * \param[in] regValue : Register value + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastWriteDynamicConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t regValue ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Present Password + * + * Sends the Present Password command + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] pwdNum : Password number + * \param[in] pwd : Password + * \param[in] pwdLen : Password length + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerPresentPassword( uint8_t flags, const uint8_t* uid, uint8_t pwdNum, const uint8_t* pwd, uint8_t pwdLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Get Random Number + * + * Returns a 16 bit random number + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerGetRandomNumber( uint8_t flags, const uint8_t* uid, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Read Message length + * + * Sends a Read Message Length message to retrieve the value of MB_LEN_Dyn + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[out] msgLen : Message Length + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerReadMessageLength( uint8_t flags, const uint8_t* uid, uint8_t* msgLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Read Message length + * + * Sends a Fast Read Message Length message to retrieve the value of MB_LEN_Dyn using ST Fast mode. + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[out] msgLen : Message Length + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastReadMsgLength( uint8_t flags, const uint8_t* uid, uint8_t* msgLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Read Message + * + * Reads up to 256 bytes in the Mailbox from the location + * specified by MBpointer and sends back their value in the rxBuf response. + * First MailBox location is '00'. When Number of bytes is set to 00h + * and MBPointer is equals to 00h, the MB_LEN bytes of the full message + * are returned. Otherwise, Read Message command returns (Number of Bytes + 1) bytes + * (i.e. 01h returns 2 bytes, FFh returns 256 bytes). + * An error is reported if (Pointer + Nb of bytes + 1) is greater than the message length. + * RF Reading of the last byte of the mailbox message automatically clears b1 + * of MB_CTRL_Dyn HOST_PUT_MSG, and allows RF to put a new message. + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] mbPointer : MPpointer + * \param[in] numBytes : number of bytes + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerReadMessage( uint8_t flags, const uint8_t* uid, uint8_t mbPointer, uint8_t numBytes, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Read Message + * + * Reads up to 256 bytes in the Mailbox from the location + * specified by MBpointer and sends back their value in the rxBuf response using ST Fast mode. + * First MailBox location is '00'. When Number of bytes is set to 00h + * and MBPointer is equals to 00h, the MB_LEN bytes of the full message + * are returned. Otherwise, Read Message command returns (Number of Bytes + 1) bytes + * (i.e. 01h returns 2 bytes, FFh returns 256 bytes). + * An error is reported if (Pointer + Nb of bytes + 1) is greater than the message length. + * RF Reading of the last byte of the mailbox message automatically clears b1 + * of MB_CTRL_Dyn HOST_PUT_MSG, and allows RF to put a new message. + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] mbPointer : MPpointer + * \param[in] numBytes : number of bytes + * \param[out] rxBuf : buffer to store response (also with RES_FLAGS) + * \param[in] rxBufLen : length of rxBuf + * \param[out] rcvLen : number of bytes received + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastReadMessage( uint8_t flags, const uint8_t* uid, uint8_t mbPointer, uint8_t numBytes, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Write Message + * + * Sends Write message Command + * + * On receiving the Write Message command, the ST25DVxxx puts the data contained + * in the request into the Mailbox buffer, update the MB_LEN_Dyn register, and + * set bit RF_PUT_MSG in MB_CTRL_Dyn register. It then reports if the write operation was successful + * in the response. The ST25DVxxx Mailbox contains up to 256 data bytes which are filled from the + * first location '00'. MSGlength parameter of the command is the number of + * Data bytes minus 1 (00 for 1 byte of data, FFh for 256 bytes of data). + * Write Message could be executed only when Mailbox is accessible by RF. + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] msgLen : MSGLen number of Data bytes minus 1 + * \param[in] msgData : Message Data + * \param[out] txBuf : buffer to used to build the Write Message command + * \param[in] txBufLen : length of txBuf + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerWriteMessage( uint8_t flags, const uint8_t* uid, uint8_t msgLen, const uint8_t* msgData, uint8_t* txBuf, uint16_t txBufLen ); + +/*! + ***************************************************************************** + * \brief NFC-V Poller Fast Write Message + * + * Sends Fast Write message Command using ST Fast mode + * + * On receiving the Write Message command, the ST25DVxxx puts the data contained + * in the request into the Mailbox buffer, update the MB_LEN_Dyn register, and + * set bit RF_PUT_MSG in MB_CTRL_Dyn register. It then reports if the write operation was successful + * in the response. The ST25DVxxx Mailbox contains up to 256 data bytes which are filled from the + * first location '00'. MSGlength parameter of the command is the number of + * Data bytes minus 1 (00 for 1 byte of data, FFh for 256 bytes of data). + * Write Message could be executed only when Mailbox is accessible by RF. + * + * \param[in] flags : Flags to be used: Sub-carrier; Data_rate; Option + * for NFC-Forum use: RFAL_NFCV_REQ_FLAG_DEFAULT + * \param[in] uid : UID of the device to be put to be read + * if not provided Select mode will be used + * \param[in] msgLen : MSGLen number of Data bytes minus 1 + * \param[in] msgData : Message Data + * \param[out] txBuf : buffer to used to build the Write Message command + * \param[in] txBufLen : length of txBuf + * + * \return ERR_WRONG_STATE : RFAL not initialized or incorrect mode + * \return ERR_PARAM : Invalid parameters + * \return ERR_IO : Generic internal error + * \return ERR_CRC : CRC error detected + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_TIMEOUT : Timeout error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalST25xVPollerFastWriteMessage( uint8_t flags, const uint8_t* uid, uint8_t msgLen, const uint8_t* msgData, uint8_t* txBuf, uint16_t txBufLen ); + +#endif /* RFAL_ST25xV_H */ + +/** + * @} + * + * @} + * + * @} + */ + diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_t1t.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_t1t.h new file mode 100644 index 0000000..0f619f9 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_t1t.h @@ -0,0 +1,187 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_t1t.h + * + * \author Gustavo Patricio + * + * \brief Provides NFC-A T1T convenience methods and definitions + * + * This module provides an interface to perform as a NFC-A Reader/Writer + * to handle a Type 1 Tag T1T (Topaz) + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup T1T + * \brief RFAL T1T Module + * @{ + * + */ + + +#ifndef RFAL_T1T_H +#define RFAL_T1T_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ +#define RFAL_T1T_UID_LEN 4 /*!< T1T UID length of cascade level 1 only tag */ +#define RFAL_T1T_HR_LENGTH 2 /*!< T1T HR(Header ROM) length */ + +#define RFAL_T1T_HR0_NDEF_MASK 0xF0 /*!< T1T HR0 NDEF capability mask T1T 1.2 2.2.2 */ +#define RFAL_T1T_HR0_NDEF_SUPPORT 0x10 /*!< T1T HR0 NDEF capable value T1T 1.2 2.2.2 */ + + +/*! NFC-A T1T (Topaz) command set */ +typedef enum +{ + RFAL_T1T_CMD_RID = 0x78, /*!< T1T Read UID */ + RFAL_T1T_CMD_RALL = 0x00, /*!< T1T Read All */ + RFAL_T1T_CMD_READ = 0x01, /*!< T1T Read */ + RFAL_T1T_CMD_WRITE_E = 0x53, /*!< T1T Write with erase (single byte) */ + RFAL_T1T_CMD_WRITE_NE = 0x1A /*!< T1T Write with no erase (single byte) */ +} rfalT1Tcmds; + + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + + +/*! NFC-A T1T (Topaz) RID_RES Digital 1.1 10.6.2 & Table 50 */ +typedef struct +{ + uint8_t hr0; /*!< T1T Header ROM: HR0 */ + uint8_t hr1; /*!< T1T Header ROM: HR1 */ + uint8_t uid[RFAL_T1T_UID_LEN]; /*!< T1T UID */ +} rfalT1TRidRes; + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + + +/*! + ***************************************************************************** + * \brief Initialize NFC-A T1T Poller mode + * + * This methods configures RFAL RF layer to perform as a + * NFC-A T1T Poller/RW (Topaz) including all default timings + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT1TPollerInitialize( void ); + + +/*! + ***************************************************************************** + * \brief NFC-A T1T Poller RID + * + * This method reads the UID of a NFC-A T1T Listener device + * + * + * \param[out] ridRes : pointer to place the RID_RES + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT1TPollerRid( rfalT1TRidRes *ridRes ); + + +/*! + ***************************************************************************** + * \brief NFC-A T1T Poller RALL + * + * This method send a Read All command to a NFC-A T1T Listener device + * + * + * \param[in] uid : the UID of the device to read data + * \param[out] rxBuf : pointer to place the read data + * \param[in] rxBufLen : size of rxBuf + * \param[out] rxRcvdLen : actual received data + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT1TPollerRall( const uint8_t* uid, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rxRcvdLen ); + + +/*! + ***************************************************************************** + * \brief NFC-A T1T Poller Write + * + * This method writes the given data on the address of a NFC-A T1T Listener device + * + * + * \param[in] uid : the UID of the device to read data + * \param[in] address : address to write the data + * \param[in] data : the data to be written + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT1TPollerWrite( const uint8_t* uid, uint8_t address, uint8_t data ); + +#endif /* RFAL_T1T_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_t2t.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_t2t.h new file mode 100644 index 0000000..c153a89 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_t2t.h @@ -0,0 +1,153 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_t2t.h + * + * \author Gustavo Patricio + * + * \brief Provides NFC-A T2T convenience methods and definitions + * + * This module provides an interface to perform as a NFC-A Reader/Writer + * to handle a Type 2 Tag T2T + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup T2T + * \brief RFAL T2T Module + * @{ + * + */ + + +#ifndef RFAL_T2T_H +#define RFAL_T2T_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_T2T_BLOCK_LEN 4U /*!< T2T block length */ +#define RFAL_T2T_READ_DATA_LEN (4U * RFAL_T2T_BLOCK_LEN) /*!< T2T READ data length */ +#define RFAL_T2T_WRITE_DATA_LEN RFAL_T2T_BLOCK_LEN /*!< T2T WRITE data length */ + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/*! + ***************************************************************************** + * \brief NFC-A T2T Poller Read + * + * This method sends a Read command to a NFC-A T2T Listener device + * + * + * \param[in] blockNum : Number of the block to read + * \param[out] rxBuf : pointer to place the read data + * \param[in] rxBufLen : size of rxBuf (RFAL_T2T_READ_DATA_LEN) + * \param[out] rcvLen : actual received data + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT2TPollerRead( uint8_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); + + +/*! + ***************************************************************************** + * \brief NFC-A T2T Poller Write + * + * This method sends a Write command to a NFC-A T2T Listener device + * + * + * \param[in] blockNum : Number of the block to write + * \param[in] wrData : data to be written on the given block + * size must be of RFAL_T2T_WRITE_DATA_LEN + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT2TPollerWrite( uint8_t blockNum, const uint8_t* wrData ); + + +/*! + ***************************************************************************** + * \brief NFC-A T2T Poller Sector Select + * + * This method sends a Sector Select commands to a NFC-A T2T Listener device + * + * \param[in] sectorNum : Sector Number + * + * \return ERR_WRONG_STATE : RFAL not initialized or mode not set + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ + ReturnCode rfalT2TPollerSectorSelect( uint8_t sectorNum ); + +#endif /* RFAL_T2T_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Inc/rfal_t4t.h b/Software/fab-reader2-c/components/rfal/Inc/rfal_t4t.h new file mode 100644 index 0000000..0b49339 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Inc/rfal_t4t.h @@ -0,0 +1,365 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_t4t.h + * + * \author Gustavo Patricio + * + * \brief Provides convenience methods and definitions for T4T (ISO7816-4) + * + * This module provides an interface to exchange T4T APDUs according to + * NFC Forum T4T and ISO7816-4 + * + * This implementation was based on the following specs: + * - ISO/IEC 7816-4 3rd Edition 2013-04-15 + * - NFC Forum T4T Technical Specification 1.0 2017-08-28 + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-AL + * \brief RFAL Abstraction Layer + * @{ + * + * \addtogroup T4T + * \brief RFAL T4T Module + * @{ + * + */ + + +#ifndef RFAL_T4T_H +#define RFAL_T4T_H + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "platform.h" +#include "st_errno.h" +#include "rfal_rf.h" +#include "rfal_isoDep.h" + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_T4T_MAX_CAPDU_PROLOGUE_LEN 4U /*!< Command-APDU prologue length (CLA INS P1 P2) */ +#define RFAL_T4T_LE_LEN 1U /*!< Le Expected Response Length (short field coding) */ +#define RFAL_T4T_LC_LEN 1U /*!< Lc Data field length (short field coding) */ +#define RFAL_T4T_MAX_RAPDU_SW1SW2_LEN 2U /*!< SW1 SW2 length */ +#define RFAL_T4T_CLA 0x00U /*!< Class byte (contains 00h because secure message are not used) */ + +#define RFAL_T4T_ISO7816_P1_SELECT_BY_DF_NAME 0x04U /*!< P1 value for Select by name */ +#define RFAL_T4T_ISO7816_P1_SELECT_BY_FILEID 0x00U /*!< P1 value for Select by file identifier */ +#define RFAL_T4T_ISO7816_P2_SELECT_FIRST_OR_ONLY_OCCURENCE 0x00U /*!< b2b1 P2 value for First or only occurence */ +#define RFAL_T4T_ISO7816_P2_SELECT_RETURN_FCI_TEMPLATE 0x00U /*!< b4b3 P2 value for Return FCI template */ +#define RFAL_T4T_ISO7816_P2_SELECT_NO_RESPONSE_DATA 0x0CU /*!< b4b3 P2 value for No responce data */ + +#define RFAL_T4T_ISO7816_STATUS_COMPLETE 0x9000U /*!< Command completed \ Normal processing - No further qualification*/ + + +/* +****************************************************************************** +* GLOBAL VARIABLES +****************************************************************************** +*/ + + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ +/*! NFC-A T4T Command-APDU structure */ +typedef struct +{ + uint8_t CLA; /*!< Class byte */ + uint8_t INS; /*!< Instruction byte */ + uint8_t P1; /*!< Parameter byte 1 */ + uint8_t P2; /*!< Parameter byte 2 */ + uint8_t Lc; /*!< Data field length */ + bool LcFlag; /*!< Lc flag (append Lc when true) */ + uint8_t Le; /*!< Expected Response Length */ + bool LeFlag; /*!< Le flag (append Le when true) */ + + rfalIsoDepApduBufFormat *cApduBuf; /*!< Command-APDU buffer (Tx) */ + uint16_t *cApduLen; /*!< Command-APDU Length */ +}rfalT4tCApduParam; + +/*! NFC-A T4T Response-APDU structure */ +typedef struct +{ + rfalIsoDepApduBufFormat *rApduBuf; /*!< Response-APDU buffer (Rx) */ + uint16_t rcvdLen; /*!< Full response length */ + uint16_t rApduBodyLen; /*!< Response body length */ + uint16_t statusWord; /*!< R-APDU Status Word SW1|SW2 */ +}rfalT4tRApduParam; + + + +/*! NFC-A T4T command set T4T 1.0 & ISO7816-4 2013 Table 4 */ +typedef enum +{ + RFAL_T4T_INS_SELECT = 0xA4U, /*!< T4T Select */ + RFAL_T4T_INS_READBINARY = 0xB0U, /*!< T4T ReadBinary */ + RFAL_T4T_INS_UPDATEBINARY = 0xD6U, /*!< T4T UpdateBinay */ + RFAL_T4T_INS_READBINARY_ODO = 0xB1U, /*!< T4T ReadBinary using ODO */ + RFAL_T4T_INS_UPDATEBINARY_ODO = 0xD7U /*!< T4T UpdateBinay using ODO */ +} rfalT4tCmds; + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/*! + ***************************************************************************** + * \brief T4T Compose APDU + * + * This method computes a C-APDU according to NFC Forum T4T and ISO7816-4. + * + * If C-APDU contains data to be sent, it must be placed inside the buffer + * rfalT4tTxRxApduParam.txRx.cApduBuf.apdu and signaled by Lc + * + * To transceive the formed APDU the ISO-DEP layer shall be used + * + * \see rfalIsoDepStartApduTransceive() + * \see rfalIsoDepGetApduTransceiveStatus() + * \see rfalT4TPollerParseRAPDU() + * + * \warning The ISO-DEP module is used to perform the tranceive. Usually + * activation has been done via ISO-DEP activatiavtion. If not + * please call rfalIsoDepInitialize() before. + * + * \param[in,out] apduParam : APDU parameters + * apduParam.cApduLen will contain the APDU length + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerComposeCAPDU( rfalT4tCApduParam *apduParam ); + + +/*! + ***************************************************************************** + * \brief T4T Parse R-APDU + * + * This method parses a R-APDU according to NFC Forum T4T and ISO7816-4. + * It will extract the data length and check if the Satus word is expected. + * + * \param[in,out] apduParam : APDU parameters + * apduParam.rApduBodyLen will contain the data length + * apduParam.statusWord will contain the SW1 and SW2 + * + * \return ERR_REQUEST : Status word (SW1 SW2) different from 9000 + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerParseRAPDU( rfalT4tRApduParam *apduParam ); + +/*! + ***************************************************************************** + * \brief T4T Compose Select Application APDU + * + * This method computes a Select Application APDU according to NFC Forum T4T + * + * To transceive the formed APDU the ISO-DEP layer shall be used + * + * \see rfalIsoDepStartApduTransceive() + * \see rfalIsoDepGetApduTransceiveStatus() + * + * \param[out] cApduBuf : buffer where the C-APDU will be placed + * \param[in] aid : Application ID to be used + * \param[in] aidLen : Application ID length + * \param[out] cApduLen : Composed C-APDU length + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerComposeSelectAppl( rfalIsoDepApduBufFormat *cApduBuf, const uint8_t* aid, uint8_t aidLen, uint16_t *cApduLen ); + +/*! + ***************************************************************************** + * \brief T4T Compose Select File APDU + * + * This method computes a Select File APDU according to NFC Forum T4T + * + * To transceive the formed APDU the ISO-DEP layer shall be used + * + * \see rfalIsoDepStartApduTransceive() + * \see rfalIsoDepGetApduTransceiveStatus() + * + * \param[out] cApduBuf : buffer where the C-APDU will be placed + * \param[in] fid : File ID to be used + * \param[in] fidLen : File ID length + * \param[out] cApduLen : Composed C-APDU length + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerComposeSelectFile( rfalIsoDepApduBufFormat *cApduBuf, const uint8_t* fid, uint8_t fidLen, uint16_t *cApduLen ); + +/*! + ***************************************************************************** + * \brief T4T Compose Select File APDU for Mapping Version 1 + * + * This method computes a Select File APDU according to NFC Forum T4TOP_v1.0 + * + * To transceive the formed APDU the ISO-DEP layer shall be used + * + * \see rfalIsoDepStartApduTransceive() + * \see rfalIsoDepGetApduTransceiveStatus() + * + * \param[out] cApduBuf : buffer where the C-APDU will be placed + * \param[in] fid : File ID to be used + * \param[in] fidLen : File ID length + * \param[out] cApduLen : Composed C-APDU length + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerComposeSelectFileV1Mapping( rfalIsoDepApduBufFormat *cApduBuf, const uint8_t* fid, uint8_t fidLen, uint16_t *cApduLen ); + +/*! + ***************************************************************************** + * \brief T4T Compose Read Data APDU + * + * This method computes a Read Data APDU according to NFC Forum T4T + * + * To transceive the formed APDU the ISO-DEP layer shall be used + * + * \see rfalIsoDepStartApduTransceive() + * \see rfalIsoDepGetApduTransceiveStatus() + * + * \param[out] cApduBuf : buffer where the C-APDU will be placed + * \param[in] offset : File offset + * \param[in] expLen : Expected length (Le) + * \param[out] cApduLen : Composed C-APDU length + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerComposeReadData( rfalIsoDepApduBufFormat *cApduBuf, uint16_t offset, uint8_t expLen, uint16_t *cApduLen ); + +/*! + ***************************************************************************** + * \brief T4T Compose Read Data ODO APDU + * + * This method computes a Read Data ODO APDU according to NFC Forum T4T + * + * To transceive the formed APDU the ISO-DEP layer shall be used + * + * \see rfalIsoDepStartApduTransceive() + * \see rfalIsoDepGetApduTransceiveStatus() + * + * \param[out] cApduBuf : buffer where the C-APDU will be placed + * \param[in] offset : File offset + * \param[in] expLen : Expected length (Le) + * \param[out] cApduLen : Composed C-APDU length + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerComposeReadDataODO( rfalIsoDepApduBufFormat *cApduBuf, uint32_t offset, uint8_t expLen, uint16_t *cApduLen ); + +/*! + ***************************************************************************** + * \brief T4T Compose Write Data APDU + * + * This method computes a Write Data APDU according to NFC Forum T4T + * + * To transceive the formed APDU the ISO-DEP layer shall be used + * + * \see rfalIsoDepStartApduTransceive() + * \see rfalIsoDepGetApduTransceiveStatus() + * + * \param[out] cApduBuf : buffer where the C-APDU will be placed + * \param[in] offset : File offset + * \param[in] data : Data to be written + * \param[in] dataLen : Data length to be written (Lc) + * \param[out] cApduLen : Composed C-APDU length + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerComposeWriteData( rfalIsoDepApduBufFormat *cApduBuf, uint16_t offset, const uint8_t* data, uint8_t dataLen, uint16_t *cApduLen ); + +/*! + ***************************************************************************** + * \brief T4T Compose Write Data ODO APDU + * + * This method computes a Write Data ODO sAPDU according to NFC Forum T4T + * + * To transceive the formed APDU the ISO-DEP layer shall be used + * + * \see rfalIsoDepStartApduTransceive() + * \see rfalIsoDepGetApduTransceiveStatus() + * + * \param[out] cApduBuf : buffer where the C-APDU will be placed + * \param[in] offset : File offset + * \param[in] data : Data to be written + * \param[in] dataLen : Data length to be written (Lc) + * \param[out] cApduLen : Composed C-APDU length + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_PROTO : Protocol error + * \return ERR_NONE : No error + ***************************************************************************** + */ +ReturnCode rfalT4TPollerComposeWriteDataODO( rfalIsoDepApduBufFormat *cApduBuf, uint32_t offset, const uint8_t* data, uint8_t dataLen, uint16_t *cApduLen ); + +#endif /* RFAL_T4T_H */ + +/** + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_analogConfig.c b/Software/fab-reader2-c/components/rfal/Src/rfal_analogConfig.c new file mode 100644 index 0000000..64b646b --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_analogConfig.c @@ -0,0 +1,417 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_analogConfig.c + * + * \author bkam + * + * \brief Funcitons to manage and set analog settings. + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_analogConfig.h" +#include "rfal_chip.h" +#include "st_errno.h" +#include "platform.h" +#include "utils.h" + + +/* Check whether the Default Analog settings are to be used or custom ones */ +#ifdef RFAL_ANALOG_CONFIG_CUSTOM + extern const uint8_t* rfalAnalogConfigCustomSettings; + extern const uint16_t rfalAnalogConfigCustomSettingsLength; +#else + #include "rfal_analogConfigTbl.h" +#endif + +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ + + +#define RFAL_TEST_REG 0x0080U /*!< Test Register indicator */ + +/* + ****************************************************************************** + * MACROS + ****************************************************************************** + */ + +/* + ****************************************************************************** + * LOCAL DATA TYPES + ****************************************************************************** + */ + +#if RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG + static uint8_t gRfalAnalogConfig[RFAL_ANALOG_CONFIG_TBL_SIZE]; /*!< Analog Configuration Settings List */ +#endif /* RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG */ + + +/*! Struct for Analog Config Look Up Table Update */ +typedef struct { + const uint8_t *currentAnalogConfigTbl; /*!< Reference to start of current Analog Configuration */ + uint16_t configTblSize; /*!< Total size of Analog Configuration */ + bool ready; /*!< Indicate if Look Up Table is complete and ready for use */ +} rfalAnalogConfigMgmt; + +static rfalAnalogConfigMgmt gRfalAnalogConfigMgmt; /*!< Analog Configuration LUT management */ + +/* + ****************************************************************************** + * LOCAL TABLES + ****************************************************************************** + */ + +/* + ****************************************************************************** + * LOCAL FUNCTION PROTOTYPES + ****************************************************************************** + */ +static rfalAnalogConfigNum rfalAnalogConfigSearch( rfalAnalogConfigId configId, uint16_t *configOffset ); + +#if RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG + static void rfalAnalogConfigPtrUpdate( const uint8_t* analogConfigTbl ); +#endif /* RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG */ + +/* + ****************************************************************************** + * GLOBAL VARIABLE DEFINITIONS + ****************************************************************************** + */ + +/* + ****************************************************************************** + * GLOBAL FUNCTIONS + ****************************************************************************** + */ + +void rfalAnalogConfigInitialize( void ) +{ + /* Use default Analog configuration settings in Flash by default. */ + +/* Check whether the Default Analog settings are to be used or custom ones */ +#ifdef RFAL_ANALOG_CONFIG_CUSTOM + gRfalAnalogConfigMgmt.currentAnalogConfigTbl = (const uint8_t *)&rfalAnalogConfigCustomSettings; + gRfalAnalogConfigMgmt.configTblSize = rfalAnalogConfigCustomSettingsLength; +#else + gRfalAnalogConfigMgmt.currentAnalogConfigTbl = (const uint8_t *)&rfalAnalogConfigDefaultSettings; + gRfalAnalogConfigMgmt.configTblSize = sizeof(rfalAnalogConfigDefaultSettings); +#endif + + gRfalAnalogConfigMgmt.ready = true; +} /* rfalAnalogConfigInitialize() */ + + +bool rfalAnalogConfigIsReady( void ) +{ + return gRfalAnalogConfigMgmt.ready; +} + +ReturnCode rfalAnalogConfigListWriteRaw( const uint8_t *configTbl, uint16_t configTblSize ) +{ +#if RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG + + /* Check if the Configuration Table exceed the Table size */ + if ( configTblSize >= RFAL_ANALOG_CONFIG_TBL_SIZE ) + { + rfalAnalogConfigInitialize(); /* Revert to default Analog Configuration */ + return ERR_NOMEM; + } + + /* Check for invalid parameters */ + if( (configTbl == NULL) || (configTblSize == 0U) ) + { + return ERR_PARAM; + } + + /* NOTE: Function does not check for the validity of the Table contents (conf IDs, conf sets, register address) */ + ST_MEMCPY( gRfalAnalogConfig, configTbl, configTblSize ); + + /* Update the total size of configuration settings */ + gRfalAnalogConfigMgmt.configTblSize = configTblSize; + + rfalAnalogConfigPtrUpdate(gRfalAnalogConfig); + return ERR_NONE; + +#else + + // If Analog Configuration Update is to be disabled + NO_WARNING(configTbl); + NO_WARNING(configTblSize); + return ERR_REQUEST; + +#endif /* RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG */ +} + +ReturnCode rfalAnalogConfigListWrite( uint8_t more, const rfalAnalogConfig *config ) +{ +#if RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG + + rfalAnalogConfigId configId; + rfalAnalogConfigNum numConfig; + uint8_t configSize; + + if (true == gRfalAnalogConfigMgmt.ready) + { /* First Update to the Configuration list. */ + gRfalAnalogConfigMgmt.ready = false; // invalidate the config List + gRfalAnalogConfigMgmt.configTblSize = 0; // Clear the config List + } + + configId = GETU16(config->id); + + /* Check validity of the Configuration ID. */ + if ( (RFAL_ANALOG_CONFIG_TECH_RFU <= RFAL_ANALOG_CONFIG_ID_GET_TECH(configId)) + ||((RFAL_ANALOG_CONFIG_BITRATE_6780 < RFAL_ANALOG_CONFIG_ID_GET_BITRATE(configId)) && (RFAL_ANALOG_CONFIG_BITRATE_1OF4 > RFAL_ANALOG_CONFIG_ID_GET_BITRATE(configId))) + ||(RFAL_ANALOG_CONFIG_BITRATE_1OF256 < RFAL_ANALOG_CONFIG_ID_GET_BITRATE(configId)) + ) + { + rfalAnalogConfigInitialize(); /* Revert to default Analog Configuration */ + return ERR_PARAM; + } + + numConfig = config->num; + configSize = (uint8_t)(sizeof(rfalAnalogConfigId) + sizeof(rfalAnalogConfigNum) + (numConfig * sizeof(rfalAnalogConfigRegAddrMaskVal))); + + /* Check if the Configuration Set exceed the Table size. */ + if ( RFAL_ANALOG_CONFIG_TBL_SIZE <= (gRfalAnalogConfigMgmt.configTblSize + configSize) ) + { + rfalAnalogConfigInitialize(); /* Revert to default Analog Configuration */ + return ERR_NOMEM; + } + + /* NOTE: Function does not check for the validity of the Register Address. */ + ST_MEMCPY(&gRfalAnalogConfig[gRfalAnalogConfigMgmt.configTblSize], (const uint8_t*)config, configSize); + + /* Increment the total size of configuration settings. */ + gRfalAnalogConfigMgmt.configTblSize += configSize; + + /* Check if it is the last Analog Configuration to load. */ + if (RFAL_ANALOG_CONFIG_UPDATE_LAST == more) + { /* Update the Analog Configuration to the new settings. */ + rfalAnalogConfigPtrUpdate(gRfalAnalogConfig); + } + + return ERR_NONE; + +#else + + // If Analog Configuration Update is to be disabled + NO_WARNING(config); + NO_WARNING(more); + return ERR_DISABLED; + +#endif /* RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG */ + +} /* rfalAnalogConfigListUpdate() */ + +ReturnCode rfalAnalogConfigListReadRaw( uint8_t *tblBuf, uint16_t tblBufLen, uint16_t *configTblSize ) +{ + /* Check if the the current table will fit into the given buffer */ + if( tblBufLen < gRfalAnalogConfigMgmt.configTblSize ) + { + return ERR_NOMEM; + } + + /* Check for invalid parameters */ + if( configTblSize == NULL ) + { + return ERR_PARAM; + } + + /* Copy the whole Table to the given buffer */ + if( gRfalAnalogConfigMgmt.configTblSize > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY( tblBuf, gRfalAnalogConfigMgmt.currentAnalogConfigTbl, gRfalAnalogConfigMgmt.configTblSize ); + } + *configTblSize = gRfalAnalogConfigMgmt.configTblSize; + + return ERR_NONE; +} + +ReturnCode rfalAnalogConfigListRead( rfalAnalogConfigOffset *configOffset, uint8_t *more, rfalAnalogConfig *config, rfalAnalogConfigNum numConfig ) +{ + uint16_t configSize; + rfalAnalogConfigOffset offset = *configOffset; + rfalAnalogConfigNum numConfigSet; + + /* Check if the number of register-mask-value settings for the respective Configuration ID will fit into the buffer passed in. */ + if (gRfalAnalogConfigMgmt.currentAnalogConfigTbl[offset + sizeof(rfalAnalogConfigId)] > numConfig) + { + return ERR_NOMEM; + } + + /* Get the number of Configuration set */ + numConfigSet = gRfalAnalogConfigMgmt.currentAnalogConfigTbl[offset + sizeof(rfalAnalogConfigId)]; + + /* Pass Configuration Register-Mask-Value sets */ + configSize = (sizeof(rfalAnalogConfigId) + sizeof(rfalAnalogConfigNum) + (uint16_t)(numConfigSet * sizeof(rfalAnalogConfigRegAddrMaskVal))); + ST_MEMCPY( (uint8_t*) config + , &gRfalAnalogConfigMgmt.currentAnalogConfigTbl[offset] + , configSize + ); + *configOffset = offset + configSize; + + /* Check if it is the last Analog Configuration in the Table.*/ + *more = (uint8_t)((*configOffset >= gRfalAnalogConfigMgmt.configTblSize) ? RFAL_ANALOG_CONFIG_UPDATE_LAST + : RFAL_ANALOG_CONFIG_UPDATE_MORE); + + return ERR_NONE; +} /* rfalAnalogConfigListRead() */ + + +ReturnCode rfalSetAnalogConfig( rfalAnalogConfigId configId ) +{ + rfalAnalogConfigOffset configOffset = 0; + rfalAnalogConfigNum numConfigSet; + rfalAnalogConfigRegAddrMaskVal *configTbl; + ReturnCode retCode = ERR_NONE; + rfalAnalogConfigNum i; + + if (true != gRfalAnalogConfigMgmt.ready) + { + return ERR_REQUEST; + } + + /* Search LUT for the specific Configuration ID. */ + while(true) + { + numConfigSet = rfalAnalogConfigSearch(configId, &configOffset); + if( RFAL_ANALOG_CONFIG_LUT_NOT_FOUND == numConfigSet ) + { + break; + } + + configTbl = (rfalAnalogConfigRegAddrMaskVal *)( (uint32_t)gRfalAnalogConfigMgmt.currentAnalogConfigTbl + (uint32_t)configOffset); + /* Increment the offset to the next index to search from. */ + configOffset += (uint16_t)(numConfigSet * sizeof(rfalAnalogConfigRegAddrMaskVal)); + + if ((gRfalAnalogConfigMgmt.configTblSize + 1U) < configOffset) + { /* Error check make sure that the we do not access outside the configuration Table Size */ + return ERR_NOMEM; + } + + for ( i = 0; i < numConfigSet; i++) + { + if( (GETU16(configTbl[i].addr) & RFAL_TEST_REG) != 0U ) + { + EXIT_ON_ERR(retCode, rfalChipChangeTestRegBits( (GETU16(configTbl[i].addr) & ~RFAL_TEST_REG), configTbl[i].mask, configTbl[i].val) ); + } + else + { + EXIT_ON_ERR(retCode, rfalChipChangeRegBits( GETU16(configTbl[i].addr), configTbl[i].mask, configTbl[i].val) ); + } + } + + } /* while(found Analog Config Id) */ + + return retCode; + +} /* rfalSetAnalogConfig() */ + +/* + ****************************************************************************** + * LOCAL FUNCTIONS + ****************************************************************************** + */ + +/*! + ***************************************************************************** + * \brief Update the link to Analog Configuration LUT + * + * Update the link to the Analog Configuration LUT for the subsequent search + * of Analog Settings. + * + * \param[in] analogConfigTbl: reference to the start of the new Analog Configuration Table + * + ***************************************************************************** + */ +#if RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG +static void rfalAnalogConfigPtrUpdate( const uint8_t* analogConfigTbl ) +{ + + gRfalAnalogConfigMgmt.currentAnalogConfigTbl = analogConfigTbl; + gRfalAnalogConfigMgmt.ready = true; + +} /* rfalAnalogConfigPtrUpdate() */ +#endif /* RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG */ + + +/*! + ***************************************************************************** + * \brief Search the Analog Configuration LUT for a specific Configuration ID. + * + * Search the Analog Configuration LUT for the Configuration ID. + * + * \param[in] configId: Configuration ID to search for. + * \param[in] configOffset: Configuration Offset in Table + * + * \return number of Configuration Sets + * \return #RFAL_ANALOG_CONFIG_LUT_NOT_FOUND in case Configuration ID is not found. + ***************************************************************************** + */ +static rfalAnalogConfigNum rfalAnalogConfigSearch( rfalAnalogConfigId configId, uint16_t *configOffset ) +{ + rfalAnalogConfigId foundConfigId; + rfalAnalogConfigId configIdMaskVal; + const uint8_t *configTbl; + const uint8_t *currentConfigTbl; + uint16_t i; + + currentConfigTbl = gRfalAnalogConfigMgmt.currentAnalogConfigTbl; + configIdMaskVal = ((RFAL_ANALOG_CONFIG_POLL_LISTEN_MODE_MASK | RFAL_ANALOG_CONFIG_BITRATE_MASK) + |((RFAL_ANALOG_CONFIG_TECH_CHIP == RFAL_ANALOG_CONFIG_ID_GET_TECH(configId)) ? (RFAL_ANALOG_CONFIG_TECH_MASK | RFAL_ANALOG_CONFIG_CHIP_SPECIFIC_MASK) : configId) + |((RFAL_ANALOG_CONFIG_NO_DIRECTION == RFAL_ANALOG_CONFIG_ID_GET_DIRECTION(configId)) ? RFAL_ANALOG_CONFIG_DIRECTION_MASK : configId) + ); + + i = *configOffset; + while (i < gRfalAnalogConfigMgmt.configTblSize) + { + configTbl = ¤tConfigTbl[i]; + foundConfigId = GETU16(configTbl); + if (configId == (foundConfigId & configIdMaskVal)) + { + *configOffset = (uint16_t)(i + sizeof(rfalAnalogConfigId) + sizeof(rfalAnalogConfigNum)); + return configTbl[sizeof(rfalAnalogConfigId)]; + } + + /* If Config Id does not match, increment to next Configuration Id */ + i += (uint16_t)( sizeof(rfalAnalogConfigId) + sizeof(rfalAnalogConfigNum) + + (configTbl[sizeof(rfalAnalogConfigId)] * sizeof(rfalAnalogConfigRegAddrMaskVal) ) + ); + } /* for */ + + return RFAL_ANALOG_CONFIG_LUT_NOT_FOUND; +} /* rfalAnalogConfigSearch() */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_crc.c b/Software/fab-reader2-c/components/rfal/Src/rfal_crc.c new file mode 100644 index 0000000..27384ff --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_crc.c @@ -0,0 +1,86 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_crc.c + * + * \author Oliver Regenfelder + * + * \brief CRC calculation implementation + * + */ + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "rfal_crc.h" + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +static uint16_t rfalCrcUpdateCcitt(uint16_t crcSeed, uint8_t dataByte); + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ +uint16_t rfalCrcCalculateCcitt(uint16_t preloadValue, const uint8_t* buf, uint16_t length) +{ + uint16_t crc = preloadValue; + uint16_t index; + + for (index = 0; index < length; index++) + { + crc = rfalCrcUpdateCcitt(crc, buf[index]); + } + + return crc; +} + +/* +****************************************************************************** +* LOCAL FUNCTIONS +****************************************************************************** +*/ +static uint16_t rfalCrcUpdateCcitt(uint16_t crcSeed, uint8_t dataByte) +{ + uint16_t crc = crcSeed; + uint8_t dat = dataByte; + + dat ^= (uint8_t)(crc & 0xFFU); + dat ^= (dat << 4); + + crc = (crc >> 8)^(((uint16_t) dat) << 8)^(((uint16_t) dat) << 3)^(((uint16_t) dat) >> 4); + + return crc; +} + diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_dpo.c b/Software/fab-reader2-c/components/rfal/Src/rfal_dpo.c new file mode 100644 index 0000000..95f3b5e --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_dpo.c @@ -0,0 +1,240 @@ + +/****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * $Revision: $ + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_dpo.c + * + * \author Martin Zechleitner + * + * \brief Functions to manage and set dynamic power settings. + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_dpoTbl.h" +#include "rfal_dpo.h" +#include "platform.h" +#include "rfal_rf.h" +#include "rfal_chip.h" +#include "utils.h" + + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_DPO + #define RFAL_FEATURE_DPO false /* Dynamic Power Module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_DPO + +/* + ****************************************************************************** + * LOCAL DATA TYPES + ****************************************************************************** + */ + +static bool gRfalDpoIsEnabled = false; +static uint8_t* gRfalCurrentDpo; +static uint8_t gRfalDpoTableEntries; +static uint8_t gRfalDpo[RFAL_DPO_TABLE_SIZE_MAX]; +static uint8_t gRfalDpoTableEntry; +static rfalDpoMeasureFunc gRfalDpoMeasureCallback = NULL; + +/* + ****************************************************************************** + * GLOBAL FUNCTIONS + ****************************************************************************** + */ +void rfalDpoInitialize( void ) +{ + /* Use the default Dynamic Power values */ + gRfalCurrentDpo = (uint8_t*) rfalDpoDefaultSettings; + gRfalDpoTableEntries = (sizeof(rfalDpoDefaultSettings) / RFAL_DPO_TABLE_PARAMETER); + + ST_MEMCPY( gRfalDpo, gRfalCurrentDpo, sizeof(rfalDpoDefaultSettings) ); + + /* by default use amplitude measurement */ + gRfalDpoMeasureCallback = rfalChipMeasureAmplitude; + + /* by default DPO is disabled */ + gRfalDpoIsEnabled = false; + + gRfalDpoTableEntry = 0; +} + +void rfalDpoSetMeasureCallback( rfalDpoMeasureFunc pMeasureFunc ) +{ + gRfalDpoMeasureCallback = pMeasureFunc; +} + +/*******************************************************************************/ +ReturnCode rfalDpoTableWrite( rfalDpoEntry* powerTbl, uint8_t powerTblEntries ) +{ + uint8_t entry = 0; + + /* check if the table size parameter is too big */ + if( (powerTblEntries * RFAL_DPO_TABLE_PARAMETER) > RFAL_DPO_TABLE_SIZE_MAX) + { + return ERR_NOMEM; + } + + /* check if the first increase entry is 0xFF */ + if( (powerTblEntries == 0) || (powerTbl == NULL) ) + { + return ERR_PARAM; + } + + /* check if the entries of the dynamic power table are valid */ + for (entry = 0; entry < powerTblEntries; entry++) + { + if(powerTbl[entry].inc < powerTbl[entry].dec) + { + return ERR_PARAM; + } + } + + /* copy the data set */ + ST_MEMCPY( gRfalDpo, powerTbl, (powerTblEntries * RFAL_DPO_TABLE_PARAMETER) ); + gRfalCurrentDpo = gRfalDpo; + gRfalDpoTableEntries = powerTblEntries; + + if(gRfalDpoTableEntry > powerTblEntries) + { + /* is always greater then zero, otherwise we already returned ERR_PARAM */ + gRfalDpoTableEntry = (powerTblEntries - 1); + } + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalDpoTableRead( rfalDpoEntry* tblBuf, uint8_t tblBufEntries, uint8_t* tableEntries ) +{ + /* wrong request */ + if( (tblBuf == NULL) || (tblBufEntries < gRfalDpoTableEntries) || (tableEntries == NULL) ) + { + return ERR_PARAM; + } + + /* Copy the whole Table to the given buffer */ + ST_MEMCPY( tblBuf, gRfalCurrentDpo, (tblBufEntries * RFAL_DPO_TABLE_PARAMETER) ); + *tableEntries = gRfalDpoTableEntries; + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalDpoAdjust( void ) +{ + uint8_t refValue = 0; + rfalDpoEntry* dpoTable = (rfalDpoEntry*) gRfalCurrentDpo; + + /* Check if the Power Adjustment is disabled and * + * if the callback to the measurement method is properly set */ + if( (gRfalCurrentDpo == NULL) || (!gRfalDpoIsEnabled) || (gRfalDpoMeasureCallback == NULL) ) + { + return ERR_PARAM; + } + + /* Ensure that the current mode is Passive Poller */ + if( !rfalIsModePassivePoll( rfalGetMode() ) ) + { + return ERR_WRONG_STATE; + } + + /* Ensure a proper measure reference value */ + if( ERR_NONE != gRfalDpoMeasureCallback( &refValue ) ) + { + return ERR_IO; + } + + + /* Increase the output power */ + if( refValue >= dpoTable[gRfalDpoTableEntry].inc ) + { + /* the top of the table represents the highest amplitude value*/ + if( gRfalDpoTableEntry == 0 ) + { + /* check if the maximum driver value has been reached */ + return ERR_NONE; + } + /* go up in the table to decrease the driver resistance */ + gRfalDpoTableEntry--; + } + else + { + /* decrease the output power */ + if(refValue <= dpoTable[gRfalDpoTableEntry].dec) + { + /* The bottom is the highest possible value */ + if( (gRfalDpoTableEntry + 1) >= gRfalDpoTableEntries) + { + /* check if the minimum driver value has been reached */ + return ERR_NONE; + } + /* go down in the table to increase the driver resistance */ + gRfalDpoTableEntry++; + } + else + { + /* do not write the driver again with the same value */ + } + } + + /* get the new value for RFO resistance form the table and apply the new RFO resistance setting */ + rfalChipSetRFO( dpoTable[gRfalDpoTableEntry].rfoRes ); + return ERR_NONE; +} + +/*******************************************************************************/ +rfalDpoEntry* rfalDpoGetCurrentTableEntry( void ) +{ + rfalDpoEntry* dpoTable = (rfalDpoEntry*) gRfalCurrentDpo; + return &dpoTable[gRfalDpoTableEntry]; +} + +/*******************************************************************************/ +void rfalDpoSetEnabled( bool enable ) +{ + gRfalDpoIsEnabled = enable; +} + +/*******************************************************************************/ +bool rfalDpoIsEnabled( void ) +{ + return gRfalDpoIsEnabled; +} + +#endif /* RFAL_FEATURE_DPO */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_iso15693_2.c b/Software/fab-reader2-c/components/rfal/Src/rfal_iso15693_2.c new file mode 100644 index 0000000..94ea414 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_iso15693_2.c @@ -0,0 +1,534 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_iso15693_2.c + * + * \author Ulrich Herrmann + * + * \brief Implementation of ISO-15693-2 + * + */ + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "rfal_iso15693_2.h" +#include "rfal_crc.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_NFCV + #define RFAL_FEATURE_NFCV false /* NFC-V module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_NFCV + +/* +****************************************************************************** +* LOCAL MACROS +****************************************************************************** +*/ + +//#define ISO_15693_DEBUG dbgLog +#define ISO_15693_DEBUG(...) /*!< Macro for the log method */ + +/* +****************************************************************************** +* LOCAL DEFINES +****************************************************************************** +*/ +#define ISO15693_DAT_SOF_1_4 0x21 /* LSB constants */ +#define ISO15693_DAT_EOF_1_4 0x04 +#define ISO15693_DAT_00_1_4 0x02 +#define ISO15693_DAT_01_1_4 0x08 +#define ISO15693_DAT_10_1_4 0x20 +#define ISO15693_DAT_11_1_4 0x80 + +#define ISO15693_DAT_SOF_1_256 0x81 +#define ISO15693_DAT_EOF_1_256 0x04 +#define ISO15693_DAT_SLOT0_1_256 0x02 +#define ISO15693_DAT_SLOT1_1_256 0x08 +#define ISO15693_DAT_SLOT2_1_256 0x20 +#define ISO15693_DAT_SLOT3_1_256 0x80 + +#define ISO15693_PHY_DAT_MANCHESTER_1 0xaaaa + +#define ISO15693_PHY_BIT_BUFFER_SIZE 1000 /*!< size of the receiving buffer. Might be adjusted if longer datastreams are expected. */ + + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ +static iso15693PhyConfig_t iso15693PhyConfig; /*!< current phy configuration */ + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +static ReturnCode iso15693PhyVCDCode1Of4(const uint8_t data, uint8_t* outbuffer, uint16_t maxOutBufLen, uint16_t* outBufLen); +static ReturnCode iso15693PhyVCDCode1Of256(const uint8_t data, uint8_t* outbuffer, uint16_t maxOutBufLen, uint16_t* outBufLen); + + + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ +ReturnCode iso15693PhyConfigure(const iso15693PhyConfig_t* config, const struct iso15693StreamConfig ** needed_stream_config ) +{ + static struct iso15693StreamConfig stream_config = { /* MISRA 8.9 */ + .useBPSK = 0, /* 0: subcarrier, 1:BPSK */ + .din = 5, /* 2^5*fc = 423750 Hz: divider for the in subcarrier frequency */ + .dout = 7, /*!< 2^7*fc = 105937 : divider for the in subcarrier frequency */ + .report_period_length = 3, /*!< 8=2^3 the length of the reporting period */ + }; + + + /* make a copy of the configuration */ + ST_MEMCPY( (uint8_t*)&iso15693PhyConfig, (const uint8_t*)config, sizeof(iso15693PhyConfig_t)); + + if ( config->speedMode <= 3U) + { /* If valid speed mode adjust report period accordingly */ + stream_config.report_period_length = (3U - (uint8_t)config->speedMode); + } + else + { /* If invalid default to normal (high) speed */ + stream_config.report_period_length = 3; + } + + *needed_stream_config = &stream_config; + + return ERR_NONE; +} + +ReturnCode iso15693PhyGetConfiguration(iso15693PhyConfig_t* config) +{ + ST_MEMCPY(config, &iso15693PhyConfig, sizeof(iso15693PhyConfig_t)); + + return ERR_NONE; +} + +ReturnCode iso15693VCDCode(uint8_t* buffer, uint16_t length, bool sendCrc, bool sendFlags, bool picopassMode, + uint16_t *subbit_total_length, uint16_t *offset, + uint8_t* outbuf, uint16_t outBufSize, uint16_t* actOutBufSize) +{ + ReturnCode err = ERR_NONE; + uint8_t eof, sof; + uint8_t transbuf[2]; + uint16_t crc = 0; + ReturnCode (*txFunc)(const uint8_t data, uint8_t* outbuffer, uint16_t maxOutBufLen, uint16_t* outBufLen); + uint8_t crc_len; + uint8_t* outputBuf; + uint16_t outputBufSize; + + crc_len = (uint8_t)((sendCrc)?2:0); + + *actOutBufSize = 0; + + if (ISO15693_VCD_CODING_1_4 == iso15693PhyConfig.coding) + { + sof = ISO15693_DAT_SOF_1_4; + eof = ISO15693_DAT_EOF_1_4; + txFunc = iso15693PhyVCDCode1Of4; + *subbit_total_length = ( + ( 1U /* SOF */ + + ((length + (uint16_t)crc_len) * 4U) + + 1U) /* EOF */ + ); + if (outBufSize < 5U) { /* 5 should be safe: enough for sof + 1byte data in 1of4 */ + return ERR_NOMEM; + } + } + else + { + sof = ISO15693_DAT_SOF_1_256; + eof = ISO15693_DAT_EOF_1_256; + txFunc = iso15693PhyVCDCode1Of256; + *subbit_total_length = ( + ( 1U /* SOF */ + + ((length + (uint16_t)crc_len) * 64U) + + 1U) /* EOF */ + ); + + if (*offset != 0U) + { + if (outBufSize < 64U) { /* 64 should be safe: enough a single byte data in 1of256 */ + return ERR_NOMEM; + } + } + else + { + if (outBufSize < 65U) { /* At beginning of a frame we need at least 65 bytes to start: enough for sof + 1byte data in 1of256 */ + return ERR_NOMEM; + } + } + } + + if (length == 0U) + { + *subbit_total_length = 1; + } + + if ((length != 0U) && (0U == *offset) && sendFlags && !picopassMode) + { + /* set high datarate flag */ + buffer[0] |= (uint8_t)ISO15693_REQ_FLAG_HIGH_DATARATE; + /* clear sub-carrier flag - we only support single sub-carrier */ + buffer[0] = (uint8_t)(buffer[0] & ~ISO15693_REQ_FLAG_TWO_SUBCARRIERS); /* MISRA 10.3 */ + } + + outputBuf = outbuf; /* MISRA 17.8: Use intermediate variable */ + outputBufSize = outBufSize; /* MISRA 17.8: Use intermediate variable */ + + /* Send SOF if at 0 offset */ + if ((length != 0U) && (0U == *offset)) + { + *outputBuf = sof; + (*actOutBufSize)++; + outputBufSize--; + outputBuf++; + } + + while ((*offset < length) && (err == ERR_NONE)) + { + uint16_t filled_size; + /* send data */ + err = txFunc(buffer[*offset], outputBuf, outputBufSize, &filled_size); + (*actOutBufSize) += filled_size; + outputBuf = &outputBuf[filled_size]; /* MISRA 18.4: Avoid pointer arithmetic */ + outputBufSize -= filled_size; + if (err == ERR_NONE) { + (*offset)++; + } + } + if (err != ERR_NONE) { + return ERR_AGAIN; + } + + while ((err == ERR_NONE) && sendCrc && (*offset < (length + 2U))) + { + uint16_t filled_size; + if (0U==crc) + { + crc = rfalCrcCalculateCcitt( (uint16_t) ((picopassMode) ? 0xE012U : 0xFFFFU), /* In PicoPass Mode a different Preset Value is used */ + ((picopassMode) ? (buffer + 1U) : buffer), /* CMD byte is not taken into account in PicoPass mode */ + ((picopassMode) ? (length - 1U) : length)); /* CMD byte is not taken into account in PicoPass mode */ + + crc = (uint16_t)((picopassMode) ? crc : ~crc); + } + /* send crc */ + transbuf[0] = (uint8_t)(crc & 0xffU); + transbuf[1] = (uint8_t)((crc >> 8) & 0xffU); + err = txFunc(transbuf[*offset - length], outputBuf, outputBufSize, &filled_size); + (*actOutBufSize) += filled_size; + outputBuf = &outputBuf[filled_size]; /* MISRA 18.4: Avoid pointer arithmetic */ + outputBufSize -= filled_size; + if (err == ERR_NONE) { + (*offset)++; + } + } + if (err != ERR_NONE) { + return ERR_AGAIN; + } + + if ((!sendCrc && (*offset == length)) + || (sendCrc && (*offset == (length + 2U)))) + { + *outputBuf = eof; + (*actOutBufSize)++; + outputBufSize--; + outputBuf++; + } + else + { + return ERR_AGAIN; + } + + return err; +} + +ReturnCode iso15693VICCDecode(const uint8_t *inBuf, + uint16_t inBufLen, + uint8_t* outBuf, + uint16_t outBufLen, + uint16_t* outBufPos, + uint16_t* bitsBeforeCol, + uint16_t ignoreBits, + bool picopassMode ) +{ + ReturnCode err = ERR_NONE; + uint16_t crc; + uint16_t mp; /* Current bit position in manchester bit inBuf*/ + uint16_t bp; /* Current bit position in outBuf */ + + *bitsBeforeCol = 0; + *outBufPos = 0; + + /* first check for valid SOF. Since it starts with 3 unmodulated pulses it is 0x17. */ + if ((inBuf[0] & 0x1fU) != 0x17U) + { + ISO_15693_DEBUG("0x%x\n", iso15693PhyBitBuffer[0]); + return ERR_FRAMING; + } + ISO_15693_DEBUG("SOF\n"); + + if (outBufLen == 0U) + { + return ERR_NONE; + } + + mp = 5; /* 5 bits were SOF, now manchester starts: 2 bits per payload bit */ + bp = 0; + + ST_MEMSET(outBuf,0,outBufLen); + + if (inBufLen == 0U) + { + return ERR_CRC; + } + + for ( ; mp < ((inBufLen * 8U) - 2U); mp+=2U ) + { + bool isEOF = false; + + uint8_t man; + man = (inBuf[mp/8U] >> (mp%8U)) & 0x1U; + man |= ((inBuf[(mp+1U)/8U] >> ((mp+1U)%8U)) & 0x1U) << 1; + if (1U == man) + { + bp++; + } + if (2U == man) + { + outBuf[bp/8U] = (uint8_t)(outBuf[bp/8U] | (1U <<(bp%8U))); /* MISRA 10.3 */ + bp++; + } + if ((bp%8U) == 0U) + { /* Check for EOF */ + ISO_15693_DEBUG("ceof %hhx %hhx\n", inBuf[mp/8U], inBuf[mp/8+1]); + if ( ((inBuf[mp/8U] & 0xe0U) == 0xa0U) + &&(inBuf[(mp/8U)+1U] == 0x03U)) + { /* Now we know that it was 10111000 = EOF */ + ISO_15693_DEBUG("EOF\n"); + isEOF = true; + } + } + if ( ((0U == man) || (3U == man)) && !isEOF ) + { + if (bp >= ignoreBits) + { + err = ERR_RF_COLLISION; + } + else + { + /* ignored collision: leave as 0 */ + bp++; + } + } + if ( (bp >= (outBufLen * 8U)) || (err == ERR_RF_COLLISION) || isEOF ) + { /* Don't write beyond the end */ + break; + } + } + + *outBufPos = (bp / 8U); + *bitsBeforeCol = bp; + + if (err != ERR_NONE) + { + return err; + } + + if ((bp%8U) != 0U) + { + return ERR_CRC; + } + + if (*outBufPos > 2U) + { + /* finally, check crc */ + ISO_15693_DEBUG("Calculate CRC, val: 0x%x, outBufLen: ", *outBuf); + ISO_15693_DEBUG("0x%x ", *outBufPos - 2); + + crc = rfalCrcCalculateCcitt(((picopassMode) ? 0xE012U : 0xFFFFU), outBuf, *outBufPos - 2U); + crc = (uint16_t)((picopassMode) ? crc : ~crc); + + if (((crc & 0xffU) == outBuf[*outBufPos-2U]) && + (((crc >> 8U) & 0xffU) == outBuf[*outBufPos-1U])) + { + err = ERR_NONE; + ISO_15693_DEBUG("OK\n"); + } + else + { + ISO_15693_DEBUG("error! Expected: 0x%x, got ", crc); + ISO_15693_DEBUG("0x%hhx 0x%hhx\n", outBuf[*outBufPos-2], outBuf[*outBufPos-1]); + err = ERR_CRC; + } + } + else + { + err = ERR_CRC; + } + + return err; +} + +/* +****************************************************************************** +* LOCAL FUNCTIONS +****************************************************************************** +*/ +/*! + ***************************************************************************** + * \brief Perform 1 of 4 coding and send coded data + * + * This function takes \a length bytes from \a buffer, perform 1 of 4 coding + * (see ISO15693-2 specification) and sends the data using stream mode. + * + * \param[in] sendSof : send SOF prior to data. + * \param[in] buffer : data to send. + * \param[in] length : number of bytes to send. + * + * \return ERR_IO : Error during communication. + * \return ERR_NONE : No error. + * + ***************************************************************************** + */ +static ReturnCode iso15693PhyVCDCode1Of4(const uint8_t data, uint8_t* outbuffer, uint16_t maxOutBufLen, uint16_t* outBufLen) +{ + uint8_t tmp; + ReturnCode err = ERR_NONE; + uint16_t a; + uint8_t* outbuf = outbuffer; + + *outBufLen = 0; + + if (maxOutBufLen < 4U) { + return ERR_NOMEM; + } + + tmp = data; + for (a = 0; a < 4U; a++) + { + switch (tmp & 0x3U) + { + case 0: + *outbuf = ISO15693_DAT_00_1_4; + break; + case 1: + *outbuf = ISO15693_DAT_01_1_4; + break; + case 2: + *outbuf = ISO15693_DAT_10_1_4; + break; + case 3: + *outbuf = ISO15693_DAT_11_1_4; + break; + default: + /* MISRA 16.4: mandatory default statement */ + break; + } + outbuf++; + (*outBufLen)++; + tmp >>= 2; + } + return err; +} + +/*! + ***************************************************************************** + * \brief Perform 1 of 256 coding and send coded data + * + * This function takes \a length bytes from \a buffer, perform 1 of 256 coding + * (see ISO15693-2 specification) and sends the data using stream mode. + * \note This function sends SOF prior to the data. + * + * \param[in] sendSof : send SOF prior to data. + * \param[in] buffer : data to send. + * \param[in] length : number of bytes to send. + * + * \return ERR_IO : Error during communication. + * \return ERR_NONE : No error. + * + ***************************************************************************** + */ +static ReturnCode iso15693PhyVCDCode1Of256(const uint8_t data, uint8_t* outbuffer, uint16_t maxOutBufLen, uint16_t* outBufLen) +{ + uint8_t tmp; + ReturnCode err = ERR_NONE; + uint16_t a; + uint8_t* outbuf = outbuffer; + + *outBufLen = 0; + + if (maxOutBufLen < 64U) { + return ERR_NOMEM; + } + + tmp = data; + for (a = 0; a < 64U; a++) + { + switch (tmp) + { + case 0: + *outbuf = ISO15693_DAT_SLOT0_1_256; + break; + case 1: + *outbuf = ISO15693_DAT_SLOT1_1_256; + break; + case 2: + *outbuf = ISO15693_DAT_SLOT2_1_256; + break; + case 3: + *outbuf = ISO15693_DAT_SLOT3_1_256; + break; + default: + *outbuf = 0; + break; + } + outbuf++; + (*outBufLen)++; + tmp -= 4U; + } + + return err; +} + +#endif /* RFAL_FEATURE_NFCV */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_isoDep.c b/Software/fab-reader2-c/components/rfal/Src/rfal_isoDep.c new file mode 100644 index 0000000..2048841 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_isoDep.c @@ -0,0 +1,2552 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: NFCC firmware + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_isoDep.c + * + * \author Gustavo Patricio + * + * \brief Implementation of ISO-DEP protocol + * + * This implementation was based on the following specs: + * - ISO/IEC 14443-4 2nd Edition 2008-07-15 + * - NFC Forum Digital Protocol 1.1 2014-01-14 + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ + +#include "rfal_isoDep.h" +#include "rfal_rf.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_ISO_DEP + #define RFAL_FEATURE_ISO_DEP false /* ISO-DEP module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_ISO_DEP + +#if ( !RFAL_FEATURE_ISO_DEP_POLL && !RFAL_FEATURE_ISO_DEP_LISTEN ) + #error " RFAL: Invalid ISO-DEP Configuration. Please select at least one mode: Poller and/or Listener. " +#endif + +/* Check for valid I-Block length [RFAL_ISODEP_FSX_16 ; RFAL_ISODEP_FSX_4096]*/ +#if( (RFAL_FEATURE_ISO_DEP_IBLOCK_MAX_LEN > 4096 ) || (RFAL_FEATURE_ISO_DEP_IBLOCK_MAX_LEN < 16) ) + #error " RFAL: Invalid ISO-DEP IBlock Max length. Please change RFAL_FEATURE_ISO_DEP_IBLOCK_MAX_LEN. " +#endif + +/* Check for valid APDU length, It must be n*IBlock */ +#if( (RFAL_FEATURE_ISO_DEP_APDU_MAX_LEN < RFAL_FEATURE_ISO_DEP_IBLOCK_MAX_LEN) || (RFAL_FEATURE_ISO_DEP_APDU_MAX_LEN % RFAL_FEATURE_ISO_DEP_IBLOCK_MAX_LEN) ) + #error " RFAL: Invalid ISO-DEP APDU Max length. Please change RFAL_FEATURE_ISO_DEP_APDU_MAX_LEN. " +#endif + +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ +#define ISODEP_CRC_LEN RFAL_CRC_LEN /*!< ISO1443 CRC Length */ + + +#define ISODEP_PCB_POS (0U) /*!< PCB position on message header*/ +#define ISODEP_SWTX_INF_POS (1U) /*!< INF position in a S-WTX */ + +#define ISODEP_DID_POS (1U) /*!< DID position on message header*/ +#define ISODEP_SWTX_PARAM_LEN (1U) /*!< SWTX parameter length */ + +#define ISODEP_DSL_MAX_LEN ( RFAL_ISODEP_PCB_LEN + RFAL_ISODEP_DID_LEN ) /*!< Deselect Req/Res length */ + +#define ISODEP_PCB_xBLOCK_MASK (0xC0U) /*!< Bit mask for Block type */ +#define ISODEP_PCB_IBLOCK (0x00U) /*!< Bit mask indicating a I-Block */ +#define ISODEP_PCB_RBLOCK (0x80U) /*!< Bit mask indicating a R-Block */ +#define ISODEP_PCB_SBLOCK (0xC0U) /*!< Bit mask indicating a S-Block */ +#define ISODEP_PCB_INVALID (0x40U) /*!< Bit mask of an Invalid PCB */ + +#define ISODEP_HDR_MAX_LEN (RFAL_ISODEP_PCB_LEN + RFAL_ISODEP_DID_LEN + RFAL_ISODEP_NAD_LEN) /*!< Max header length (PCB + DID + NAD) */ + +#define ISODEP_PCB_IB_VALID_MASK (ISODEP_PCB_B6_BIT | ISODEP_PCB_B2_BIT) /*!< Bit mask for the MUST bits on I-Block */ +#define ISODEP_PCB_IB_VALID_VAL (ISODEP_PCB_B2_BIT) /*!< Value for the MUST bits on I-Block */ +#define ISODEP_PCB_RB_VALID_MASK (ISODEP_PCB_B6_BIT | ISODEP_PCB_B3_BIT | ISODEP_PCB_B2_BIT) /*!< Bit mask for the MUST bits on R-Block */ +#define ISODEP_PCB_RB_VALID_VAL (ISODEP_PCB_B6_BIT | ISODEP_PCB_B2_BIT) /*!< Value for the MUST bits on R-Block */ +#define ISODEP_PCB_SB_VALID_MASK (ISODEP_PCB_B3_BIT | ISODEP_PCB_B2_BIT | ISODEP_PCB_B1_BIT) /*!< Bit mask for the MUST bits on I-Block */ +#define ISODEP_PCB_SB_VALID_VAL (ISODEP_PCB_B2_BIT) /*!< Value for the MUST bits on I-Block */ + + +#define ISODEP_PCB_B1_BIT (0x01U) /*!< Bit mask for the RFU S Blocks */ +#define ISODEP_PCB_B2_BIT (0x02U) /*!< Bit mask for the RFU bit2 in I,S,R Blocks */ +#define ISODEP_PCB_B3_BIT (0x04U) /*!< Bit mask for the RFU bit3 in R Blocks */ +#define ISODEP_PCB_B6_BIT (0x20U) /*!< Bit mask for the RFU bit2 in R Blocks */ +#define ISODEP_PCB_CHAINING_BIT (0x10U) /*!< Bit mask for the chaining bit of an ISO DEP I-Block in PCB. */ +#define ISODEP_PCB_DID_BIT (0x08U) /*!< Bit mask for the DID presence bit of an ISO DEP I,S,R Blocks PCB. */ +#define ISODEP_PCB_NAD_BIT (0x04U) /*!< Bit mask for the NAD presence bit of an ISO DEP I,S,R Blocks in PCB */ +#define ISODEP_PCB_BN_MASK (0x01U) /*!< Bit mask for the block number of an ISO DEP I,R Block in PCB */ + +#define ISODEP_SWTX_PL_MASK (0xC0U) /*!< Bit mask for the Power Level bits of the inf byte of an WTX request or response */ +#define ISODEP_SWTX_WTXM_MASK (0x3FU) /*!< Bit mask for the WTXM bits of the inf byte of an WTX request or response */ + + +#define ISODEP_RBLOCK_INF_LEN (0U) /*!< INF length of R-Block Digital 1.1 15.1.3 */ +#define ISODEP_SDSL_INF_LEN (0U) /*!< INF length of S(DSL) Digital 1.1 15.1.3 */ +#define ISODEP_SWTX_INF_LEN (1U) /*!< INF length of S(WTX) Digital 1.1 15.2.2 */ + +#define ISODEP_WTXM_MIN (1U) /*!< Minimum allowed value for the WTXM, Digital 1.0 13.2.2 */ +#define ISODEP_WTXM_MAX (59U) /*!< Maximum allowed value for the WTXM, Digital 1.0 13.2.2 */ + +#define ISODEP_PCB_Sxx_MASK (0x30U) /*!< Bit mask for the S-Block type */ +#define ISODEP_PCB_DESELECT (0x00U) /*!< Bit mask for S-Block indicating Deselect */ +#define ISODEP_PCB_WTX (0x30U) /*!< Bit mask for S-Block indicating Waiting Time eXtension */ + +#define ISODEP_PCB_Rx_MASK (0x10U) /*!< Bit mask for the R-Block type */ +#define ISODEP_PCB_ACK (0x00U) /*!< Bit mask for R-Block indicating ACK */ +#define ISODEP_PCB_NAK (0x10U) /*!< Bit mask for R-Block indicating NAK */ + +/*! Maximum length of control message (no INF) */ +#define ISODEP_CONTROLMSG_BUF_LEN (RFAL_ISODEP_PCB_LEN + RFAL_ISODEP_DID_LEN + RFAL_ISODEP_NAD_LEN + ISODEP_SWTX_PARAM_LEN) + +#define ISODEP_FWT_DEACTIVATION (71680U) /*!< FWT to be used after DESELECT, Digital 1.0 A9 */ +#define ISODEP_MAX_RERUNS (0x0FFFFFFFU)/*!< Maximum rerun retrys for a blocking protocol run*/ + + +#define ISODEP_PCBSBLOCK ( 0x00U | ISODEP_PCB_SBLOCK | ISODEP_PCB_B2_BIT ) /*!< PCB Value of a S-Block */ +#define ISODEP_PCB_SDSL ( ISODEP_PCBSBLOCK | ISODEP_PCB_DESELECT ) /*!< PCB Value of a S-Block with DESELECT */ +#define ISODEP_PCB_SWTX ( ISODEP_PCBSBLOCK | ISODEP_PCB_WTX ) /*!< PCB Value of a S-Block with WTX */ +#define ISODEP_PCB_SPARAMETERS ( ISODEP_PCB_SBLOCK | ISODEP_PCB_WTX ) /*!< PCB Value of a S-Block with PARAMETERS */ + +#define ISODEP_FWI_LIS_MAX_NFC 8U /*!< FWT Listener Max FWIT4ATmax FWIBmax Digital 1.1 A6 & A3 */ +#define ISODEP_FWI_LIS_MAX_EMVCO 7U /*!< FWT Listener Max FWIMAX EMVCo 2.6 A.5 */ +#define ISODEP_FWI_LIS_MAX (uint8_t)((gIsoDep.compMode == RFAL_COMPLIANCE_MODE_EMV) ? ISODEP_FWI_LIS_MAX_EMVCO : ISODEP_FWI_LIS_MAX_NFC) /*!< FWI Listener Max as NFC / EMVCo */ +#define ISODEP_FWT_LIS_MAX rfalIsoDepFWI2FWT(ISODEP_FWI_LIS_MAX) /*!< FWT Listener Max */ + +#define ISODEP_FWI_MIN_10 (1U) /*!< Minimum value for FWI Digital 1.0 11.6.2.17 */ +#define ISODEP_FWI_MIN_11 (0U) /*!< Default value for FWI Digital 1.1 13.6.2 */ +#define ISODEP_FWI_MAX (14U) /*!< Maximum value for FWI Digital 1.0 11.6.2.17 */ +#define ISODEP_SFGI_MIN (0U) /*!< Default value for FWI Digital 1.1 13.6.2.22 */ +#define ISODEP_SFGI_MAX (14U) /*!< Maximum value for FWI Digital 1.1 13.6.2.22 */ + + +#define RFAL_ISODEP_SPARAM_TVL_HDR_LEN (2U) /*!< S(PARAMETERS) TVL header length: Tag + Len */ +#define RFAL_ISODEP_SPARAM_HDR_LEN (RFAL_ISODEP_PCB_LEN + RFAL_ISODEP_SPARAM_TVL_HDR_LEN) /*!< S(PARAMETERS) header length: PCB + Tag + Len */ + + +/**********************************************************************************************************************/ +/**********************************************************************************************************************/ +#define RFAL_ISODEP_NO_PARAM (0U) /*!< No parameter flag for isoDepHandleControlMsg() */ + +#define RFAL_ISODEP_CMD_RATS (0xE0U) /*!< RATS command Digital 1.1 13.6.1 */ + +#define RFAL_ISODEP_ATS_MIN_LEN (1U) /*!< Minimum ATS length Digital 1.1 13.6.2 */ +#define RFAL_ISODEP_ATS_HDR_LEN (5U) /*!< ATS headerlength Digital 1.1 13.6.2 */ +#define RFAL_ISODEP_ATS_MAX_LEN (RFAL_ISODEP_ATS_HDR_LEN + RFAL_ISODEP_ATS_HB_MAX_LEN) /*!< Maximum ATS length Digital 1.1 13.6.2 */ +#define RFAL_ISODEP_ATS_T0_FSCI_MASK (0x0FU) /*!< ATS T0's FSCI mask Digital 1.1 13.6.2 */ +#define RFAL_ISODEP_ATS_TB_FWI_SHIFT (4U) /*!< ATS TB's FWI shift Digital 1.1 13.6.2 */ +#define RFAL_ISODEP_ATS_FWI_MASK (0x0FU) /*!< ATS TB's FWI shift Digital 1.1 13.6.2 */ + + +#define RFAL_ISODEP_PPS_SB (0xD0U) /*!< PPS REQ PPSS's SB value (no CID) ISO14443-4 5.3 */ +#define RFAL_ISODEP_PPS_MASK (0xF0U) /*!< PPS REQ PPSS's SB mask ISO14443-4 5.3 */ +#define RFAL_ISODEP_PPS_SB_DID_MASK (0x0FU) /*!< PPS REQ PPSS's DID|CID mask ISO14443-4 5.3 */ +#define RFAL_ISODEP_PPS_PPS0_PPS1_PRESENT (0x11U) /*!< PPS REQ PPS0 indicating that PPS1 is present */ +#define RFAL_ISODEP_PPS_PPS1 (0x00U) /*!< PPS REQ PPS1 fixed value ISO14443-4 5.3 */ +#define RFAL_ISODEP_PPS_PPS1_DSI_SHIFT (2U) /*!< PPS REQ PPS1 fixed value ISO14443-4 5.3 */ +#define RFAL_ISODEP_PPS_PPS1_DXI_MASK (0x0FU) /*!< PPS REQ PPS1 fixed value ISO14443-4 5.3 */ +#define RFAL_ISODEP_PPS_RES_LEN (1U) /*!< PPS Response length ISO14443-4 5.4 */ +#define RFAL_ISODEP_PPS_STARTBYTE_POS (0U) /*!< PPS REQ PPSS's byte position ISO14443-4 5.4 */ +#define RFAL_ISODEP_PPS_PPS0_POS (1U) /*!< PPS REQ PPS0's byte position ISO14443-4 5.4 */ +#define RFAL_ISODEP_PPS_PPS1_POS (2U) /*!< PPS REQ PPS1's byte position ISO14443-4 5.4 */ +#define RFAL_ISODEP_PPS0_VALID_MASK (0xEFU) /*!< PPS REQ PPS0 valid coding mask ISO14443-4 5.4 */ + +#define RFAL_ISODEP_CMD_ATTRIB (0x1DU) /*!< ATTRIB command Digital 1.1 14.6.1 */ +#define RFAL_ISODEP_ATTRIB_PARAM2_DSI_SHIFT (6U) /*!< ATTRIB PARAM2 DSI shift Digital 1.1 14.6.1 */ +#define RFAL_ISODEP_ATTRIB_PARAM2_DRI_SHIFT (4U) /*!< ATTRIB PARAM2 DRI shift Digital 1.1 14.6.1 */ +#define RFAL_ISODEP_ATTRIB_PARAM2_DXI_MASK (0xF0U) /*!< ATTRIB PARAM2 DxI mask Digital 1.1 14.6.1 */ +#define RFAL_ISODEP_ATTRIB_PARAM2_FSDI_MASK (0x0FU) /*!< ATTRIB PARAM2 FSDI mask Digital 1.1 14.6.1 */ +#define RFAL_ISODEP_ATTRIB_PARAM4_DID_MASK (0x0FU) /*!< ATTRIB PARAM4 DID mask Digital 1.1 14.6.1 */ +#define RFAL_ISODEP_ATTRIB_HDR_LEN (9U) /*!< ATTRIB REQ header length Digital 1.1 14.6.1 */ + +#define RFAL_ISODEP_ATTRIB_RES_HDR_LEN (1U) /*!< ATTRIB RES header length Digital 1.1 14.6.2 */ +#define RFAL_ISODEP_ATTRIB_RES_DID_MASK (0x0FU) /*!< ATTRIB RES DID mask Digital 1.1 14.6.2 */ +#define RFAL_ISODEP_ATTRIB_RES_MBLI_MASK (0x0FU) /*!< ATTRIB RES MBLI mask Digital 1.1 14.6.2 */ +#define RFAL_ISODEP_ATTRIB_RES_MBLI_SHIFT (4U) /*!< ATTRIB RES MBLI shift Digital 1.1 14.6.2 */ + +#define RFAL_ISODEP_DID_MASK (0x0FU) /*!< ISODEP's DID mask */ +#define RFAL_ISODEP_DID_00 (0U) /*!< ISODEP's DID value 0 */ + +#define RFAL_ISODEP_FSDI_MAX_NFC (8U) /*!< Max FSDI value Digital 2.0 14.6.1.9 & B7 & B8 */ +#define RFAL_ISODEP_FSDI_MAX_EMV (0x0CU) /*!< Max FSDI value EMVCo 3.0 5.7.2.5 */ + +#define RFAL_ISODEP_RATS_PARAM_FSDI_MASK (0xF0U) /*!< Mask bits for FSDI in RATS */ +#define RFAL_ISODEP_RATS_PARAM_FSDI_SHIFT (4U) /*!< Shift for FSDI in RATS */ +#define RFAL_ISODEP_RATS_PARAM_DID_MASK (0x0FU) /*!< Mask bits for DID in RATS */ + +#define RFAL_ISODEP_ATS_TL_OFFSET (0x00U) /*!< Offset of TL on ATS */ +#define RFAL_ISODEP_ATS_TA_OFFSET (0x02U) /*!< Offset of TA if it is present on ATS */ +#define RFAL_ISODEP_ATS_TB_OFFSET (0x03U) /*!< Offset of TB if both TA and TB is present on ATS */ +#define RFAL_ISODEP_ATS_TC_OFFSET (0x04U) /*!< Offset of TC if both TA,TB & TC are present on ATS */ +#define RFAL_ISODEP_ATS_HIST_OFFSET (0x05U) /*!< Offset of Historical Bytes if TA, TB & TC are present on ATS */ +#define RFAL_ISODEP_ATS_TC_ADV_FEAT (0x10U) /*!< Bit mask indicating support for Advanced protocol features: DID & NAD */ +#define RFAL_ISODEP_ATS_TC_DID (0x02U) /*!< Bit mask indicating support for DID */ +#define RFAL_ISODEP_ATS_TC_NAD (0x01U) /*!< Bit mask indicating support for NAD */ + +#define RFAL_ISODEP_PPS0_PPS1_PRESENT (0x11U) /*!< PPS0 byte indicating that PPS1 is present */ +#define RFAL_ISODEP_PPS0_PPS1_NOT_PRESENT (0x01U) /*!< PPS0 byte indicating that PPS1 is NOT present */ +#define RFAL_ISODEP_PPS1_DRI_MASK (0x03U) /*!< PPS1 byte DRI mask bits */ +#define RFAL_ISODEP_PPS1_DSI_MASK (0x0CU) /*!< PPS1 byte DSI mask bits */ +#define RFAL_ISODEP_PPS1_DSI_SHIFT (2U) /*!< PPS1 byte DSI shift */ +#define RFAL_ISODEP_PPS1_DxI_MASK (0x03U) /*!< PPS1 byte DSI/DRS mask bits */ + + +/*! Delta Time for polling during Activation (ATS) : 20ms Digital 1.0 11.7.1.1 & A.7 */ +#define RFAL_ISODEP_T4T_DTIME_POLL_10 rfalConvMsTo1fc(20) + +/*! Delta Time for polling during Activation (ATS) : 16.4ms Digital 1.1 13.8.1.1 & A.6 + * Use 16 ms as testcase T4AT_BI_10_03 sends a frame exactly at the border */ +#define RFAL_ISODEP_T4T_DTIME_POLL_11 216960U + +/*! Activation frame waiting time FWT(act) = 71680/fc (~5286us) Digital 1.1 13.8.1.1 & A.6 */ +#define RFAL_ISODEP_T4T_FWT_ACTIVATION (71680U + RFAL_ISODEP_T4T_DTIME_POLL_11) + + +/*! Delta frame waiting time = 16/fc Digital 1.0 11.7.1.3 & A.7*/ +#define RFAL_ISODEP_DFWT_10 16U + +/*! Delta frame waiting time = 16/fc Digital 2.0 14.8.1.3 & B.7*/ +#define RFAL_ISODEP_DFWT_20 49152U + +/* + ****************************************************************************** + * MACROS + ****************************************************************************** + */ + +#define isoDep_PCBisIBlock( pcb ) ( ((pcb) & (ISODEP_PCB_xBLOCK_MASK | ISODEP_PCB_IB_VALID_MASK)) == (ISODEP_PCB_IBLOCK | ISODEP_PCB_IB_VALID_VAL)) /*!< Checks if pcb is a I-Block */ +#define isoDep_PCBisRBlock( pcb ) ( ((pcb) & (ISODEP_PCB_xBLOCK_MASK | ISODEP_PCB_RB_VALID_MASK)) == (ISODEP_PCB_RBLOCK | ISODEP_PCB_RB_VALID_VAL)) /*!< Checks if pcb is a R-Block */ +#define isoDep_PCBisSBlock( pcb ) ( ((pcb) & (ISODEP_PCB_xBLOCK_MASK | ISODEP_PCB_SB_VALID_MASK)) == (ISODEP_PCB_SBLOCK | ISODEP_PCB_SB_VALID_VAL)) /*!< Checks if pcb is a S-Block */ + +#define isoDep_PCBisChaining( pcb ) ( ((pcb) & ISODEP_PCB_CHAINING_BIT) == ISODEP_PCB_CHAINING_BIT) /*!< Checks if pcb is indicating chaining */ + +#define isoDep_PCBisDeselect( pcb ) ( ((pcb) & ISODEP_PCB_Sxx_MASK) == ISODEP_PCB_DESELECT) /*!< Checks if pcb is indicating DESELECT */ +#define isoDep_PCBisWTX( pcb ) ( ((pcb) & ISODEP_PCB_Sxx_MASK) == ISODEP_PCB_WTX) /*!< Checks if pcb is indicating WTX */ + +#define isoDep_PCBisACK( pcb ) ( ((pcb) & ISODEP_PCB_Rx_MASK) == ISODEP_PCB_ACK) /*!< Checks if pcb is indicating ACK */ +#define isoDep_PCBisNAK( pcb ) ( ((pcb) & ISODEP_PCB_Rx_MASK) == ISODEP_PCB_NAK) /*!< Checks if pcb is indicating ACK */ + +#define isoDep_PCBhasDID( pcb ) ( ((pcb) & ISODEP_PCB_DID_BIT) == ISODEP_PCB_DID_BIT) /*!< Checks if pcb is indicating DID */ +#define isoDep_PCBhasNAD( pcb ) ( ((pcb) & ISODEP_PCB_NAD_BIT) == ISODEP_PCB_NAD_BIT) /*!< Checks if pcb is indicating NAD */ + + +#define isoDep_PCBisIChaining( pcb ) ( isoDep_PCBisIBlock(pcb) && isoDep_PCBisChaining(pcb) ) /*!< Checks if pcb is I-Block indicating chaining*/ + +#define isoDep_PCBisSDeselect( pcb ) ( isoDep_PCBisSBlock(pcb) && isoDep_PCBisDeselect(pcb) ) /*!< Checks if pcb is S-Block indicating DESELECT*/ +#define isoDep_PCBisSWTX( pcb ) ( isoDep_PCBisSBlock(pcb) && isoDep_PCBisWTX(pcb) ) /*!< Checks if pcb is S-Block indicating WTX */ + +#define isoDep_PCBisRACK( pcb ) ( isoDep_PCBisRBlock(pcb) && isoDep_PCBisACK(pcb) ) /*!< Checks if pcb is R-Block indicating ACK */ +#define isoDep_PCBisRNAK( pcb ) ( isoDep_PCBisRBlock(pcb) && isoDep_PCBisNAK(pcb) ) /*!< Checks if pcb is R-Block indicating NAK */ + + +#define isoDep_PCBIBlock( bn ) ( (uint8_t)( 0x00U | ISODEP_PCB_IBLOCK | ISODEP_PCB_B2_BIT | ((bn) & ISODEP_PCB_BN_MASK) )) /*!< Returns an I-Block with the given block number (bn) */ +#define isoDep_PCBIBlockChaining( bn ) ( (uint8_t)(isoDep_PCBIBlock(bn) | ISODEP_PCB_CHAINING_BIT)) /*!< Returns an I-Block with the given block number (bn) indicating chaining */ + +#define isoDep_PCBRBlock( bn ) ( (uint8_t)( 0x00U | ISODEP_PCB_RBLOCK | ISODEP_PCB_B6_BIT | ISODEP_PCB_B2_BIT | ((bn) & ISODEP_PCB_BN_MASK) ) ) /*!< Returns an R-Block with the given block number (bn) */ +#define isoDep_PCBRACK( bn ) ( (uint8_t)( isoDep_PCBRBlock( bn ) | ISODEP_PCB_ACK ) ) /*!< Returns an R-Block with the given block number (bn) indicating ACK */ +#define isoDep_PCBRNAK( bn ) ( (uint8_t)( isoDep_PCBRBlock( bn ) | ISODEP_PCB_NAK ) ) /*!< Returns an R-Block with the given block number (bn) indicating NAK */ + + +#define isoDep_GetBN( pcb ) ( (uint8_t) ((pcb) & ISODEP_PCB_BN_MASK ) ) /*!< Returns the block number (bn) from the given pcb */ +#define isoDep_GetWTXM( inf ) ( (uint8_t) ((inf) & ISODEP_SWTX_WTXM_MASK) ) /*!< Returns the WTX value from the given inf byte */ +#define isoDep_isWTXMValid( wtxm ) (((wtxm) >= ISODEP_WTXM_MIN) && ((wtxm) <= ISODEP_WTXM_MAX)) /*!< Checks if the given wtxm is valid */ + +#define isoDep_WTXMListenerMax( fwt ) ( MIN( (uint8_t)(ISODEP_FWT_LIS_MAX / (fwt)), ISODEP_WTXM_MAX) ) /*!< Calculates the Max WTXM value for the given fwt as a Listener */ + +#define isoDepCalcdSGFT( s ) (384U * ((uint32_t)1U << (s))) /*!< Calculates the dSFGT with given SFGI Digital 1.1 13.8.2.1 & A.6*/ +#define isoDepCalcSGFT( s ) (4096U * ((uint32_t)1U << (s))) /*!< Calculates the SFGT with given SFGI Digital 1.1 13.8.2 */ + +#define isoDep_PCBNextBN( bn ) (((uint8_t)(bn)^0x01U) & ISODEP_PCB_BN_MASK) /*!< Returns the value of the next block number based on bn */ +#define isoDep_PCBPrevBN( bn ) isoDep_PCBNextBN(bn) /*!< Returns the value of the previous block number based on bn */ +#define isoDep_ToggleBN( bn ) ((bn) = (((bn)^0x01U) & ISODEP_PCB_BN_MASK) ) /*!< Toggles the block number value of the given bn */ + +#define isoDep_WTXAdjust( v ) ((v) - ((v)>>3)) /*!< Adjust WTX timer value to a percentage of the total, current 88% */ + + +/*! ISO 14443-4 7.5.6.2 & Digital 1.1 - 15.2.6.2 The CE SHALL NOT attempt error recovery and remains in Rx mode upon Transmission or a Protocol Error */ +#define isoDepReEnableRx( rxB, rxBL, rxL ) rfalTransceiveBlockingTx( NULL, 0, rxB, rxBL, rxL, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FWT_NONE ) + +#define isoDepTimerStart( timer, time_ms ) (timer) = platformTimerCreate((uint16_t)(time_ms)) /*!< Configures and starts the WTX timer */ +#define isoDepTimerisExpired( timer ) platformTimerIsExpired( timer ) /*!< Checks WTX timer has expired */ + +/* + ****************************************************************************** + * LOCAL DATA TYPES + ****************************************************************************** + */ + + /*! Internal structure to be used in handling of S(PARAMETRS) only */ +typedef struct +{ + uint8_t pcb; /*!< PCB byte */ + rfalIsoDepSParameter sParam; /*!< S(PARAMETERS) */ +} rfalIsoDepControlMsgSParam; + +/*! Enumeration of the possible control message types */ +typedef enum +{ + ISODEP_R_ACK, /*!< R-ACK Acknowledge */ + ISODEP_R_NAK, /*!< R-NACK Negative acknowledge */ + ISODEP_S_WTX, /*!< S-WTX Waiting Time Extension */ + ISODEP_S_DSL /*!< S-DSL Deselect */ +} rfalIsoDepControlMsg; + +/*! Enumeration of the IsoDep roles */ +typedef enum +{ + ISODEP_ROLE_PCD, /*!< Perform as Reader/PCD */ + ISODEP_ROLE_PICC /*!< Perform as Card/PICC */ +} rfalIsoDepRole; + +/*! ISO-DEP layer states */ +typedef enum +{ + ISODEP_ST_IDLE, /*!< Idle State */ + ISODEP_ST_PCD_TX, /*!< PCD Transmission State */ + ISODEP_ST_PCD_RX, /*!< PCD Reception State */ + ISODEP_ST_PCD_WAIT_DSL, /*!< PCD Wait for DSL response */ + + ISODEP_ST_PICC_ACT_ATS, /*!< PICC has replied to RATS (ATS) */ + ISODEP_ST_PICC_ACT_ATTRIB, /*!< PICC has replied to ATTRIB */ + ISODEP_ST_PICC_RX, /*!< PICC REception State */ + ISODEP_ST_PICC_SWTX, /*!< PICC Waiting Time eXtension */ + ISODEP_ST_PICC_TX, /*!< PICC Transmission State */ +} rfalIsoDepState; + + + + +/*! Holds all ISO-DEP data(counters, buffers, ID, timeouts, frame size) */ +typedef struct{ + rfalIsoDepState state; /*!< ISO-DEP module state */ + rfalIsoDepRole role; /*!< Current ISO-DEP role */ + + uint8_t blockNumber; /*!< Current block number */ + uint8_t did; /*!< Current DID */ + uint8_t nad; /*!< Current DID */ + uint8_t cntIRetrys; /*!< I-Block retry counter */ + uint8_t cntRRetrys; /*!< R-Block retry counter */ + uint8_t cntSRetrys; /*!< S-Block retry counter */ + uint32_t fwt; /*!< Current FWT (Frame Waiting Time) */ + uint32_t dFwt; /*!< Current delta FWT */ + uint16_t fsx; /*!< Current FSx FSC or FSD (max Frame size) */ + bool isTxChaining; /*!< Flag for chaining on Tx */ + bool isRxChaining; /*!< Flag for chaining on Rx */ + uint8_t* txBuf; /*!< Tx buffer pointer */ + uint8_t* rxBuf; /*!< Rx buffer pointer */ + uint16_t txBufLen; /*!< Tx buffer length */ + uint16_t rxBufLen; /*!< Rx buffer length */ + uint8_t txBufInfPos; /*!< Start of payload in txBuf */ + uint8_t rxBufInfPos; /*!< Start of payload in rxBuf */ + + + uint16_t ourFsx; /*!< Our current FSx FSC or FSD (Frame size) */ + uint8_t lastPCB; /*!< Last PCB sent */ + uint8_t lastWTXM; /*!< Last WTXM sent */ + uint8_t atsTA; /*!< TA on ATS */ + uint8_t hdrLen; /*!< Current ISO-DEP length */ + rfalBitRate txBR; /*!< Current Tx Bit Rate */ + rfalBitRate rxBR; /*!< Current Rx Bit Rate */ + uint16_t *rxLen; /*!< Output parameter ptr to Rx length */ + bool *rxChaining; /*!< Output parameter ptr to Rx chaining flag */ + uint32_t WTXTimer; /*!< Timer used for WTX */ + bool lastDID00; /*!< Last PCD block had DID flag (for DID = 0) */ + + bool isTxPending; /*!< Flag pending Block while waiting WTX Ack */ + bool isWait4WTX; /*!< Flag for waiting WTX Ack */ + + uint32_t SFGTTimer; /*!< Timer used for SFGT */ + + uint8_t maxRetriesI; /*!< Number of retries for a I-Block */ + uint8_t maxRetriesS; /*!< Number of retries for a S-Block */ + uint8_t maxRetriesR; /*!< Number of retries for a R-Block */ + uint8_t maxRetriesRATS;/*!< Number of retries for RATS */ + + rfalComplianceMode compMode; /*!< Compliance mode */ + + uint8_t ctrlRxBuf[ISODEP_CONTROLMSG_BUF_LEN]; /*!< Control msg buf */ + uint16_t ctrlRxLen; /*!< Control msg rcvd len (used only for DSL) */ + + + rfalIsoDepListenActvParam actvParam; /*!< Listen Activation context */ + + rfalIsoDepApduTxRxParam APDUParam; /*!< APDU TxRx params */ + uint16_t APDUTxPos; /*!< APDU Tx position */ + uint16_t APDURxPos; /*!< APDU Rx position */ + bool isAPDURxChaining; /*!< APDU Transceive chaining flag */ + +}rfalIsoDep; + + + +/* + ****************************************************************************** + * LOCAL VARIABLES + ****************************************************************************** + */ + +static rfalIsoDep gIsoDep; /*!< ISO-DEP Module instance */ + +/* + ****************************************************************************** + * LOCAL FUNCTION PROTOTYPES + ****************************************************************************** + */ +static void isoDepClearCounters( void ); +static ReturnCode isoDepTx( uint8_t pcb, const uint8_t* txBuf, uint8_t *infBuf, uint16_t infLen, uint32_t fwt ); +static ReturnCode isoDepHandleControlMsg( rfalIsoDepControlMsg controlMsg, uint8_t param ); +static void rfalIsoDepApdu2IBLockParam( rfalIsoDepApduTxRxParam apduParam, rfalIsoDepTxRxParam *iBlockParam, uint16_t txPos, uint16_t rxPos ); + +#if RFAL_FEATURE_ISO_DEP_POLL + static ReturnCode isoDepDataExchangePCD( uint16_t *outActRxLen, bool *outIsChaining ); + static void rfalIsoDepCalcBitRate(rfalBitRate maxAllowedBR, uint8_t piccBRCapability, rfalBitRate *dsi, rfalBitRate *dri); + static uint32_t rfalIsoDepSFGI2SFGT( uint8_t sfgi ); +#endif +#if RFAL_FEATURE_ISO_DEP_LISTEN + static ReturnCode isoDepDataExchangePICC( void ); + static ReturnCode isoDepReSendControlMsg( void ); +#endif + + + + +/* + ****************************************************************************** + * LOCAL FUNCTIONS + ****************************************************************************** + */ + +/*******************************************************************************/ +static void isoDepClearCounters( void ) +{ + gIsoDep.cntIRetrys = 0; + gIsoDep.cntRRetrys = 0; + gIsoDep.cntSRetrys = 0; +} + +/*******************************************************************************/ +static ReturnCode isoDepTx( uint8_t pcb, const uint8_t* txBuf, uint8_t *infBuf, uint16_t infLen, uint32_t fwt ) +{ + uint8_t *txBlock; + uint16_t txBufLen; + uint8_t computedPcb; + + + txBlock = infBuf; /* Point to beginning of the INF, and go backwards */ + gIsoDep.lastPCB = pcb; /* Store the last PCB sent */ + + + if ( infLen > 0U ) + { + if ( ((uint32_t)infBuf - (uint32_t)txBuf) < gIsoDep.hdrLen ) /* Check that we can fit the header in the given space */ + { + return ERR_NOMEM; + } + } + + + /*******************************************************************************/ + /* Compute optional PCB bits */ + computedPcb = pcb; + if ((gIsoDep.did != RFAL_ISODEP_NO_DID) || ((gIsoDep.did == RFAL_ISODEP_DID_00) && gIsoDep.lastDID00) ) { computedPcb |= ISODEP_PCB_DID_BIT; } + if (gIsoDep.nad != RFAL_ISODEP_NO_NAD) { computedPcb |= ISODEP_PCB_NAD_BIT; } + if ((gIsoDep.isTxChaining) && (isoDep_PCBisIBlock(computedPcb)) ) { computedPcb |= ISODEP_PCB_CHAINING_BIT; } + + + /*******************************************************************************/ + /* Compute Payload on the given txBuf, start by the PCB | DID | NAD | before INF */ + + if (gIsoDep.nad != RFAL_ISODEP_NO_NAD) + { + *(--txBlock) = gIsoDep.nad; /* NAD is optional */ + } + + if ( (gIsoDep.did != RFAL_ISODEP_NO_DID) || ((gIsoDep.did == RFAL_ISODEP_DID_00) && gIsoDep.lastDID00) ) + { + *(--txBlock) = gIsoDep.did; /* DID is optional */ + } + + *(--txBlock) = computedPcb; /* PCB always present */ + + txBufLen = (infLen + (uint16_t)((uint32_t)infBuf - (uint32_t)txBlock)); /* Calculate overall buffer size */ + + if ( txBufLen > (gIsoDep.fsx - ISODEP_CRC_LEN) ) /* Check if msg length violates the maximum frame size FSC */ + { + return ERR_NOTSUPP; + } + + return rfalTransceiveBlockingTx( txBlock, txBufLen, gIsoDep.rxBuf, gIsoDep.rxBufLen, gIsoDep.rxLen, RFAL_TXRX_FLAGS_DEFAULT, ((gIsoDep.role == ISODEP_ROLE_PICC) ? RFAL_FWT_NONE : fwt ) ); +} + +/*******************************************************************************/ +static ReturnCode isoDepHandleControlMsg( rfalIsoDepControlMsg controlMsg, uint8_t param ) +{ + uint8_t pcb; + uint8_t ctrlMsgBuf[ISODEP_CONTROLMSG_BUF_LEN]; + uint8_t infLen; + uint32_t fwtTemp; + + infLen = 0; + fwtTemp = (gIsoDep.fwt + gIsoDep.dFwt); + ST_MEMSET( ctrlMsgBuf, 0x00, ISODEP_CONTROLMSG_BUF_LEN ); + + switch( controlMsg ) + { + /*******************************************************************************/ + case ISODEP_R_ACK: + + if( gIsoDep.cntRRetrys++ > gIsoDep.maxRetriesR ) + { + return ERR_PROTO; + } + + pcb = isoDep_PCBRACK( gIsoDep.blockNumber ); + break; + + /*******************************************************************************/ + case ISODEP_R_NAK: + if( gIsoDep.cntRRetrys++ > gIsoDep.maxRetriesR ) + { + return ERR_TIMEOUT; + } + + pcb = isoDep_PCBRNAK( gIsoDep.blockNumber ); + break; + + /*******************************************************************************/ + case ISODEP_S_WTX: + if( gIsoDep.cntSRetrys++ > gIsoDep.maxRetriesS ) + { + return ERR_PROTO; + } + + /* Check if WTXM is valid */ + if( ! isoDep_isWTXMValid(param) ) + { + return ERR_PROTO; + } + + if( gIsoDep.role == ISODEP_ROLE_PCD ) + { + /* Calculate temp Wait Time eXtension */ + fwtTemp = (gIsoDep.fwt * param); + fwtTemp = MIN( RFAL_ISODEP_MAX_FWT, fwtTemp ); + fwtTemp += gIsoDep.dFwt; + } + + pcb = ISODEP_PCB_SWTX; + ctrlMsgBuf[ RFAL_ISODEP_PCB_LEN + RFAL_ISODEP_DID_LEN + infLen++] = param; + break; + + /*******************************************************************************/ + case ISODEP_S_DSL: + if( gIsoDep.cntSRetrys++ > gIsoDep.maxRetriesS ) + { + return ERR_PROTO; + } + + if( gIsoDep.role == ISODEP_ROLE_PCD ) + { + /* Digital 1.0 - 13.2.7.3 Poller must wait fwtDEACTIVATION */ + fwtTemp = ISODEP_FWT_DEACTIVATION; + gIsoDep.state = ISODEP_ST_PCD_WAIT_DSL; + } + pcb = ISODEP_PCB_SDSL; + break; + + /*******************************************************************************/ + default: + return ERR_INTERNAL; + } + + return isoDepTx( pcb, ctrlMsgBuf, &ctrlMsgBuf[RFAL_ISODEP_PCB_LEN + RFAL_ISODEP_DID_LEN], infLen, fwtTemp ); +} + +#if RFAL_FEATURE_ISO_DEP_LISTEN +/*******************************************************************************/ +static ReturnCode isoDepReSendControlMsg( void ) +{ + if( isoDep_PCBisRACK( gIsoDep.lastPCB ) ) + { + return isoDepHandleControlMsg( ISODEP_R_ACK, RFAL_ISODEP_NO_PARAM ); + } + + if( isoDep_PCBisRNAK( gIsoDep.lastPCB ) ) + { + return isoDepHandleControlMsg( ISODEP_R_NAK, RFAL_ISODEP_NO_PARAM ); + } + + if( isoDep_PCBisSDeselect( gIsoDep.lastPCB ) ) + { + return isoDepHandleControlMsg( ISODEP_S_DSL, RFAL_ISODEP_NO_PARAM ); + } + + if( isoDep_PCBisSWTX( gIsoDep.lastPCB ) ) + { + return isoDepHandleControlMsg( ISODEP_S_WTX, gIsoDep.lastWTXM ); + } + return ERR_WRONG_STATE; +} +#endif /* RFAL_FEATURE_ISO_DEP_LISTEN */ + + +/* + ****************************************************************************** + * GLOBAL FUNCTIONS + ****************************************************************************** + */ + + +/*******************************************************************************/ +void rfalIsoDepInitialize( void ) +{ + gIsoDep.state = ISODEP_ST_IDLE; + gIsoDep.role = ISODEP_ROLE_PCD; + gIsoDep.did = RFAL_ISODEP_NO_DID; + gIsoDep.nad = RFAL_ISODEP_NO_NAD; + gIsoDep.blockNumber = 0; + gIsoDep.isTxChaining = false; + gIsoDep.isRxChaining = false; + gIsoDep.lastDID00 = false; + gIsoDep.lastPCB = ISODEP_PCB_INVALID; + gIsoDep.fsx = (uint16_t)RFAL_ISODEP_FSX_16; + gIsoDep.ourFsx = (uint16_t)RFAL_ISODEP_FSX_16; + gIsoDep.hdrLen = RFAL_ISODEP_PCB_LEN; + + gIsoDep.rxLen = NULL; + gIsoDep.rxBuf = NULL; + + gIsoDep.isTxPending = false; + gIsoDep.isWait4WTX = false; + + gIsoDep.compMode = RFAL_COMPLIANCE_MODE_NFC; + gIsoDep.maxRetriesR = RFAL_ISODEP_MAX_R_RETRYS; + gIsoDep.maxRetriesS = RFAL_ISODEP_MAX_S_RETRYS; + gIsoDep.maxRetriesI = RFAL_ISODEP_MAX_I_RETRYS; + gIsoDep.maxRetriesRATS = RFAL_ISODEP_RATS_RETRIES; + + isoDepClearCounters(); +} + + +/*******************************************************************************/ +void rfalIsoDepInitializeWithParams( rfalComplianceMode compMode, uint8_t maxRetriesR, uint8_t maxRetriesS, uint8_t maxRetriesI, uint8_t maxRetriesRATS ) +{ + rfalIsoDepInitialize(); + + gIsoDep.compMode = compMode; + gIsoDep.maxRetriesR = maxRetriesR; + gIsoDep.maxRetriesS = maxRetriesS; + gIsoDep.maxRetriesI = maxRetriesI; + gIsoDep.maxRetriesRATS = maxRetriesRATS; +} + + +#if RFAL_FEATURE_ISO_DEP_POLL +/*******************************************************************************/ +static ReturnCode isoDepDataExchangePCD( uint16_t *outActRxLen, bool *outIsChaining ) +{ + ReturnCode ret; + uint8_t rxPCB; + + /* Check out parameters */ + if( (outActRxLen == NULL) || (outIsChaining == NULL) ) + { + return ERR_PARAM; + } + + *outIsChaining = false; + + /* Calculate header required and check if the buffers InfPositions are suitable */ + gIsoDep.hdrLen = RFAL_ISODEP_PCB_LEN; + if (gIsoDep.did != RFAL_ISODEP_NO_DID) { gIsoDep.hdrLen += RFAL_ISODEP_DID_LEN; } + if (gIsoDep.nad != RFAL_ISODEP_NO_NAD) { gIsoDep.hdrLen += RFAL_ISODEP_NAD_LEN; } + + /* check if there is enough space before the infPos to append ISO-DEP headers on rx and tx */ + if( (gIsoDep.rxBufInfPos < gIsoDep.hdrLen) || (gIsoDep.txBufInfPos < gIsoDep.hdrLen) ) + { + return ERR_PARAM; + } + + /*******************************************************************************/ + /* Wait until SFGT has been fulfilled (as a PCD) */ + if(gIsoDep.SFGTTimer != 0U) + { + if( !isoDepTimerisExpired( gIsoDep.SFGTTimer ) ) + { + return ERR_BUSY; + } + } + /* Once done, clear SFGT timer */ + gIsoDep.SFGTTimer = 0; + + + /*******************************************************************************/ + switch( gIsoDep.state ) + { + /*******************************************************************************/ + case ISODEP_ST_IDLE: + return ERR_NONE; + + /*******************************************************************************/ + case ISODEP_ST_PCD_TX: + ret = isoDepTx( isoDep_PCBIBlock( gIsoDep.blockNumber ), gIsoDep.txBuf, &gIsoDep.txBuf[gIsoDep.txBufInfPos], gIsoDep.txBufLen, (gIsoDep.fwt + gIsoDep.dFwt) ); + switch( ret ) + { + case ERR_NONE: + gIsoDep.state = ISODEP_ST_PCD_RX; + break; + + default: + return ret; + } + /* fall through */ + + /*******************************************************************************/ + case ISODEP_ST_PCD_WAIT_DSL: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + case ISODEP_ST_PCD_RX: + + ret = rfalGetTransceiveStatus(); + switch( ret ) + { + /* Data rcvd with error or timeout -> Send R-NAK */ + case ERR_TIMEOUT: + case ERR_CRC: + case ERR_PAR: + case ERR_FRAMING: /* added to handle test cases scenario TC_POL_NFCB_T4AT_BI_82_x_y & TC_POL_NFCB_T4BT_BI_82_x_y */ + case ERR_INCOMPLETE_BYTE: /* added to handle test cases scenario TC_POL_NFCB_T4AT_BI_82_x_y & TC_POL_NFCB_T4BT_BI_82_x_y */ + + if( gIsoDep.isRxChaining ) + { /* Rule 5 - In PICC chaining when a invalid/timeout occurs -> R-ACK */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_R_ACK, RFAL_ISODEP_NO_PARAM ) ); + } + else if( gIsoDep.state == ISODEP_ST_PCD_WAIT_DSL ) + { /* Rule 8 - If s-Deselect response fails MAY retransmit */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_S_DSL, RFAL_ISODEP_NO_PARAM ) ); + } + else + { /* Rule 4 - When a invalid block or timeout occurs -> R-NACK */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_R_NAK, RFAL_ISODEP_NO_PARAM ) ); + } + return ERR_BUSY; + + case ERR_NONE: + break; + + case ERR_BUSY: + return ERR_BUSY; /* Debug purposes */ + + default: + return ret; + } + + /*******************************************************************************/ + /* No error, process incoming msg */ + /*******************************************************************************/ + + (*outActRxLen) = rfalConvBitsToBytes( *outActRxLen ); + + + /* Check rcvd msg length, cannot be less then the expected header */ + if( ((*outActRxLen) < gIsoDep.hdrLen) || ((*outActRxLen) >= gIsoDep.ourFsx) ) + { + return ERR_PROTO; + } + + /* Grab rcvd PCB */ + rxPCB = gIsoDep.rxBuf[ ISODEP_PCB_POS ]; + + + /* EMVCo doesn't allow usage of for CID or NAD EMVCo 2.6 TAble 10.2 */ + if( (gIsoDep.compMode == RFAL_COMPLIANCE_MODE_EMV) && ( isoDep_PCBhasDID(rxPCB) || isoDep_PCBhasNAD(rxPCB)) ) + { + return ERR_PROTO; + } + + /* If we are expecting DID, check if PCB signals its presence and if device ID match*/ + if( (gIsoDep.did != RFAL_ISODEP_NO_DID) && ( !isoDep_PCBhasDID(rxPCB) || (gIsoDep.did != gIsoDep.rxBuf[ ISODEP_DID_POS ])) ) + { + return ERR_PROTO; + } + + + /*******************************************************************************/ + /* Process S-Block */ + /*******************************************************************************/ + if( isoDep_PCBisSBlock(rxPCB) ) + { + /* Check if is a Wait Time eXtension */ + if( isoDep_PCBisSWTX(rxPCB) ) + { + /* Rule 3 - respond to S-block: get 1st INF byte S(STW): Power + WTXM */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_S_WTX, isoDep_GetWTXM(gIsoDep.rxBuf[gIsoDep.hdrLen]) ) ); + return ERR_BUSY; + } + + /* Check if is a deselect response */ + if( isoDep_PCBisSDeselect(rxPCB) ) + { + if( gIsoDep.state == ISODEP_ST_PCD_WAIT_DSL ) + { + rfalIsoDepInitialize(); /* Session finished reInit vars */ + return ERR_NONE; + } + + /* Deselect response not expected */ + /* fall through to PROTO error */ + } + /* Unexpected S-Block */ + return ERR_PROTO; + } + + /*******************************************************************************/ + /* Process R-Block */ + /*******************************************************************************/ + else if( isoDep_PCBisRBlock(rxPCB) ) + { + if( isoDep_PCBisRACK(rxPCB) ) /* Check if is a R-ACK */ + { + if( isoDep_GetBN(rxPCB) == gIsoDep.blockNumber ) /* Expected block number */ + { + /* Rule B - ACK with expected bn -> Increment block number */ + gIsoDep.blockNumber = isoDep_PCBNextBN( gIsoDep.blockNumber ); + + /* R-ACK only allowed when PCD chaining */ + if( !gIsoDep.isTxChaining ) + { + return ERR_PROTO; + } + + /* Rule 7 - Chaining transaction done, continue chaining */ + isoDepClearCounters(); + return ERR_NONE; /* This block has been transmitted */ + } + else + { + /* Rule 6 - R-ACK with wrong block number retransmit */ + if( gIsoDep.cntIRetrys++ < gIsoDep.maxRetriesI ) + { + gIsoDep.cntRRetrys = 0; /* Clear R counter only */ + gIsoDep.state = ISODEP_ST_PCD_TX; + return ERR_BUSY; + } + return ERR_PROTO; + } + } + else /* Unexcpected R-Block */ + { + return ERR_PROTO; + } + } + + /*******************************************************************************/ + /* Process I-Block */ + /*******************************************************************************/ + else if( isoDep_PCBisIBlock(rxPCB) ) + { + /*******************************************************************************/ + /* is PICC performing chaining */ + if( isoDep_PCBisChaining(rxPCB) ) + { + gIsoDep.isRxChaining = true; + *outIsChaining = true; + + if( isoDep_GetBN(rxPCB) == gIsoDep.blockNumber ) + { + /* Rule B - ACK with correct block number -> Increase Block number */ + isoDep_ToggleBN( gIsoDep.blockNumber ); + + isoDepClearCounters(); /* Clear counters in case R counter is already at max */ + + /* Rule 2 - Send ACK */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_R_ACK, RFAL_ISODEP_NO_PARAM ) ); + + /* Received I-Block with chaining, send current data to DH */ + + /* remove ISO DEP header, check is necessary to move the INF data on the buffer */ + *outActRxLen -= gIsoDep.hdrLen; + if( (gIsoDep.hdrLen != gIsoDep.rxBufInfPos) && (*outActRxLen > 0U) ) + { + ST_MEMMOVE( &gIsoDep.rxBuf[gIsoDep.rxBufInfPos], &gIsoDep.rxBuf[gIsoDep.hdrLen], *outActRxLen ); + } + + isoDepClearCounters(); + return ERR_AGAIN; /* Send Again signalling to run again, but some chaining data has arrived */ + } + else + { + /* Rule 5 - PICC chaining invalid I-Block -> R-ACK */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_R_ACK, RFAL_ISODEP_NO_PARAM ) ); + } + return ERR_BUSY; + } + + gIsoDep.isRxChaining = false; /* clear PICC chaining flag */ + + if( isoDep_GetBN(rxPCB) == gIsoDep.blockNumber ) + { + /* Rule B - I-Block with correct block number -> Increase Block number */ + isoDep_ToggleBN( gIsoDep.blockNumber ); + + /* I-Block transaction done successfully */ + + /* remove ISO DEP header, check is necessary to move the INF data on the buffer */ + *outActRxLen -= gIsoDep.hdrLen; + if( (gIsoDep.hdrLen != gIsoDep.rxBufInfPos) && (*outActRxLen > 0U) ) + { + ST_MEMMOVE( &gIsoDep.rxBuf[gIsoDep.rxBufInfPos], &gIsoDep.rxBuf[gIsoDep.hdrLen], *outActRxLen ); + } + + gIsoDep.state = ISODEP_ST_IDLE; + isoDepClearCounters(); + return ERR_NONE; + } + else + { + if( (gIsoDep.compMode != RFAL_COMPLIANCE_MODE_ISO) ) + { + /* Invalid Block (not chaining) -> Raise error Digital 1.1 15.2.6.4 EMVCo 2.6 10.3.5.4 */ + return ERR_PROTO; + } + + /* Rule 4 - Invalid Block -> R-NAK */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_R_NAK, RFAL_ISODEP_NO_PARAM ) ); + return ERR_BUSY; + } + } + else /* not S/R/I - Block */ + { + return ERR_PROTO; + } + /* fall through */ + + /*******************************************************************************/ + default: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + /* MISRA 16.4: no empty default (comment will suffice) */ + break; + } + + return ERR_INTERNAL; +} + +/*******************************************************************************/ +ReturnCode rfalIsoDepDeselect( void ) +{ + ReturnCode ret; + uint32_t cntRerun; + bool dummyB; + + /*******************************************************************************/ + /* Check if rx parameters have been set before, otherwise use global variable * + * To cope with a Deselect after RATS\ATTRIB without any I-Block exchanged */ + if( (gIsoDep.rxLen == NULL) || (gIsoDep.rxBuf == NULL) ) + { + /* Using local vars would be safe as rfalIsoDepInitialize will clear the * + * reference to local vars before exiting (no EXIT_ON_ERR), * + * but MISRA 18.6 3217 would be still be flagged. Using static variables */ + gIsoDep.rxLen = &gIsoDep.ctrlRxLen; + gIsoDep.rxBuf = gIsoDep.ctrlRxBuf; + + gIsoDep.rxBufLen = ISODEP_CONTROLMSG_BUF_LEN; + gIsoDep.rxBufInfPos = (RFAL_ISODEP_PCB_LEN + RFAL_ISODEP_DID_LEN); + gIsoDep.txBufInfPos = (RFAL_ISODEP_PCB_LEN + RFAL_ISODEP_DID_LEN); + } + + + /*******************************************************************************/ + /* The Deselect process is being done blocking, Digital 1.0 - 13.2.7.1 MUST wait response and retry*/ + /* Set the maximum reruns while we will wait for a response */ + cntRerun = ISODEP_MAX_RERUNS; + + /* Send DSL request and run protocol until get a response, error or "timeout" */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_S_DSL, RFAL_ISODEP_NO_PARAM )); + do{ + ret = isoDepDataExchangePCD( gIsoDep.rxLen, &dummyB ); + rfalWorker(); + } + while( ((cntRerun--) != 0U) && (ret == ERR_BUSY) ); + + rfalIsoDepInitialize(); + return ((cntRerun == 0U) ? ERR_TIMEOUT : ret); +} + +#endif /* RFAL_FEATURE_ISO_DEP_POLL */ + + +/*******************************************************************************/ +uint32_t rfalIsoDepFWI2FWT( uint8_t fwi ) +{ + uint32_t result; + uint8_t tmpFWI; + + tmpFWI = fwi; + + /* RFU values -> take the default value + * Digital 1.0 11.6.2.17 FWI[1,14] + * Digital 1.1 7.6.2.22 FWI[0,14] + * EMVCo 2.6 Table A.5 FWI[0,14] */ + if( tmpFWI > ISODEP_FWI_MAX ) + { + tmpFWI = RFAL_ISODEP_FWI_DEFAULT; + } + + /* FWT = (256 x 16/fC) x 2^FWI => 2^(FWI+12) Digital 1.1 13.8.1 & 7.9.1 */ + + result = ((uint32_t)1U << (tmpFWI + 12U)); + result = MIN( RFAL_ISODEP_MAX_FWT, result); /* Maximum Frame Waiting Time must be fulfilled */ + + return result; +} + + +/*******************************************************************************/ +uint16_t rfalIsoDepFSxI2FSx( uint8_t FSxI ) +{ + uint16_t fsx; + uint8_t fsi; + + /* Enforce maximum FSxI/FSx allowed - NFC Forum and EMVCo differ */ + fsi = (( gIsoDep.compMode == RFAL_COMPLIANCE_MODE_EMV ) ? MIN( FSxI, RFAL_ISODEP_FSDI_MAX_EMV ) : MIN( FSxI, RFAL_ISODEP_FSDI_MAX_NFC )); + + switch( fsi ) + { + case (uint8_t)RFAL_ISODEP_FSXI_16: fsx = (uint16_t)RFAL_ISODEP_FSX_16; break; + case (uint8_t)RFAL_ISODEP_FSXI_24: fsx = (uint16_t)RFAL_ISODEP_FSX_24; break; + case (uint8_t)RFAL_ISODEP_FSXI_32: fsx = (uint16_t)RFAL_ISODEP_FSX_32; break; + case (uint8_t)RFAL_ISODEP_FSXI_40: fsx = (uint16_t)RFAL_ISODEP_FSX_40; break; + case (uint8_t)RFAL_ISODEP_FSXI_48: fsx = (uint16_t)RFAL_ISODEP_FSX_48; break; + case (uint8_t)RFAL_ISODEP_FSXI_64: fsx = (uint16_t)RFAL_ISODEP_FSX_64; break; + case (uint8_t)RFAL_ISODEP_FSXI_96: fsx = (uint16_t)RFAL_ISODEP_FSX_96; break; + case (uint8_t)RFAL_ISODEP_FSXI_128: fsx = (uint16_t)RFAL_ISODEP_FSX_128; break; + case (uint8_t)RFAL_ISODEP_FSXI_256: fsx = (uint16_t)RFAL_ISODEP_FSX_256; break; + case (uint8_t)RFAL_ISODEP_FSXI_512: fsx = (uint16_t)RFAL_ISODEP_FSX_512; break; + case (uint8_t)RFAL_ISODEP_FSXI_1024: fsx = (uint16_t)RFAL_ISODEP_FSX_1024; break; + case (uint8_t)RFAL_ISODEP_FSXI_2048: fsx = (uint16_t)RFAL_ISODEP_FSX_2048; break; + case (uint8_t)RFAL_ISODEP_FSXI_4096: fsx = (uint16_t)RFAL_ISODEP_FSX_4096; break; + default: fsx = (uint16_t)RFAL_ISODEP_FSX_256; break; + } + return fsx; +} + + +#if RFAL_FEATURE_ISO_DEP_LISTEN + +/*******************************************************************************/ +bool rfalIsoDepIsRats( const uint8_t *buf, uint8_t bufLen ) +{ + if(buf != NULL) + { + if ((RFAL_ISODEP_CMD_RATS == (uint8_t)*buf) && (sizeof(rfalIsoDepRats) == bufLen)) + { + return true; + } + } + return false; +} + + +/*******************************************************************************/ +bool rfalIsoDepIsAttrib( const uint8_t *buf, uint8_t bufLen ) +{ + if(buf != NULL) + { + if ( (RFAL_ISODEP_CMD_ATTRIB == (uint8_t)*buf) && + (RFAL_ISODEP_ATTRIB_REQ_MIN_LEN <= bufLen) && + ((RFAL_ISODEP_ATTRIB_REQ_MIN_LEN + RFAL_ISODEP_ATTRIB_HLINFO_LEN) >= bufLen) ) + { + return true; + } + } + return false; +} + + + +/*******************************************************************************/ +ReturnCode rfalIsoDepListenStartActivation( rfalIsoDepAtsParam *atsParam, const rfalIsoDepAttribResParam *attribResParam, uint8_t *buf, uint16_t bufLen, rfalIsoDepListenActvParam actParam) +{ + uint8_t *txBuf; + uint8_t bufIt; + uint8_t *buffer = buf; + + /*******************************************************************************/ + bufIt = 0; + txBuf = (uint8_t*)actParam.rxBuf; /* Use the rxBuf as TxBuf as well, the struct enforces a size enough MAX( NFCA_ATS_MAX_LEN, NFCB_ATTRIB_RES_MAX_LEN ) */ + gIsoDep.txBR = RFAL_BR_106; + gIsoDep.rxBR = RFAL_BR_106; + + /* Check for a valid buffer pointer */ + if( buffer == NULL ) + { + return ERR_PARAM; + } + + /*******************************************************************************/ + if( *buffer == RFAL_ISODEP_CMD_RATS ) + { + /* Check ATS parameters */ + if( atsParam == NULL ) + { + return ERR_PARAM; + } + + /* If requested copy RATS to device info */ + if( actParam.isoDepDev != NULL ) + { + ST_MEMCPY( (uint8_t*)&actParam.isoDepDev->activation.A.Poller.RATS, buffer, sizeof(rfalIsoDepRats) ); /* Copy RATS' CMD + PARAM */ + } + + + /*******************************************************************************/ + /* Process RATS */ + buffer++; + gIsoDep.fsx = rfalIsoDepFSxI2FSx( (((*buffer) & RFAL_ISODEP_RATS_PARAM_FSDI_MASK) >> RFAL_ISODEP_RATS_PARAM_FSDI_SHIFT) ); + gIsoDep.did = (*buffer & RFAL_ISODEP_DID_MASK); + + + /*******************************************************************************/ + /* Digital 1.1 13.6.1.8 - DID as to between 0 and 14 */ + if( gIsoDep.did > RFAL_ISODEP_DID_MAX ) + { + return ERR_PROTO; + } + + /* Check if we are configured to support DID */ + if( (gIsoDep.did != RFAL_ISODEP_DID_00) && (!atsParam->didSupport) ) + { + return ERR_NOTSUPP; + } + + + /*******************************************************************************/ + /* Check RFAL supported bit rates */ + if( (!(RFAL_SUPPORT_BR_CE_A_212) && (((atsParam->ta & RFAL_ISODEP_ATS_TA_DPL_212) != 0U) || ((atsParam->ta & RFAL_ISODEP_ATS_TA_DLP_212) != 0U))) || + (!(RFAL_SUPPORT_BR_CE_A_424) && (((atsParam->ta & RFAL_ISODEP_ATS_TA_DPL_424) != 0U) || ((atsParam->ta & RFAL_ISODEP_ATS_TA_DLP_424) != 0U))) || + (!(RFAL_SUPPORT_BR_CE_A_848) && (((atsParam->ta & RFAL_ISODEP_ATS_TA_DPL_848) != 0U) || ((atsParam->ta & RFAL_ISODEP_ATS_TA_DLP_848) != 0U))) ) + { + return ERR_NOTSUPP; + } + + /* Enforce proper FWI configuration */ + if( atsParam->fwi > ISODEP_FWI_LIS_MAX) + { + atsParam->fwi = ISODEP_FWI_LIS_MAX; + } + + gIsoDep.atsTA = atsParam->ta; + gIsoDep.fwt = rfalIsoDepFWI2FWT(atsParam->fwi); + gIsoDep.ourFsx = rfalIsoDepFSxI2FSx(atsParam->fsci); + + + /* Ensure proper/maximum Historical Bytes length */ + atsParam->hbLen = MIN( RFAL_ISODEP_ATS_HB_MAX_LEN, atsParam->hbLen ); + + /*******************************************************************************/ + /* Compute ATS */ + + txBuf[ bufIt++ ] = (RFAL_ISODEP_ATS_HIST_OFFSET + atsParam->hbLen); /* TL */ + txBuf[ bufIt++ ] = ( (RFAL_ISODEP_ATS_T0_TA_PRESENCE_MASK | RFAL_ISODEP_ATS_T0_TB_PRESENCE_MASK | + RFAL_ISODEP_ATS_T0_TC_PRESENCE_MASK)| atsParam->fsci ); /* T0 */ + txBuf[ bufIt++ ] = atsParam->ta; /* TA */ + txBuf[ bufIt++ ] = ( (atsParam->fwi << RFAL_ISODEP_RATS_PARAM_FSDI_SHIFT) | + (atsParam->sfgi & RFAL_ISODEP_RATS_PARAM_FSDI_MASK) ); /* TB */ + txBuf[ bufIt++ ] = (uint8_t)((atsParam->didSupport) ? RFAL_ISODEP_ATS_TC_DID : 0U); /* TC */ + + if( atsParam->hbLen > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY( &txBuf[bufIt], atsParam->hb, atsParam->hbLen ); /* T1-Tk */ + bufIt += atsParam->hbLen; + } + + gIsoDep.state = ISODEP_ST_PICC_ACT_ATS; + + } + /*******************************************************************************/ + else if( *buffer == RFAL_ISODEP_CMD_ATTRIB ) + { + /* Check ATTRIB parameters */ + if( attribResParam == NULL ) + { + return ERR_PARAM; + } + + /* REMARK: ATTRIB handling */ + NO_WARNING(attribResParam); + NO_WARNING(bufLen); + return ERR_NOT_IMPLEMENTED; + } + else + { + return ERR_PARAM; + } + + gIsoDep.actvParam = actParam; + + + /*******************************************************************************/ + /* If requested copy to ISO-DEP device info */ + if( actParam.isoDepDev != NULL ) + { + actParam.isoDepDev->info.DID = gIsoDep.did; + actParam.isoDepDev->info.FSx = gIsoDep.fsx; + actParam.isoDepDev->info.FWT = gIsoDep.fwt; + actParam.isoDepDev->info.dFWT = 0; + actParam.isoDepDev->info.DSI = gIsoDep.txBR; + actParam.isoDepDev->info.DRI = gIsoDep.rxBR; + } + + return rfalTransceiveBlockingTx( txBuf, bufIt, (uint8_t*)actParam.rxBuf, sizeof( rfalIsoDepBufFormat ), actParam.rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FWT_NONE ); +} + + +/*******************************************************************************/ +ReturnCode rfalIsoDepListenGetActivationStatus( void ) +{ + ReturnCode err; + uint8_t* txBuf; + uint8_t bufIt; + + rfalBitRate dsi; + rfalBitRate dri; + + + /* Check if Activation is running */ + if( gIsoDep.state < ISODEP_ST_PICC_ACT_ATS ) + { + return ERR_WRONG_STATE; + } + + /* Check if Activation has finished already */ + if( gIsoDep.state >= ISODEP_ST_PICC_RX ) + { + return ERR_NONE; + } + + + /*******************************************************************************/ + /* Check for incoming msg */ + err = rfalGetTransceiveStatus(); + switch( err ) + { + /*******************************************************************************/ + case ERR_NONE: + break; + + /*******************************************************************************/ + case ERR_LINK_LOSS: + case ERR_BUSY: + return err; + + /*******************************************************************************/ + case ERR_CRC: + case ERR_PAR: + case ERR_FRAMING: + + /* ISO14443 4 5.6.2.2 2 If ATS has been replied upon a invalid block, PICC disables the PPS responses */ + if( gIsoDep.state == ISODEP_ST_PICC_ACT_ATS ) + { + gIsoDep.state = ISODEP_ST_PICC_RX; + break; + } + /* fall through */ + + /*******************************************************************************/ + default: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + /* ReEnable the receiver and wait for another frame */ + isoDepReEnableRx( (uint8_t*)gIsoDep.actvParam.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.actvParam.rxLen ); + + return ERR_BUSY; + } + + + txBuf = (uint8_t*)gIsoDep.actvParam.rxBuf; /* Use the rxBuf as TxBuf as well, the struct enforces a size enough MAX(NFCA_PPS_RES_LEN, ISODEP_DSL_MAX_LEN) */ + dri = RFAL_BR_KEEP; /* The RFAL_BR_KEEP is used to check if PPS with BR change was requested */ + dsi = RFAL_BR_KEEP; /* MISRA 9.1 */ + bufIt = 0; + + + /*******************************************************************************/ + gIsoDep.role = ISODEP_ROLE_PICC; + + /*******************************************************************************/ + if( gIsoDep.state == ISODEP_ST_PICC_ACT_ATS ) + { + /* Check for a PPS ISO 14443-4 5.3 */ + if( ( ((uint8_t*)gIsoDep.actvParam.rxBuf)[RFAL_ISODEP_PPS_STARTBYTE_POS] & RFAL_ISODEP_PPS_MASK) == RFAL_ISODEP_PPS_SB ) + { + /* ISO 14443-4 5.3.1 Check if the we are the addressed DID/CID */ + /* ISO 14443-4 5.3.2 Check for a valid PPS0 */ + if( (( ((uint8_t*)gIsoDep.actvParam.rxBuf)[RFAL_ISODEP_PPS_STARTBYTE_POS] & RFAL_ISODEP_DID_MASK) != gIsoDep.did) || + (( ((uint8_t*)gIsoDep.actvParam.rxBuf)[RFAL_ISODEP_PPS_PPS0_POS] & RFAL_ISODEP_PPS0_VALID_MASK) != RFAL_ISODEP_PPS0_PPS1_NOT_PRESENT) ) + { + /* Invalid DID on PPS request or Invalid PPS0, reEnable the receiver and wait another frame */ + isoDepReEnableRx( (uint8_t*)gIsoDep.actvParam.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.actvParam.rxLen ); + + return ERR_BUSY; + } + + /*******************************************************************************/ + /* Check PPS1 presence */ + if( ((uint8_t*)gIsoDep.actvParam.rxBuf)[RFAL_ISODEP_PPS_PPS0_POS] == RFAL_ISODEP_PPS0_PPS1_PRESENT ) + { + uint8_t newdri = ((uint8_t*)gIsoDep.actvParam.rxBuf)[RFAL_ISODEP_PPS_PPS1_POS] & RFAL_ISODEP_PPS1_DxI_MASK; /* MISRA 10.8 */ + uint8_t newdsi = (((uint8_t*)gIsoDep.actvParam.rxBuf)[RFAL_ISODEP_PPS_PPS1_POS] >> RFAL_ISODEP_PPS1_DSI_SHIFT) & RFAL_ISODEP_PPS1_DxI_MASK; /* MISRA 10.8 */ + /* PRQA S 4342 2 # MISRA 10.5 - Layout of enum rfalBitRate and above masks guarantee no invalid enum values to be created */ + dri = (rfalBitRate) (newdri); + dsi = (rfalBitRate) (newdsi); + + if( (!(RFAL_SUPPORT_BR_CE_A_106) && (( dsi == RFAL_BR_106 ) || ( dri == RFAL_BR_106 ))) || + (!(RFAL_SUPPORT_BR_CE_A_212) && (( dsi == RFAL_BR_212 ) || ( dri == RFAL_BR_212 ))) || + (!(RFAL_SUPPORT_BR_CE_A_424) && (( dsi == RFAL_BR_424 ) || ( dri == RFAL_BR_424 ))) || + (!(RFAL_SUPPORT_BR_CE_A_848) && (( dsi == RFAL_BR_848 ) || ( dri == RFAL_BR_848 ))) ) + { + return ERR_PROTO; + } + } + + /*******************************************************************************/ + /* Compute and send PPS RES / Ack */ + txBuf[ bufIt++ ] = ((uint8_t*)gIsoDep.actvParam.rxBuf)[RFAL_ISODEP_PPS_STARTBYTE_POS]; + + rfalTransceiveBlockingTx( txBuf, bufIt, (uint8_t*)gIsoDep.actvParam.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.actvParam.rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FWT_NONE ); + + /*******************************************************************************/ + /* Exchange the bit rates if requested */ + if( dri != RFAL_BR_KEEP ) + { + rfalSetBitRate( dsi, dri ); /* PRQA S 2880 # MISRA 2.1 - Unreachable code due to configuration option being set/unset above (RFAL_SUPPORT_BR_CE_A_xxx) */ + + gIsoDep.txBR = dsi; /* DSI codes the divisor from PICC to PCD */ + gIsoDep.rxBR = dri; /* DRI codes the divisor from PCD to PICC */ + + + if(gIsoDep.actvParam.isoDepDev != NULL) + { + gIsoDep.actvParam.isoDepDev->info.DSI = dsi; + gIsoDep.actvParam.isoDepDev->info.DRI = dri; + } + } + } + /* Check for a S-Deselect is done on Data Exchange Activity */ + } + + /*******************************************************************************/ + gIsoDep.hdrLen = RFAL_ISODEP_PCB_LEN; + gIsoDep.hdrLen += RFAL_ISODEP_DID_LEN; /* Always assume DID to be aligned with Digital 1.1 15.1.2 and ISO14443 4 5.6.3 #454 */ + gIsoDep.hdrLen += (uint8_t)((gIsoDep.nad != RFAL_ISODEP_NO_NAD) ? RFAL_ISODEP_NAD_LEN : 0U); + + /*******************************************************************************/ + /* Rule C - The PICC block number shall be initialized to 1 at activation */ + gIsoDep.blockNumber = 1; + + /* Activation done, keep the rcvd data in, reMap the activation buffer to the global to be retrieved by the DEP method */ + gIsoDep.rxBuf = (uint8_t*)gIsoDep.actvParam.rxBuf; + gIsoDep.rxBufLen = sizeof( rfalIsoDepBufFormat ); + gIsoDep.rxBufInfPos = (uint8_t)((uint32_t)gIsoDep.actvParam.rxBuf->inf - (uint32_t)gIsoDep.actvParam.rxBuf->prologue); + gIsoDep.rxLen = gIsoDep.actvParam.rxLen; + gIsoDep.rxChaining = gIsoDep.actvParam.isRxChaining; + + gIsoDep.state = ISODEP_ST_PICC_RX; + return ERR_NONE; +} + +#endif /* RFAL_FEATURE_ISO_DEP_LISTEN */ + + +/*******************************************************************************/ +uint16_t rfalIsoDepGetMaxInfLen( void ) +{ + /* Check whether all parameters are valid, otherwise return minimum default value */ + if( (gIsoDep.fsx < (uint16_t)RFAL_ISODEP_FSX_16) || (gIsoDep.fsx > (uint16_t)RFAL_ISODEP_FSX_4096) || (gIsoDep.hdrLen > ISODEP_HDR_MAX_LEN) ) + { + uint16_t isodepFsx16 = (uint16_t)RFAL_ISODEP_FSX_16; /* MISRA 10.1 */ + return (isodepFsx16 - RFAL_ISODEP_PCB_LEN - ISODEP_CRC_LEN); + } + + return (gIsoDep.fsx - gIsoDep.hdrLen - ISODEP_CRC_LEN); +} + + +/*******************************************************************************/ +ReturnCode rfalIsoDepStartTransceive( rfalIsoDepTxRxParam param ) +{ + gIsoDep.txBuf = param.txBuf->prologue; + gIsoDep.txBufInfPos = (uint8_t)((uint32_t)param.txBuf->inf - (uint32_t)param.txBuf->prologue); + gIsoDep.txBufLen = param.txBufLen; + gIsoDep.isTxChaining = param.isTxChaining; + + gIsoDep.rxBuf = param.rxBuf->prologue; + gIsoDep.rxBufInfPos = (uint8_t)((uint32_t)param.rxBuf->inf - (uint32_t)param.rxBuf->prologue); + gIsoDep.rxBufLen = sizeof(rfalIsoDepBufFormat); + + gIsoDep.rxLen = param.rxLen; + gIsoDep.rxChaining = param.isRxChaining; + + + gIsoDep.fwt = param.FWT; + gIsoDep.dFwt = param.dFWT; + gIsoDep.fsx = param.FSx; + gIsoDep.did = param.DID; + + /* Only change the FSx from activation if no to Keep */ + gIsoDep.ourFsx = (( param.ourFSx != RFAL_ISODEP_FSX_KEEP ) ? param.ourFSx : gIsoDep.ourFsx); + + /* Clear inner control params for next dataExchange */ + gIsoDep.isRxChaining = false; + isoDepClearCounters(); + + if(gIsoDep.role == ISODEP_ROLE_PICC) + { + if(gIsoDep.txBufLen > 0U) + { + /* Ensure that an RTOX Ack is not being expected at moment */ + if( !gIsoDep.isWait4WTX ) + { + gIsoDep.state = ISODEP_ST_PICC_TX; + return ERR_NONE; + } + else + { + /* If RTOX Ack is expected, signal a pending Tx to be transmitted right after */ + gIsoDep.isTxPending = true; + } + } + + /* Digital 1.1 15.2.5.1 The first block SHALL be sent by the Reader/Writer */ + gIsoDep.state = ISODEP_ST_PICC_RX; + return ERR_NONE; + } + + gIsoDep.state = ISODEP_ST_PCD_TX; + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalIsoDepGetTransceiveStatus( void ) +{ + if( gIsoDep.role == ISODEP_ROLE_PICC) + { +#if RFAL_FEATURE_ISO_DEP_LISTEN + return isoDepDataExchangePICC(); +#else + return ERR_NOTSUPP; +#endif /* RFAL_FEATURE_ISO_DEP_LISTEN */ + } + else + { +#if RFAL_FEATURE_ISO_DEP_POLL + return isoDepDataExchangePCD( gIsoDep.rxLen, gIsoDep.rxChaining ); +#else + return ERR_NOTSUPP; +#endif /* RFAL_FEATURE_ISO_DEP_POLL */ + } +} + + +#if RFAL_FEATURE_ISO_DEP_LISTEN + +/*******************************************************************************/ +static ReturnCode isoDepDataExchangePICC( void ) +{ + uint8_t rxPCB; + ReturnCode ret; + + switch( gIsoDep.state ) + { + /*******************************************************************************/ + case ISODEP_ST_IDLE: + return ERR_NONE; + + + /*******************************************************************************/ + case ISODEP_ST_PICC_TX: + + ret = isoDepTx( isoDep_PCBIBlock( gIsoDep.blockNumber ), gIsoDep.txBuf, &gIsoDep.txBuf[gIsoDep.txBufInfPos], gIsoDep.txBufLen, RFAL_FWT_NONE ); + + /* Clear pending Tx flag */ + gIsoDep.isTxPending = false; + + switch( ret ) + { + case ERR_NONE: + gIsoDep.state = ISODEP_ST_PICC_RX; + return ERR_BUSY; + + default: + /* MISRA 16.4: no empty default statement (a comment being enough) */ + break; + } + return ret; + + + /*******************************************************************************/ + case ISODEP_ST_PICC_RX: + + ret = rfalGetTransceiveStatus(); + switch( ret ) + { + /*******************************************************************************/ + /* Data rcvd with error or timeout -> mute */ + case ERR_TIMEOUT: + case ERR_CRC: + case ERR_PAR: + case ERR_FRAMING: + + /* Digital 1.1 - 15.2.6.2 The CE SHALL NOT attempt error recovery and remains in Rx mode upon Transmission or a Protocol Error */ + isoDepReEnableRx( (uint8_t*)gIsoDep.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.rxLen ); + + return ERR_BUSY; + + /*******************************************************************************/ + case ERR_LINK_LOSS: + return ret; /* Debug purposes */ + + case ERR_BUSY: + return ret; /* Debug purposes */ + + /*******************************************************************************/ + case ERR_NONE: + *gIsoDep.rxLen = rfalConvBitsToBytes( *gIsoDep.rxLen ); + break; + + /*******************************************************************************/ + default: + return ret; + } + break; + + + /*******************************************************************************/ + case ISODEP_ST_PICC_SWTX: + + if( !isoDepTimerisExpired( gIsoDep.WTXTimer ) ) /* Do nothing until WTX timer has expired */ + { + return ERR_BUSY; + } + + /* Set waiting for WTX Ack Flag */ + gIsoDep.isWait4WTX = true; + + /* Digital 1.1 15.2.2.9 - Calculate the WTXM such that FWTtemp <= FWTmax */ + gIsoDep.lastWTXM = (uint8_t)isoDep_WTXMListenerMax( gIsoDep.fwt ); + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_S_WTX, gIsoDep.lastWTXM ) ); + + gIsoDep.state = ISODEP_ST_PICC_RX; /* Go back to Rx to process WTX ack */ + return ERR_BUSY; + + + /*******************************************************************************/ + default: + return ERR_INTERNAL; + } + + /* ISO 14443-4 7.5.6.2 CE SHALL NOT attempt error recovery -> clear counters */ + isoDepClearCounters(); + + /*******************************************************************************/ + /* No error, process incoming msg */ + /*******************************************************************************/ + + /* Grab rcvd PCB */ + rxPCB = gIsoDep.rxBuf[ ISODEP_PCB_POS ]; + + + /*******************************************************************************/ + /* When DID=0 PCD may or may not use DID, therefore check whether current PCD request + * has DID present to be reflected on max INF length #454 */ + + /* ReCalculate Header Length */ + gIsoDep.hdrLen = RFAL_ISODEP_PCB_LEN; + gIsoDep.hdrLen += (uint8_t)( (isoDep_PCBhasDID(rxPCB)) ? RFAL_ISODEP_DID_LEN : 0U ); + gIsoDep.hdrLen += (uint8_t)( (isoDep_PCBhasNAD(rxPCB)) ? RFAL_ISODEP_NAD_LEN : 0U ); + + /* Store whether last PCD block had DID. for PICC special handling of DID = 0 */ + if( gIsoDep.did == RFAL_ISODEP_DID_00 ) + { + gIsoDep.lastDID00 = ( (isoDep_PCBhasDID(rxPCB)) ? true : false ); + } + + /*******************************************************************************/ + /* Check rcvd msg length, cannot be less then the expected header OR * + * if the rcvd msg exceeds our announced frame size (FSD) */ + if( ((*gIsoDep.rxLen) < gIsoDep.hdrLen) || ((*gIsoDep.rxLen) > (gIsoDep.ourFsx - ISODEP_CRC_LEN)) ) + { + isoDepReEnableRx( (uint8_t*)gIsoDep.actvParam.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.actvParam.rxLen ); + return ERR_BUSY; /* ERR_PROTO Ignore this protocol request */ + } + + /* If we are expecting DID, check if PCB signals its presence and if device ID match OR + * If our DID=0 and DID is sent but with an incorrect value */ + if( ((gIsoDep.did != RFAL_ISODEP_DID_00) && ( !isoDep_PCBhasDID(rxPCB) || (gIsoDep.did != gIsoDep.rxBuf[ ISODEP_DID_POS ]))) || + ((gIsoDep.did == RFAL_ISODEP_DID_00) && isoDep_PCBhasDID(rxPCB) && (RFAL_ISODEP_DID_00 != gIsoDep.rxBuf[ ISODEP_DID_POS ]) ) ) + { + isoDepReEnableRx( (uint8_t*)gIsoDep.actvParam.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.actvParam.rxLen ); + return ERR_BUSY; /* Ignore a wrong DID request */ + } + + /* If we aren't expecting NAD and it's received */ + if( (gIsoDep.nad == RFAL_ISODEP_NO_NAD) && isoDep_PCBhasNAD(rxPCB) ) + { + isoDepReEnableRx( (uint8_t*)gIsoDep.actvParam.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.actvParam.rxLen ); + return ERR_BUSY; /* Ignore a unexpected NAD request */ + } + + /*******************************************************************************/ + /* Process S-Block */ + /*******************************************************************************/ + if( isoDep_PCBisSBlock(rxPCB) ) + { + /* Check if is a Wait Time eXtension */ + if( isoDep_PCBisSWTX(rxPCB) ) + { + /* Check if we're expecting a S-WTX */ + if( isoDep_PCBisWTX( gIsoDep.lastPCB ) ) + { + /* Digital 1.1 15.2.2.11 S(WTX) Ack with different WTXM -> Protocol Error * + * Power level indication also should be set to 0 */ + if( ( gIsoDep.rxBuf[ gIsoDep.hdrLen ] == gIsoDep.lastWTXM) && ((*gIsoDep.rxLen - gIsoDep.hdrLen) == ISODEP_SWTX_INF_LEN) ) + { + /* Clear waiting for RTOX Ack Flag */ + gIsoDep.isWait4WTX = false; + + /* Check if a Tx is already pending */ + if( gIsoDep.isTxPending ) + { + /* Has a pending Tx, go immediately to TX */ + gIsoDep.state = ISODEP_ST_PICC_TX; + return ERR_BUSY; + } + + /* Set WTX timer */ + isoDepTimerStart( gIsoDep.WTXTimer, isoDep_WTXAdjust( (gIsoDep.lastWTXM * rfalConv1fcToMs( gIsoDep.fwt )) ) ); + + gIsoDep.state = ISODEP_ST_PICC_SWTX; + return ERR_BUSY; + } + } + /* Unexpected/Incorrect S-WTX, fall into reRenable */ + } + + /* Check if is a deselect request */ + if( isoDep_PCBisSDeselect(rxPCB) && ((*gIsoDep.rxLen - gIsoDep.hdrLen) == ISODEP_SDSL_INF_LEN) ) + { + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_S_DSL, RFAL_ISODEP_NO_PARAM ) ); + + rfalIsoDepInitialize(); /* Session finished reInit vars */ + return ERR_SLEEP_REQ; + } + + /* Unexpected S-Block, fall into reRenable */ + } + + /*******************************************************************************/ + /* Process R-Block */ + /*******************************************************************************/ + else if( isoDep_PCBisRBlock(rxPCB) && ((*gIsoDep.rxLen - gIsoDep.hdrLen) == ISODEP_RBLOCK_INF_LEN)) + { + if( isoDep_PCBisRACK(rxPCB) ) /* Check if is a R-ACK */ + { + if( isoDep_GetBN(rxPCB) == gIsoDep.blockNumber ) /* Check block number */ + { + /* Rule 11 - R(ACK) with current bn -> re-transmit */ + if( !isoDep_PCBisIBlock(gIsoDep.lastPCB) ) + { + isoDepReSendControlMsg(); + } + else + { + gIsoDep.state = ISODEP_ST_PICC_TX; + } + + return ERR_BUSY; + } + else + { + if( !gIsoDep.isTxChaining ) + { + /* Rule 13 violation R(ACK) without performing chaining */ + isoDepReEnableRx( (uint8_t*)gIsoDep.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.rxLen ); + return ERR_BUSY; + } + + /* Rule E - R(ACK) with not current bn -> toogle bn */ + isoDep_ToggleBN( gIsoDep.blockNumber ); + + /* This block has been transmitted and acknowledged, perform WTX until next data is provided */ + + /* Rule 9 - PICC is allowed to send an S(WTX) instead of an I-block or an R(ACK) */ + isoDepTimerStart( gIsoDep.WTXTimer, isoDep_WTXAdjust( rfalConv1fcToMs( gIsoDep.fwt )) ); + gIsoDep.state = ISODEP_ST_PICC_SWTX; + + /* Rule 13 - R(ACK) with not current bn -> continue chaining */ + return ERR_NONE; /* This block has been transmitted */ + } + } + else if( isoDep_PCBisRNAK(rxPCB) ) /* Check if is a R-NACK */ + { + if( isoDep_GetBN(rxPCB) == gIsoDep.blockNumber ) /* Check block number */ + { + /* Rule 11 - R(NAK) with current bn -> re-transmit last x-Block */ + if( !isoDep_PCBisIBlock(gIsoDep.lastPCB) ) + { + isoDepReSendControlMsg(); + } + else + { + gIsoDep.state = ISODEP_ST_PICC_TX; + } + + return ERR_BUSY; + } + else + { + /* Rule 12 - R(NAK) with not current bn -> R(ACK) */ + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_R_ACK, RFAL_ISODEP_NO_PARAM ) ); + + return ERR_BUSY; + } + } + else + { + /* MISRA 15.7 - Empty else */ + } + + /* Unexpected R-Block, fall into reRenable */ + } + + /*******************************************************************************/ + /* Process I-Block */ + /*******************************************************************************/ + else if( isoDep_PCBisIBlock(rxPCB) ) + { + /* Rule D - When an I-block is received, the PICC shall toggle its block number before sending a block */ + isoDep_ToggleBN( gIsoDep.blockNumber ); + + /*******************************************************************************/ + /* Check if the block number is the one expected */ + /* Check if PCD sent an I-Block instead ACK/NACK when we are chaining */ + if( (isoDep_GetBN(rxPCB) != gIsoDep.blockNumber) || (gIsoDep.isTxChaining) ) + { + /* Remain in the same Block Number */ + isoDep_ToggleBN( gIsoDep.blockNumber ); + + /* ISO 14443-4 7.5.6.2 & Digital 1.1 - 15.2.6.2 The CE SHALL NOT attempt error recovery and remains in Rx mode upon Transmission or a Protocol Error */ + isoDepReEnableRx( (uint8_t*)gIsoDep.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.rxLen ); + return ERR_BUSY; + } + + /*******************************************************************************/ + /* is PCD performing chaining ? */ + if( isoDep_PCBisChaining(rxPCB) ) + { + gIsoDep.isRxChaining = true; + *gIsoDep.rxChaining = true; /* Output Parameter*/ + + EXIT_ON_ERR( ret, isoDepHandleControlMsg( ISODEP_R_ACK, RFAL_ISODEP_NO_PARAM ) ); + + /* Received I-Block with chaining, send current data to DH */ + + /* remove ISO DEP header, check is necessary to move the INF data on the buffer */ + *gIsoDep.rxLen -= gIsoDep.hdrLen; + if( (gIsoDep.hdrLen != gIsoDep.rxBufInfPos) && (*gIsoDep.rxLen > 0U) ) + { + ST_MEMMOVE( &gIsoDep.rxBuf[gIsoDep.rxBufInfPos], &gIsoDep.rxBuf[gIsoDep.hdrLen], *gIsoDep.rxLen ); + } + return ERR_AGAIN; /* Send Again signalling to run again, but some chaining data has arrived*/ + } + + + /*******************************************************************************/ + /* PCD is not performing chaining */ + gIsoDep.isRxChaining = false; /* clear PCD chaining flag */ + *gIsoDep.rxChaining = false; /* Output Parameter */ + + /* remove ISO DEP header, check is necessary to move the INF data on the buffer */ + *gIsoDep.rxLen -= gIsoDep.hdrLen; + if( (gIsoDep.hdrLen != gIsoDep.rxBufInfPos) && (*gIsoDep.rxLen > 0U) ) + { + ST_MEMMOVE( &gIsoDep.rxBuf[gIsoDep.rxBufInfPos], &gIsoDep.rxBuf[gIsoDep.hdrLen], *gIsoDep.rxLen ); + } + + + /*******************************************************************************/ + /* Reception done, send data back and start WTX timer */ + isoDepTimerStart( gIsoDep.WTXTimer, isoDep_WTXAdjust( rfalConv1fcToMs( gIsoDep.fwt )) ); + + gIsoDep.state = ISODEP_ST_PICC_SWTX; + return ERR_NONE; + } + else + { + /* MISRA 15.7 - Empty else */ + } + + /* Unexpected/Unknown Block */ + /* ISO 14443-4 7.5.6.2 & Digital 1.1 - 15.2.6.2 The CE SHALL NOT attempt error recovery and remains in Rx mode upon Transmission or a Protocol Error */ + isoDepReEnableRx( (uint8_t*)gIsoDep.rxBuf, sizeof( rfalIsoDepBufFormat ), gIsoDep.rxLen ); + + return ERR_BUSY; +} +#endif /* RFAL_FEATURE_ISO_DEP_LISTEN */ + + +#if RFAL_FEATURE_ISO_DEP_POLL + +#if RFAL_FEATURE_NFCA + +/*******************************************************************************/ +ReturnCode rfalIsoDepRATS( rfalIsoDepFSxI FSDI, uint8_t DID, rfalIsoDepAts *ats , uint8_t *atsLen) +{ + uint16_t rcvLen; + ReturnCode ret; + rfalIsoDepRats ratsReq; + + if( ats == NULL ) + { + return ERR_PARAM; + } + + /*******************************************************************************/ + /* Compose RATS */ + ratsReq.CMD = RFAL_ISODEP_CMD_RATS; + ratsReq.PARAM = (((uint8_t)FSDI << RFAL_ISODEP_RATS_PARAM_FSDI_SHIFT) & RFAL_ISODEP_RATS_PARAM_FSDI_MASK) | (DID & RFAL_ISODEP_RATS_PARAM_DID_MASK); + + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&ratsReq, sizeof(rfalIsoDepRats), (uint8_t*)ats, sizeof(rfalIsoDepAts), &rcvLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ISODEP_T4T_FWT_ACTIVATION ); + + if( ret == ERR_NONE ) + { + /* Check for valid ATS length Digital 1.1 13.6.2.1 & 13.6.2.3 */ + if( (rcvLen < RFAL_ISODEP_ATS_MIN_LEN) || (rcvLen > RFAL_ISODEP_ATS_MAX_LEN) || (ats->TL != rcvLen) ) + { + return ERR_PROTO; + } + + /* Assign our FSx, in case the a Deselect is send without Transceive */ + gIsoDep.ourFsx = rfalIsoDepFSxI2FSx( (uint8_t)FSDI ); + } + + /* Check and assign if ATS length was requested (length also available on TL) */ + if( atsLen != NULL ) + { + *atsLen = (uint8_t)rcvLen; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalIsoDepPPS( uint8_t DID, rfalBitRate DSI, rfalBitRate DRI, rfalIsoDepPpsRes *ppsRes ) +{ + uint16_t rcvLen; + ReturnCode ret; + rfalIsoDepPpsReq ppsReq; + + if( (ppsRes == NULL) || (DSI > RFAL_BR_848) || (DRI > RFAL_BR_848) || (DID > RFAL_ISODEP_DID_MAX) ) + { + return ERR_PARAM; + } + + /*******************************************************************************/ + /* Compose PPS Request */ + ppsReq.PPSS = (RFAL_ISODEP_PPS_SB | (DID & RFAL_ISODEP_PPS_SB_DID_MASK)); + ppsReq.PPS0 = RFAL_ISODEP_PPS_PPS0_PPS1_PRESENT; + ppsReq.PPS1 = (RFAL_ISODEP_PPS_PPS1 | ((((uint8_t)DSI<PPSS != ppsReq.PPSS) ) + { + return ERR_PROTO; + } + } + return ret; +} + +#endif /* RFAL_FEATURE_NFCA */ + + +#if RFAL_FEATURE_NFCB + +/*******************************************************************************/ +ReturnCode rfalIsoDepATTRIB( const uint8_t* nfcid0, uint8_t PARAM1, rfalBitRate DSI, rfalBitRate DRI, rfalIsoDepFSxI FSDI, uint8_t PARAM3, uint8_t DID, const uint8_t* HLInfo, uint8_t HLInfoLen, uint32_t fwt, rfalIsoDepAttribRes *attribRes, uint8_t *attribResLen ) +{ + uint16_t rcvLen; + ReturnCode ret; + rfalIsoDepAttribCmd attribCmd; + + + if( (attribRes == NULL) || (attribResLen == NULL) || (DSI > RFAL_BR_848) || (DRI > RFAL_BR_848) || (DID > RFAL_ISODEP_DID_MAX) ) + { + return ERR_NONE; + } + + /*******************************************************************************/ + /* Compose ATTRIB command */ + attribCmd.cmd = RFAL_ISODEP_CMD_ATTRIB; + attribCmd.Param.PARAM1 = PARAM1; + attribCmd.Param.PARAM2 = ( ((((uint8_t)DSI< 0U) ) + { + ST_MEMCPY(attribCmd.HLInfo, HLInfo, MIN(HLInfoLen, RFAL_ISODEP_ATTRIB_HLINFO_LEN) ); + } + + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&attribCmd, (RFAL_ISODEP_ATTRIB_HDR_LEN + MIN((uint16_t)HLInfoLen, RFAL_ISODEP_ATTRIB_HLINFO_LEN)), (uint8_t*)attribRes, sizeof(rfalIsoDepAttribRes), &rcvLen, RFAL_TXRX_FLAGS_DEFAULT, fwt ); + + *attribResLen = (uint8_t)rcvLen; + + if( ret == ERR_NONE ) + { + /* Check a for valid ATTRIB Response Digital 1.1 15.6.2.1 */ + if( (rcvLen < RFAL_ISODEP_ATTRIB_RES_HDR_LEN) || ((attribRes->mbliDid & RFAL_ISODEP_ATTRIB_RES_DID_MASK) != DID) ) + { + return ERR_PROTO; + } + } + + return ret; +} + +#endif /* RFAL_FEATURE_NFCB */ + + +#if RFAL_FEATURE_NFCA + +/*******************************************************************************/ +ReturnCode rfalIsoDepPollAHandleActivation( rfalIsoDepFSxI FSDI, uint8_t DID, rfalBitRate maxBR, rfalIsoDepDevice *isoDepDev ) +{ + uint8_t RATSretries; + uint8_t msgIt; + ReturnCode ret; + rfalIsoDepPpsRes ppsRes; + + if( isoDepDev == NULL ) + { + return ERR_PARAM; + } + + /* Enable EMD handling according Digital 1.1 4.1.1.1 ; EMVCo 2.6 4.9.2 */ + rfalSetErrorHandling( RFAL_ERRORHANDLING_EMVCO ); + + RATSretries = gIsoDep.maxRetriesRATS; + + /***************************************************************************/ + /* Send RATS */ + do + { + /* Digital 1.1 13.7.1.1 and ISO 14443-4 5.6.1.1 - Upon a failed RATS it may be retransmited [0,1] */ + ret = rfalIsoDepRATS( FSDI, DID, &isoDepDev->activation.A.Listener.ATS, &isoDepDev->activation.A.Listener.ATSLen ); + + /* EMVCo 2.6 9.6.1.1 & 9.6.1.2 If a timeout error is detected retransmit, on transmission error abort */ + if( (gIsoDep.compMode == RFAL_COMPLIANCE_MODE_EMV) && (ret != ERR_NONE) && (ret != ERR_TIMEOUT) ) + { + break; + } + + platformDelay(1); + } + while( ((RATSretries--) != 0U) && (ret != ERR_NONE) ); + + + + /* Switch between NFC Forum and ISO14443-4 behaviour #595 + * ISO14443-4 5.6.1 If RATS fails, a Deactivation sequence should be performed as defined on clause 8 + * Activity 1.1 9.6 Device Deactivation Activity is to be only performed when there's an active device */ + if( ret != ERR_NONE ) + { + if( gIsoDep.compMode == RFAL_COMPLIANCE_MODE_ISO ) + { + rfalIsoDepDeselect(); + } + return ret; + } + + /*******************************************************************************/ + /* Process ATS Response */ + isoDepDev->info.FWI = RFAL_ISODEP_FWI_DEFAULT; /* Default value EMVCo 2.6 5.7.2.6 */ + isoDepDev->info.SFGI = 0; + isoDepDev->info.MBL = 0; + isoDepDev->info.DSI = RFAL_BR_106; + isoDepDev->info.DRI = RFAL_BR_106; + isoDepDev->info.FSxI = (uint8_t)RFAL_ISODEP_FSXI_32; /* FSC default value is 32 bytes ISO14443-A 5.2.3 */ + + + /*******************************************************************************/ + /* Check for ATS optional fields */ + if( isoDepDev->activation.A.Listener.ATS.TL > RFAL_ISODEP_ATS_MIN_LEN ) + { + msgIt = RFAL_ISODEP_ATS_MIN_LEN; + + /* Format byte T0 is optional, if present assign FSDI */ + isoDepDev->info.FSxI = (isoDepDev->activation.A.Listener.ATS.T0 & RFAL_ISODEP_ATS_T0_FSCI_MASK); + + /* T0 has already been processed, always the same position */ + msgIt++; + + /* Check if TA is present */ + if( (isoDepDev->activation.A.Listener.ATS.T0 & RFAL_ISODEP_ATS_T0_TA_PRESENCE_MASK) != 0U ) + { + rfalIsoDepCalcBitRate( maxBR, ((uint8_t*)&isoDepDev->activation.A.Listener.ATS)[msgIt++], &isoDepDev->info.DSI, &isoDepDev->info.DRI ); + } + + /* Check if TB is present */ + if( (isoDepDev->activation.A.Listener.ATS.T0 & RFAL_ISODEP_ATS_T0_TB_PRESENCE_MASK) != 0U ) + { + isoDepDev->info.SFGI = ((uint8_t*)&isoDepDev->activation.A.Listener.ATS)[msgIt++]; + isoDepDev->info.FWI = (uint8_t)((isoDepDev->info.SFGI >> RFAL_ISODEP_ATS_TB_FWI_SHIFT) & RFAL_ISODEP_ATS_FWI_MASK); + isoDepDev->info.SFGI &= RFAL_ISODEP_ATS_TB_SFGI_MASK; + } + + /* Check if TC is present */ + if( (isoDepDev->activation.A.Listener.ATS.T0 & RFAL_ISODEP_ATS_T0_TC_PRESENCE_MASK) != 0U ) + { + /* Check for Protocol features support */ + /* Advanced protocol features defined on Digital 1.0 Table 69, removed after */ + isoDepDev->info.supAdFt = (((((uint8_t*)&isoDepDev->activation.A.Listener.ATS)[msgIt] & RFAL_ISODEP_ATS_TC_ADV_FEAT) != 0U) ? true : false); + isoDepDev->info.supDID = (((((uint8_t*)&isoDepDev->activation.A.Listener.ATS)[msgIt] & RFAL_ISODEP_ATS_TC_DID) != 0U) ? true : false); + isoDepDev->info.supNAD = (((((uint8_t*)&isoDepDev->activation.A.Listener.ATS)[msgIt++] & RFAL_ISODEP_ATS_TC_NAD) != 0U) ? true : false); + } + } + + isoDepDev->info.FSx = rfalIsoDepFSxI2FSx(isoDepDev->info.FSxI); + + isoDepDev->info.SFGT = rfalIsoDepSFGI2SFGT( (uint8_t)isoDepDev->info.SFGI ); + isoDepTimerStart( gIsoDep.SFGTTimer, isoDepDev->info.SFGT ); + + isoDepDev->info.FWT = rfalIsoDepFWI2FWT( isoDepDev->info.FWI ); + isoDepDev->info.dFWT = RFAL_ISODEP_DFWT_20; + + isoDepDev->info.DID = ( (isoDepDev->info.supDID) ? DID : RFAL_ISODEP_NO_DID); + isoDepDev->info.NAD = RFAL_ISODEP_NO_NAD; + + + /*******************************************************************************/ + /* If higher bit rates are supported by both devices, send PPS */ + if( (isoDepDev->info.DSI != RFAL_BR_106) || (isoDepDev->info.DRI != RFAL_BR_106) ) + { + /* Wait until SFGT has been fulfilled */ + while( !isoDepTimerisExpired( gIsoDep.SFGTTimer ) ) { /* MISRA 15.6: mandatory brackets */ }; + + ret = rfalIsoDepPPS( isoDepDev->info.DID, isoDepDev->info.DSI, isoDepDev->info.DRI, &ppsRes ); + + if( ret == ERR_NONE ) + { + /* DSI code the divisor from PICC to PCD */ + /* DRI code the divisor from PCD to PICC */ + rfalSetBitRate( isoDepDev->info.DRI, isoDepDev->info.DSI ); + } + else + { + isoDepDev->info.DSI = RFAL_BR_106; + isoDepDev->info.DRI = RFAL_BR_106; + } + } + + /*******************************************************************************/ + /* Store already FS info, rfalIsoDepGetMaxInfLen() may be called before setting TxRx params */ + gIsoDep.fsx = isoDepDev->info.FSx; + gIsoDep.ourFsx = rfalIsoDepFSxI2FSx( (uint8_t)FSDI ); + + return ERR_NONE; +} + +#endif /* RFAL_FEATURE_NFCA */ + +#if RFAL_FEATURE_NFCB + +/*******************************************************************************/ +ReturnCode rfalIsoDepPollBHandleActivation( rfalIsoDepFSxI FSDI, uint8_t DID, rfalBitRate maxBR, uint8_t PARAM1, const rfalNfcbListenDevice *nfcbDev, const uint8_t* HLInfo, uint8_t HLInfoLen, rfalIsoDepDevice *isoDepDev ) +{ + ReturnCode ret; + uint8_t mbli; + + /***************************************************************************/ + /* Initialize ISO-DEP Device with info from SENSB_RES */ + isoDepDev->info.FWI = ((nfcbDev->sensbRes.protInfo.FwiAdcFo >> RFAL_NFCB_SENSB_RES_FWI_SHIFT) & RFAL_NFCB_SENSB_RES_FWI_MASK); + isoDepDev->info.FWT = rfalIsoDepFWI2FWT( isoDepDev->info.FWI ); + isoDepDev->info.dFWT = RFAL_NFCB_DFWT; + isoDepDev->info.SFGI = (((uint32_t)nfcbDev->sensbRes.protInfo.SFGI >> RFAL_NFCB_SENSB_RES_SFGI_SHIFT) & RFAL_NFCB_SENSB_RES_SFGI_MASK); + isoDepDev->info.SFGT = rfalIsoDepSFGI2SFGT( (uint8_t)isoDepDev->info.SFGI ); + isoDepDev->info.FSxI = ((nfcbDev->sensbRes.protInfo.FsciProType >> RFAL_NFCB_SENSB_RES_FSCI_SHIFT) & RFAL_NFCB_SENSB_RES_FSCI_MASK); + isoDepDev->info.FSx = rfalIsoDepFSxI2FSx(isoDepDev->info.FSxI); + isoDepDev->info.DID = DID; + isoDepDev->info.supDID = ((( nfcbDev->sensbRes.protInfo.FwiAdcFo & RFAL_NFCB_SENSB_RES_FO_DID_MASK ) != 0U) ? true : false); + isoDepDev->info.supNAD = ((( nfcbDev->sensbRes.protInfo.FwiAdcFo & RFAL_NFCB_SENSB_RES_FO_NAD_MASK ) != 0U) ? true : false); + + + /* Check if DID requested is supported by PICC */ + if( (DID != RFAL_ISODEP_NO_DID) && (!isoDepDev->info.supDID) ) + { + return ERR_PARAM; + } + + /* Enable EMD handling according Digital 2.1 4.1.1.1 ; EMVCo 3.0 4.9.2 */ + rfalSetErrorHandling( RFAL_ERRORHANDLING_EMVCO ); + + /***************************************************************************/ + /* Set FDT Poll to be used on upcoming communications */ + if( gIsoDep.compMode == RFAL_COMPLIANCE_MODE_EMV ) + { + /* Disregard Minimum TR2 returned by PICC, always use FDTb MIN EMVCo 3.0 6.3.2.10 */ + rfalSetFDTPoll( RFAL_FDT_POLL_NFCB_POLLER ); + } + else + { + /* Apply minimum TR2 from SENSB_RES Digital 2.1 7.6.2.23 */ + rfalSetFDTPoll( rfalNfcbTR2ToFDT(((nfcbDev->sensbRes.protInfo.FsciProType >>RFAL_NFCB_SENSB_RES_PROTO_TR2_SHIFT) & RFAL_NFCB_SENSB_RES_PROTO_TR2_MASK)) ); + } + + + /* Calculate max Bit Rate */ + rfalIsoDepCalcBitRate( maxBR, nfcbDev->sensbRes.protInfo.BRC, &isoDepDev->info.DSI, &isoDepDev->info.DRI ); + + /***************************************************************************/ + /* Send ATTRIB Command */ + ret = rfalIsoDepATTRIB( (const uint8_t*)&nfcbDev->sensbRes.nfcid0, + (((nfcbDev->sensbRes.protInfo.FwiAdcFo & RFAL_NFCB_SENSB_RES_ADC_ADV_FEATURE_MASK) != 0U) ? PARAM1 : RFAL_ISODEP_ATTRIB_REQ_PARAM1_DEFAULT), + isoDepDev->info.DSI, + isoDepDev->info.DRI, + FSDI, + (gIsoDep.compMode == RFAL_COMPLIANCE_MODE_EMV) ? RFAL_NFCB_SENSB_RES_PROTO_ISO_MASK : (nfcbDev->sensbRes.protInfo.FsciProType & ( (RFAL_NFCB_SENSB_RES_PROTO_TR2_MASK<info.FWT + isoDepDev->info.dFWT), + &isoDepDev->activation.B.Listener.ATTRIB_RES, + &isoDepDev->activation.B.Listener.ATTRIB_RESLen + ); + + /***************************************************************************/ + /* Process ATTRIB Response */ + if( ret == ERR_NONE ) + { + /* Digital 1.1 14.6.2.3 - Check if received DID match */ + if( (isoDepDev->activation.B.Listener.ATTRIB_RES.mbliDid & RFAL_ISODEP_ATTRIB_RES_DID_MASK) != DID ) + { + return ERR_PROTO; + } + + /* Retrieve MBLI and calculate new FDS/MBL (Maximum Buffer Length) */ + mbli = ((isoDepDev->activation.B.Listener.ATTRIB_RES.mbliDid >> RFAL_ISODEP_ATTRIB_RES_MBLI_SHIFT) & RFAL_ISODEP_ATTRIB_RES_MBLI_MASK); + if( mbli > 0U) + { + /* Digital 1.1 14.6.2 Calculate Maximum Buffer Length MBL = FSC x 2^(MBLI-1) */ + isoDepDev->info.MBL = (isoDepDev->info.FSx * ((uint32_t)1U<<(mbli-1U))); + } + + /* DSI code the divisor from PICC to PCD */ + /* DRI code the divisor from PCD to PICC */ + rfalSetBitRate( isoDepDev->info.DRI, isoDepDev->info.DSI ); + + + if( (nfcbDev->sensbRes.protInfo.FwiAdcFo & RFAL_NFCB_SENSB_RES_ADC_ADV_FEATURE_MASK) != 0U ) + { + /* REMARK: SoF EoF TR0 and TR1 are not passed on to RF layer */ + } + + /* Start the SFGT timer */ + isoDepTimerStart( gIsoDep.SFGTTimer, isoDepDev->info.SFGT ); + } + else + { + isoDepDev->info.DSI = RFAL_BR_106; + isoDepDev->info.DRI = RFAL_BR_106; + } + + /*******************************************************************************/ + /* Store already FS info, rfalIsoDepGetMaxInfLen() may be called before setting TxRx params */ + gIsoDep.fsx = isoDepDev->info.FSx; + gIsoDep.ourFsx = rfalIsoDepFSxI2FSx( (uint8_t)FSDI ); + + return ret; +} + +#endif /* RFAL_FEATURE_NFCB */ + + +/*******************************************************************************/ +ReturnCode rfalIsoDepPollHandleSParameters( rfalIsoDepDevice *isoDepDev, rfalBitRate maxTxBR, rfalBitRate maxRxBR ) +{ + uint8_t it; + uint8_t supPCD2PICC; + uint8_t supPICC2PCD; + uint8_t currenttxBR; + uint8_t currentrxBR; + rfalBitRate txBR; + rfalBitRate rxBR; + uint16_t rcvLen; + ReturnCode ret; + rfalIsoDepControlMsgSParam sParam; + + + if( (isoDepDev == NULL) || (maxTxBR > RFAL_BR_13560) || (maxRxBR > RFAL_BR_13560) ) + { + return ERR_PARAM; + } + + it = 0; + supPICC2PCD = 0x00; + supPCD2PICC = 0x00; + txBR = RFAL_BR_106; + rxBR = RFAL_BR_106; + sParam.pcb = ISODEP_PCB_SPARAMETERS; + + /*******************************************************************************/ + /* Send S(PARAMETERS) - Block Info */ + sParam.sParam.tag = RFAL_ISODEP_SPARAM_TAG_BLOCKINFO; + sParam.sParam.value[it++] = RFAL_ISODEP_SPARAM_TAG_BRREQ; + sParam.sParam.value[it++] = RFAL_ISODEP_SPARAM_TAG_BRREQ_LEN; + sParam.sParam.length = it; + + EXIT_ON_ERR( ret, rfalTransceiveBlockingTxRx( (uint8_t*)&sParam, (RFAL_ISODEP_SPARAM_HDR_LEN + (uint16_t)it), (uint8_t*)&sParam, sizeof(rfalIsoDepControlMsgSParam), &rcvLen, RFAL_TXRX_FLAGS_DEFAULT, (isoDepDev->info.FWT + isoDepDev->info.dFWT) )); + + it = 0; + + /*******************************************************************************/ + /* Check S(PARAMETERS) response */ + if( (sParam.pcb != ISODEP_PCB_SPARAMETERS) || (sParam.sParam.tag != RFAL_ISODEP_SPARAM_TAG_BLOCKINFO) || + (sParam.sParam.value[it] != RFAL_ISODEP_SPARAM_TAG_BRIND) || (rcvLen < RFAL_ISODEP_SPARAM_HDR_LEN) || + (rcvLen != ((uint16_t)sParam.sParam.length + RFAL_ISODEP_SPARAM_HDR_LEN)) ) + { + return ERR_PROTO; + } + + /* Retrieve PICC's bit rate PICC capabilities */ + for( it=0; it<(rcvLen-(uint16_t)RFAL_ISODEP_SPARAM_TAG_LEN); it++ ) + { + if( (sParam.sParam.value[it] == RFAL_ISODEP_SPARAM_TAG_SUP_PCD2PICC) && (sParam.sParam.value[it+(uint16_t)RFAL_ISODEP_SPARAM_TAG_LEN] == RFAL_ISODEP_SPARAM_TAG_PCD2PICC_LEN) ) + { + supPCD2PICC = sParam.sParam.value[it + RFAL_ISODEP_SPARAM_TAG_PCD2PICC_LEN]; + } + + if( (sParam.sParam.value[it] == RFAL_ISODEP_SPARAM_TAG_SUP_PICC2PCD) && (sParam.sParam.value[it+(uint16_t)RFAL_ISODEP_SPARAM_TAG_LEN] == RFAL_ISODEP_SPARAM_TAG_PICC2PCD_LEN) ) + { + supPICC2PCD = sParam.sParam.value[it + RFAL_ISODEP_SPARAM_TAG_PICC2PCD_LEN]; + } + } + + /*******************************************************************************/ + /* Check if requested bit rates are supported by PICC */ + if( (supPICC2PCD == 0x00U) || (supPCD2PICC == 0x00U) ) + { + return ERR_PROTO; + } + + for( it=0; it<=(uint8_t)maxTxBR; it++ ) + { + if( (supPCD2PICC & (0x01U << it)) != 0U ) + { + txBR = (rfalBitRate)it; /* PRQA S 4342 # MISRA 10.5 - Layout of enum rfalBitRate and above clamping of maxTxBR guarantee no invalid enum values to be created */ + } + } + for( it=0; it<=(uint8_t)maxRxBR; it++ ) + { + if( (supPICC2PCD & (0x01U << it)) != 0U ) + { + rxBR = (rfalBitRate)it; /* PRQA S 4342 # MISRA 10.5 - Layout of enum rfalBitRate and above clamping of maxTxBR guarantee no invalid enum values to be created */ + } + } + + it = 0; + currenttxBR = (uint8_t)txBR; + currentrxBR = (uint8_t)rxBR; + + /*******************************************************************************/ + /* Send S(PARAMETERS) - Bit rates Activation */ + sParam.sParam.tag = RFAL_ISODEP_SPARAM_TAG_BLOCKINFO; + sParam.sParam.value[it++] = RFAL_ISODEP_SPARAM_TAG_BRACT; + sParam.sParam.value[it++] = ( RFAL_ISODEP_SPARAM_TVL_HDR_LEN + RFAL_ISODEP_SPARAM_TAG_PCD2PICC_LEN + RFAL_ISODEP_SPARAM_TVL_HDR_LEN + RFAL_ISODEP_SPARAM_TAG_PICC2PCD_LEN); + sParam.sParam.value[it++] = RFAL_ISODEP_SPARAM_TAG_SEL_PCD2PICC; + sParam.sParam.value[it++] = RFAL_ISODEP_SPARAM_TAG_PCD2PICC_LEN; + sParam.sParam.value[it++] = ((uint8_t)0x01U << currenttxBR); + sParam.sParam.value[it++] = 0x00U; + sParam.sParam.value[it++] = RFAL_ISODEP_SPARAM_TAG_SEL_PICC2PCD; + sParam.sParam.value[it++] = RFAL_ISODEP_SPARAM_TAG_PICC2PCD_LEN; + sParam.sParam.value[it++] = ((uint8_t)0x01U << currentrxBR); + sParam.sParam.value[it++] = 0x00U; + sParam.sParam.length = it; + + EXIT_ON_ERR( ret, rfalTransceiveBlockingTxRx( (uint8_t*)&sParam, (RFAL_ISODEP_SPARAM_HDR_LEN + (uint16_t)it), (uint8_t*)&sParam, sizeof(rfalIsoDepControlMsgSParam), &rcvLen, RFAL_TXRX_FLAGS_DEFAULT, (isoDepDev->info.FWT + isoDepDev->info.dFWT) )); + + it = 0; + + /*******************************************************************************/ + /* Check S(PARAMETERS) Acknowledge */ + if( (sParam.pcb != ISODEP_PCB_SPARAMETERS) || (sParam.sParam.tag != RFAL_ISODEP_SPARAM_TAG_BLOCKINFO) || + (sParam.sParam.value[it] != RFAL_ISODEP_SPARAM_TAG_BRACK) || (rcvLen < RFAL_ISODEP_SPARAM_HDR_LEN) ) + { + return ERR_PROTO; + } + + EXIT_ON_ERR( ret, rfalSetBitRate( txBR, rxBR ) ); + + isoDepDev->info.DRI = txBR; + isoDepDev->info.DSI = rxBR; + + return ERR_NONE; +} + + +/*******************************************************************************/ +static void rfalIsoDepCalcBitRate( rfalBitRate maxAllowedBR, uint8_t piccBRCapability, rfalBitRate *dsi, rfalBitRate *dri ) +{ + uint8_t driMask; + uint8_t dsiMask; + int8_t i; + bool bitrateFound; + rfalBitRate curMaxBR; + + curMaxBR = maxAllowedBR; + + do + { + bitrateFound = true; + + (*dsi) = RFAL_BR_106; + (*dri) = RFAL_BR_106; + + /* Digital 1.0 5.6.2.5 & 11.6.2.14: A received RFU value of b4 = 1b MUST be interpreted as if b7 to b1 ? 0000000b (only 106 kbits/s in both direction) */ + if( ((RFAL_ISODEP_BITRATE_RFU_MASK & piccBRCapability) != 0U) || (curMaxBR > RFAL_BR_848) ) + { + return; + } + + /***************************************************************************/ + /* Determine Listen->Poll bit rate */ + dsiMask = (piccBRCapability & RFAL_ISODEP_BSI_MASK); + for( i = 2; i >= 0; i-- ) // Check supported bit rate from the highest + { + if (((dsiMask & (0x10U << (uint8_t)i)) != 0U) && (((uint8_t)i+1U) <= (uint8_t)curMaxBR)) + { + uint8_t newdsi = ((uint8_t) i) + 1U; + (*dsi) = (rfalBitRate)newdsi; /* PRQA S 4342 # MISRA 10.5 - Layout of enum rfalBitRate and range of loop variable guarantee no invalid enum values to be created */ + break; + } + } + + /***************************************************************************/ + /* Determine Poll->Listen bit rate */ + driMask = (piccBRCapability & RFAL_ISODEP_BRI_MASK); + for( i = 2; i >= 0; i-- ) /* Check supported bit rate from the highest */ + { + if (((driMask & (0x01U << (uint8_t)i)) != 0U) && (((uint8_t)i+1U) <= (uint8_t)curMaxBR)) + { + uint8_t newdri = ((uint8_t) i) + 1U; + (*dri) = (rfalBitRate)newdri; /* PRQA S 4342 # MISRA 10.5 - Layout of enum rfalBitRate and range of loop variable guarantee no invalid enum values to be created */ + break; + } + } + + /***************************************************************************/ + /* Check if different bit rate is supported */ + + /* Digital 1.0 Table 67: if b8=1b, then only the same bit rate divisor for both directions is supported */ + if( (piccBRCapability & RFAL_ISODEP_SAME_BITRATE_MASK) != 0U ) + { + (*dsi) = MIN((*dsi), (*dri)); + (*dri) = (*dsi); + /* Check that the baudrate is supported */ + if( (RFAL_BR_106 != (*dsi)) && ( !(((dsiMask & (0x10U << ((uint8_t)(*dsi) - 1U))) != 0U) && ((driMask & (0x01U << ((uint8_t)(*dri) - 1U))) != 0U)) ) ) + { + bitrateFound = false; + curMaxBR = (*dsi); /* set allowed bitrate to be lowest and determine bit rate again */ + } + } + } while (!(bitrateFound)); + +} + +/*******************************************************************************/ +static uint32_t rfalIsoDepSFGI2SFGT( uint8_t sfgi ) +{ + uint32_t sfgt; + uint8_t tmpSFGI; + + tmpSFGI = sfgi; + + if (tmpSFGI > ISODEP_SFGI_MAX) + { + tmpSFGI = ISODEP_SFGI_MIN; + } + + if (tmpSFGI != ISODEP_SFGI_MIN) + { + /* If sfgi != 0 wait SFGT + dSFGT Digital 1.1 13.8.2.1 */ + sfgt = isoDepCalcSGFT(sfgi) + isoDepCalcdSGFT(sfgi); + } + /* Otherwise use FDTPoll min Digital 1.1 13.8.2.3*/ + else + { + sfgt = RFAL_FDT_POLL_NFCA_POLLER; + } + + /* Convert carrier cycles to milli seconds */ + return (rfalConv1fcToMs(sfgt) + 1U); +} + +#endif /* RFAL_FEATURE_ISO_DEP_POLL */ + + + /*******************************************************************************/ + static void rfalIsoDepApdu2IBLockParam( rfalIsoDepApduTxRxParam apduParam, rfalIsoDepTxRxParam *iBlockParam, uint16_t txPos, uint16_t rxPos ) +{ + NO_WARNING(rxPos); /* Keep this param for future use */ + + iBlockParam->DID = apduParam.DID; + iBlockParam->FSx = apduParam.FSx; + iBlockParam->ourFSx = apduParam.ourFSx; + iBlockParam->FWT = apduParam.FWT; + iBlockParam->dFWT = apduParam.dFWT; + + if( (apduParam.txBufLen - txPos) > rfalIsoDepGetMaxInfLen() ) + { + iBlockParam->isTxChaining = true; + iBlockParam->txBufLen = rfalIsoDepGetMaxInfLen(); + } + else + { + iBlockParam->isTxChaining = false; + iBlockParam->txBufLen = (apduParam.txBufLen - txPos); + } + + /* TxBuf is moved to the beginning for every I-Block */ + iBlockParam->txBuf = (rfalIsoDepBufFormat*)apduParam.txBuf; /* PRQA S 0310 # MISRA 11.3 - Intentional safe cast to avoiding large buffer duplication */ + iBlockParam->rxBuf = apduParam.tmpBuf; /* Simply using the apdu buffer is not possible because of current ACK handling */ + iBlockParam->isRxChaining = &gIsoDep.isAPDURxChaining; + iBlockParam->rxLen = apduParam.rxLen; +} + + +/*******************************************************************************/ +ReturnCode rfalIsoDepStartApduTransceive( rfalIsoDepApduTxRxParam param ) +{ + rfalIsoDepTxRxParam txRxParam; + + /* Initialize and store APDU context */ + gIsoDep.APDUParam = param; + gIsoDep.APDUTxPos = 0; + gIsoDep.APDURxPos = 0; + + /* Assign current FSx to calculate INF length */ + gIsoDep.ourFsx = param.ourFSx; + gIsoDep.fsx = param.FSx; + + /* Convert APDU TxRxParams to I-Block TxRxParams */ + rfalIsoDepApdu2IBLockParam( gIsoDep.APDUParam, &txRxParam, gIsoDep.APDUTxPos, gIsoDep.APDURxPos ); + + return rfalIsoDepStartTransceive( txRxParam ); +} + + +/*******************************************************************************/ +ReturnCode rfalIsoDepGetApduTransceiveStatus( void ) +{ + ReturnCode ret; + rfalIsoDepTxRxParam txRxParam; + + ret = rfalIsoDepGetTransceiveStatus(); + switch( ret ) + { + /*******************************************************************************/ + case ERR_NONE: + + /* Check if we are still doing chaining on Tx */ + if( gIsoDep.isTxChaining ) + { + /* Add already Tx bytes */ + gIsoDep.APDUTxPos += gIsoDep.txBufLen; + + /* Convert APDU TxRxParams to I-Block TxRxParams */ + rfalIsoDepApdu2IBLockParam( gIsoDep.APDUParam, &txRxParam, gIsoDep.APDUTxPos, gIsoDep.APDURxPos ); + + if( txRxParam.txBufLen > 0U ) /* MISRA 21.18 */ + { + /* Move next I-Block to beginning of APDU Tx buffer */ + ST_MEMCPY( gIsoDep.APDUParam.txBuf->apdu, &gIsoDep.APDUParam.txBuf->apdu[gIsoDep.APDUTxPos], txRxParam.txBufLen ); + } + + rfalIsoDepStartTransceive( txRxParam ); + return ERR_BUSY; + } + + if( *gIsoDep.APDUParam.rxLen > 0U ) /* MISRA 21.18 */ + { + /* Copy packet from tmp buffer to APDU buffer */ + ST_MEMCPY( &gIsoDep.APDUParam.rxBuf->apdu[gIsoDep.APDURxPos], gIsoDep.APDUParam.tmpBuf->inf, *gIsoDep.APDUParam.rxLen ); + gIsoDep.APDURxPos += *gIsoDep.APDUParam.rxLen; + } + + /* APDU TxRx is done */ + break; + + /*******************************************************************************/ + case ERR_AGAIN: + + if( *gIsoDep.APDUParam.rxLen > 0U ) /* MISRA 21.18 */ + { + /* Copy chained packet from tmp buffer to APDU buffer */ + ST_MEMCPY( &gIsoDep.APDUParam.rxBuf->apdu[gIsoDep.APDURxPos], gIsoDep.APDUParam.tmpBuf->inf, *gIsoDep.APDUParam.rxLen ); + gIsoDep.APDURxPos += *gIsoDep.APDUParam.rxLen; + } + + /* Wait for next I-Block */ + return ERR_BUSY; + + /*******************************************************************************/ + default: + return ret; + } + + *gIsoDep.APDUParam.rxLen = gIsoDep.APDURxPos; + + return ERR_NONE; + } + +#endif /* RFAL_FEATURE_ISO_DEP */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_nfc.c b/Software/fab-reader2-c/components/rfal/Src/rfal_nfc.c new file mode 100644 index 0000000..26223d1 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_nfc.c @@ -0,0 +1,1684 @@ +/** + ****************************************************************************** + * + * COPYRIGHT(c) 2017 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/*! \file rfal_nfc.c + * + * \author Gustavo Patricio + * + * \brief RFAL NFC device + * + * This module provides the required features to behave as an NFC Poller + * or Listener device. It grants an easy to use interface for the following + * activities: Technology Detection, Collision Resollution, Activation, + * Data Exchange, and Deactivation + * + * This layer is influenced by (but not fully aligned with) the NFC Forum + * specifications, in particular: Activity 2.0 and NCI 2.0 + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_nfc.h" +#include "utils.h" +#include "rfal_analogConfig.h" + + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ +#define RFAL_NFC_MAX_DEVICES 5U /* Max number of devices supported */ + + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ +#define rfalNfcIsRemDevPoller( tp ) ( ((tp)>= RFAL_NFC_POLL_TYPE_NFCA) && ((tp)<=RFAL_NFC_POLL_TYPE_AP2P ) ) +#define rfalNfcIsRemDevListener( tp ) ( /*((tp)>= RFAL_NFC_LISTEN_TYPE_NFCA) && */ ((tp)<=RFAL_NFC_LISTEN_TYPE_AP2P) ) + +#define rfalNfcNfcNotify( st ) if( gNfcDev.disc.notifyCb != NULL ) gNfcDev.disc.notifyCb( st ) + + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +typedef struct{ + rfalNfcState state; /* Main state */ + uint16_t techsFound; /* Technologies found bitmask */ + uint16_t techs2do; /* Technologies still to be performed */ + rfalBitRate ap2pBR; /* Bit rate to poll for AP2P */ + uint8_t selDevIdx; /* Selected device index */ + rfalNfcDevice *activeDev; /* Active device pointer */ + rfalNfcDiscoverParam disc; /* Discovery parameters pointer */ + rfalNfcDevice devList[RFAL_NFC_MAX_DEVICES]; /*!< Location of device list */ + uint8_t devCnt; /* Decices found counter */ + uint32_t discTmr; /* Discovery Total duration timer */ + ReturnCode dataExErr; /* Last Data Exchange error */ + bool discRestart; /* Restart discover after deactivation flag */ + bool isRxChaining; /* Flag indicating Other device is chaining */ + uint32_t lmMask; /* Listen Mode mask */ + + rfalNfcBuffer txBuf; /* Tx buffer for Data Exchange */ + rfalNfcBuffer rxBuf; /* Rx buffer for Data Exchange */ + uint16_t rxLen; /* Length of received data on Data Exchange */ +}rfalNfc; + + +/* + ****************************************************************************** + * LOCAL VARIABLES + ****************************************************************************** + */ +static rfalNfc gNfcDev; + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +static ReturnCode rfalNfcPollTechDetetection( void ); +static ReturnCode rfalNfcPollCollResolution( void ); +static ReturnCode rfalNfcPollActivation( uint8_t devIt ); +static ReturnCode rfalNfcDeactivation( void ); + +#if RFAL_FEATURE_NFC_DEP +static ReturnCode rfalNfcNfcDepActivate( rfalNfcDevice *device, rfalNfcDepCommMode commMode, const uint8_t *atrReq, uint16_t atrReqLen ); +#endif /* RFAL_FEATURE_NFC_DEP */ + +#if RFAL_FEATURE_LISTEN_MODE +static ReturnCode rfalNfcListenActivation( void ); +#endif /* RFAL_FEATURE_LISTEN_MODE*/ + + +/*******************************************************************************/ +ReturnCode rfalNfcInitialize( void ) +{ + ReturnCode err; + + gNfcDev.state = RFAL_NFC_STATE_NOTINIT; + + rfalAnalogConfigInitialize(); /* Initialize RFAL's Analog Configs */ + EXIT_ON_ERR( err, rfalInitialize() ); /* Initialize RFAL */ + + gNfcDev.state = RFAL_NFC_STATE_IDLE; /* Go to initialized */ + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcDiscover( const rfalNfcDiscoverParam *disParams ) +{ + /* Check if initialization has been performed */ + if( gNfcDev.state != RFAL_NFC_STATE_IDLE ) + { + return ERR_WRONG_STATE; + } + + /* Check valid parameters */ + if( (disParams == NULL) || (disParams->devLimit > RFAL_NFC_MAX_DEVICES) || (disParams->devLimit == 0U) || + ( ((disParams->techs2Find & RFAL_NFC_POLL_TECH_F) != 0U) && (disParams->nfcfBR != RFAL_BR_212) && (disParams->nfcfBR != RFAL_BR_424) ) || + ( (((disParams->techs2Find & RFAL_NFC_POLL_TECH_AP2P) != 0U) && (disParams->ap2pBR > RFAL_BR_424)) || (disParams->GBLen > RFAL_NFCDEP_GB_MAX_LEN)) ) + { + return ERR_PARAM; + } + + if( (((disParams->techs2Find & RFAL_NFC_POLL_TECH_A) != 0U) && !((bool)RFAL_FEATURE_NFCA)) || + (((disParams->techs2Find & RFAL_NFC_POLL_TECH_B) != 0U) && !((bool)RFAL_FEATURE_NFCB)) || + (((disParams->techs2Find & RFAL_NFC_POLL_TECH_F) != 0U) && !((bool)RFAL_FEATURE_NFCF)) || + (((disParams->techs2Find & RFAL_NFC_POLL_TECH_V) != 0U) && !((bool)RFAL_FEATURE_NFCV)) || + (((disParams->techs2Find & RFAL_NFC_POLL_TECH_ST25TB) != 0U) && !((bool)RFAL_FEATURE_ST25TB)) || + (((disParams->techs2Find & RFAL_NFC_POLL_TECH_AP2P) != 0U) && !((bool)RFAL_FEATURE_NFC_DEP)) || + (((disParams->techs2Find & RFAL_NFC_LISTEN_TECH_A) != 0U) && !((bool)RFAL_FEATURE_NFCA)) || + (((disParams->techs2Find & RFAL_NFC_LISTEN_TECH_B) != 0U) && !((bool)RFAL_FEATURE_NFCB)) || + (((disParams->techs2Find & RFAL_NFC_LISTEN_TECH_F) != 0U) && !((bool)RFAL_FEATURE_NFCF)) || + (((disParams->techs2Find & RFAL_NFC_LISTEN_TECH_AP2P) != 0U) && !((bool)RFAL_FEATURE_NFC_DEP)) ) + { + return ERR_DISABLED; /* PRQA S 2880 # MISRA 2.1 - Unreachable code due to configuration option being set/unset */ + } + + /* Initialize context for discovery */ + gNfcDev.activeDev = NULL; + gNfcDev.techsFound = RFAL_NFC_TECH_NONE; + gNfcDev.devCnt = 0; + gNfcDev.discRestart = true; + gNfcDev.disc = *disParams; + + + /* Calculate Listen Mask */ + gNfcDev.lmMask = 0U; + gNfcDev.lmMask |= (((gNfcDev.disc.techs2Find & RFAL_NFC_LISTEN_TECH_A) != 0U) ? RFAL_LM_MASK_NFCA : 0U); + gNfcDev.lmMask |= (((gNfcDev.disc.techs2Find & RFAL_NFC_LISTEN_TECH_B) != 0U) ? RFAL_LM_MASK_NFCB : 0U); + gNfcDev.lmMask |= (((gNfcDev.disc.techs2Find & RFAL_NFC_LISTEN_TECH_F) != 0U) ? RFAL_LM_MASK_NFCF : 0U); + gNfcDev.lmMask |= (((gNfcDev.disc.techs2Find & RFAL_NFC_LISTEN_TECH_AP2P) != 0U) ? RFAL_LM_MASK_ACTIVE_P2P : 0U); + +#if !RFAL_FEATURE_LISTEN_MODE + /* Check if Listen Mode is supported/Enabled */ + if( gNfcDev.lmMask != 0U ) + { + return ERR_NOTSUPP; + } +#endif + + gNfcDev.state = RFAL_NFC_STATE_START_DISCOVERY; + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcDeactivate( bool discovery ) +{ + /* Check for valid state */ + if( gNfcDev.state <= RFAL_NFC_STATE_IDLE ) + { + return ERR_WRONG_STATE; + } + + /* Check if discovery is to continue afterwards */ + if( discovery == true ) + { + /* If so let the state machine continue*/ + gNfcDev.discRestart = discovery; + gNfcDev.state = RFAL_NFC_STATE_DEACTIVATION; + } + else + { + /* Otherwise deactivate immediately and go to IDLE */ + rfalNfcDeactivation(); + gNfcDev.state = RFAL_NFC_STATE_IDLE; + } + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcSelect( uint8_t devIdx ) +{ + /* Check for valid state */ + if( gNfcDev.state != RFAL_NFC_STATE_POLL_SELECT ) + { + return ERR_WRONG_STATE; + } + + gNfcDev.selDevIdx = devIdx; + gNfcDev.state = RFAL_NFC_STATE_POLL_ACTIVATION; + + return ERR_NONE; +} + +/*******************************************************************************/ +rfalNfcState rfalNfcGetState( void ) +{ + return gNfcDev.state; +} + +/*******************************************************************************/ +ReturnCode rfalNfcGetDevicesFound( rfalNfcDevice **devList, uint8_t *devCnt ) +{ + /* Check for valid state */ + if( gNfcDev.state < RFAL_NFC_STATE_POLL_SELECT ) + { + return ERR_WRONG_STATE; + } + + /* Check valid parameters */ + if( (devList == NULL) || (devCnt == NULL) ) + { + return ERR_PARAM; + } + + *devCnt = gNfcDev.devCnt; + *devList = gNfcDev.devList; + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcGetActiveDevice( rfalNfcDevice **dev ) +{ + /* Check for valid state */ + if( gNfcDev.state < RFAL_NFC_STATE_ACTIVATED ) + { + return ERR_WRONG_STATE; + } + + /* Check valid parameter */ + if( dev == NULL ) + { + return ERR_PARAM; + } + + /* Check for valid state */ + if( (gNfcDev.devCnt == 0U) || (gNfcDev.activeDev == NULL) ) + { + return ERR_REQUEST; + } + + *dev = gNfcDev.activeDev; + return ERR_NONE; +} + +/*******************************************************************************/ +void rfalNfcWorker( void ) +{ + ReturnCode err; + + rfalWorker(); /* Execute RFAL process */ + + switch( gNfcDev.state ) + { + /*******************************************************************************/ + case RFAL_NFC_STATE_NOTINIT: + case RFAL_NFC_STATE_IDLE: + break; + + /*******************************************************************************/ + case RFAL_NFC_STATE_START_DISCOVERY: + + /* Initialize context for discovery cycle */ + gNfcDev.devCnt = 0; + gNfcDev.selDevIdx = 0; + gNfcDev.techsFound = RFAL_NFC_TECH_NONE; + gNfcDev.techs2do = gNfcDev.disc.techs2Find; + gNfcDev.state = RFAL_NFC_STATE_POLL_TECHDETECT; + + #if RFAL_FEATURE_WAKEUP_MODE + /* Check if Low power Wake-Up is to be performed */ + if( gNfcDev.disc.wakeupEnabled ) + { + /* Initialize Low power Wake-up mode and wait */ + err = rfalWakeUpModeStart( (gNfcDev.disc.wakeupConfigDefault ? NULL : &gNfcDev.disc.wakeupConfig) ); + if( err == ERR_NONE ) + { + gNfcDev.state = RFAL_NFC_STATE_WAKEUP_MODE; + rfalNfcNfcNotify( gNfcDev.state ); /* Notify caller that WU was started */ + } + } + #endif /* RFAL_FEATURE_WAKEUP_MODE */ + break; + + /*******************************************************************************/ + case RFAL_NFC_STATE_WAKEUP_MODE: + + #if RFAL_FEATURE_WAKEUP_MODE + /* Check if the Wake-up mode has woke */ + if( rfalWakeUpModeHasWoke() ) + { + rfalWakeUpModeStop(); /* Disable Wake-up mode */ + gNfcDev.state = RFAL_NFC_STATE_POLL_TECHDETECT; /* Go to Technology detection */ + + rfalNfcNfcNotify( gNfcDev.state ); /* Notify caller that WU has woke */ + } + #endif /* RFAL_FEATURE_WAKEUP_MODE */ + + break; + + /*******************************************************************************/ + case RFAL_NFC_STATE_POLL_TECHDETECT: + + /* Start total duration timer */ + gNfcDev.discTmr = (uint32_t)platformTimerCreate( gNfcDev.disc.totalDuration ); + + err = rfalNfcPollTechDetetection(); /* Perform Technology Detection */ + if( err != ERR_BUSY ) /* Wait until all technologies are performed */ + { + if( ( err != ERR_NONE) || (gNfcDev.techsFound == RFAL_NFC_TECH_NONE) )/* Check if any error occurred or no techs were found */ + { + rfalFieldOff(); + gNfcDev.state = RFAL_NFC_STATE_LISTEN_TECHDETECT; /* Nothing found as poller, go to listener */ + break; + } + + gNfcDev.techs2do = gNfcDev.techsFound; /* Store the found technologies for collision resolution */ + gNfcDev.state = RFAL_NFC_STATE_POLL_COLAVOIDANCE; /* One or more devices found, go to Collision Avoidance */ + } + break; + + + /*******************************************************************************/ + case RFAL_NFC_STATE_POLL_COLAVOIDANCE: + + err = rfalNfcPollCollResolution(); /* Resolve any eventual collision */ + if( err != ERR_BUSY ) /* Wait until all technologies are performed */ + { + if( (err != ERR_NONE) || (gNfcDev.devCnt == 0U) ) /* Check if any error occurred or no devices were found */ + { + gNfcDev.state = RFAL_NFC_STATE_DEACTIVATION; + break; /* Unable to retrieve any device, restart loop */ + } + + /* Check if more than one device has been found */ + if( gNfcDev.devCnt > 1U ) + { + /* If more than one device was found inform upper layer to choose which one to activate */ + if( gNfcDev.disc.notifyCb != NULL ) + { + gNfcDev.state = RFAL_NFC_STATE_POLL_SELECT; + gNfcDev.disc.notifyCb( gNfcDev.state ); + break; + } + } + + /* If only one device or no callback has been set, activate the first device found */ + gNfcDev.selDevIdx = 0U; + gNfcDev.state = RFAL_NFC_STATE_POLL_ACTIVATION; + } + break; + + + /*******************************************************************************/ + case RFAL_NFC_STATE_POLL_ACTIVATION: + + if( rfalNfcPollActivation( gNfcDev.selDevIdx ) != ERR_NONE ) /* Activate selected device */ + { + gNfcDev.state = RFAL_NFC_STATE_DEACTIVATION; /* If Activation failed, restart loop */ + break; + } + + gNfcDev.state = RFAL_NFC_STATE_ACTIVATED; /* Device has been properly activated */ + rfalNfcNfcNotify( gNfcDev.state ); /* Inform upper layer that a device has been activated */ + break; + + + /*******************************************************************************/ + case RFAL_NFC_STATE_DATAEXCHANGE: + + rfalNfcDataExchangeGetStatus(); /* Run the internal state machine */ + + if( gNfcDev.dataExErr != ERR_BUSY ) /* If Dataexchange has terminated */ + { + gNfcDev.state = RFAL_NFC_STATE_DATAEXCHANGE_DONE; /* Go to done state */ + rfalNfcNfcNotify( gNfcDev.state ); /* And notify caller */ + } + if( gNfcDev.dataExErr == ERR_SLEEP_REQ ) /* Check if Listen mode has to go to Sleep */ + { + gNfcDev.state = RFAL_NFC_STATE_LISTEN_SLEEP; /* Go to Listen Sleep state */ + rfalNfcNfcNotify( gNfcDev.state ); /* And notify caller */ + } + break; + + + /*******************************************************************************/ + case RFAL_NFC_STATE_DEACTIVATION: + + rfalNfcDeactivation(); /* Deactivate current device */ + + gNfcDev.state = ((gNfcDev.discRestart) ? RFAL_NFC_STATE_START_DISCOVERY : RFAL_NFC_STATE_IDLE); + rfalNfcNfcNotify( gNfcDev.state ); /* Notify caller */ + break; + + /*******************************************************************************/ + case RFAL_NFC_STATE_LISTEN_TECHDETECT: + + if( platformTimerIsExpired( gNfcDev.discTmr ) ) + { + #if RFAL_FEATURE_LISTEN_MODE + rfalListenStop(); + #else + rfalFieldOff(); + #endif /* RFAL_FEATURE_LISTEN_MODE */ + + gNfcDev.state = RFAL_NFC_STATE_START_DISCOVERY; /* Restart the discovery loop */ + break; + } + + #if RFAL_FEATURE_LISTEN_MODE + err = rfalListenStart( gNfcDev.lmMask, &gNfcDev.disc.lmConfigPA, NULL, &gNfcDev.disc.lmConfigPF, (uint8_t*)&gNfcDev.rxBuf.rfBuf, sizeof(gNfcDev.rxBuf.rfBuf), &gNfcDev.rxLen ); + if( err == ERR_NONE ) + { + gNfcDev.state = RFAL_NFC_STATE_LISTEN_COLAVOIDANCE; /* Wait for listen mode to be activated */ + } + break; + + + /*******************************************************************************/ + case RFAL_NFC_STATE_LISTEN_COLAVOIDANCE: + + if( platformTimerIsExpired( gNfcDev.discTmr ) ) /* Check if the total duration has been reached */ + { + rfalListenStop(); + gNfcDev.state = RFAL_NFC_STATE_START_DISCOVERY; /* Restart the discovery loop */ + break; + } + + /* Check for external field */ + if( rfalListenGetState( NULL, NULL ) >= RFAL_LM_STATE_IDLE ) + { + gNfcDev.state = RFAL_NFC_STATE_LISTEN_ACTIVATION; /* Wait for listen mode to be activated */ + } + break; + + + /*******************************************************************************/ + case RFAL_NFC_STATE_LISTEN_ACTIVATION: + case RFAL_NFC_STATE_LISTEN_SLEEP: + + err = rfalNfcListenActivation(); + if( err != ERR_BUSY ) + { + if( err == ERR_NONE ) + { + gNfcDev.activeDev = gNfcDev.devList; /* Assign the active device to be used further on */ + gNfcDev.devCnt++; + + gNfcDev.state = RFAL_NFC_STATE_ACTIVATED; /* Device has been properly activated */ + rfalNfcNfcNotify( gNfcDev.state ); /* Inform upper layer that a device has been activated */ + } + else + { + rfalListenStop(); + gNfcDev.state = RFAL_NFC_STATE_START_DISCOVERY; /* Restart the discovery loop */ + } + } + #endif /* RFAL_FEATURE_LISTEN_MODE */ + break; + + /*******************************************************************************/ + case RFAL_NFC_STATE_ACTIVATED: + case RFAL_NFC_STATE_POLL_SELECT: + case RFAL_NFC_STATE_DATAEXCHANGE_DONE: + default: + return; + } +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDataExchangeStart( uint8_t *txData, uint16_t txDataLen, uint8_t **rxData, uint16_t **rvdLen, uint32_t fwt ) +{ + ReturnCode err; + rfalTransceiveContext ctx; + + /*******************************************************************************/ + /* The Data Exchange is divided in two different moments, the trigger/Start of * + * the transfer followed by the check until its completion */ + if( (gNfcDev.state >= RFAL_NFC_STATE_ACTIVATED) && (gNfcDev.activeDev != NULL) ) + { + + /*******************************************************************************/ + /* In Listen mode is the Poller that initiates the communicatation */ + /* Assign output parameters and rfalNfcDataExchangeGetStatus will return */ + /* incoming data from Poller/Initiator */ + if( (gNfcDev.state == RFAL_NFC_STATE_ACTIVATED) && rfalNfcIsRemDevPoller( gNfcDev.activeDev->type ) ) + { + if( txDataLen > 0U ) + { + return ERR_WRONG_STATE; + } + + *rvdLen = (uint16_t*)&gNfcDev.rxLen; + *rxData = (uint8_t*)( (gNfcDev.activeDev->rfInterface == RFAL_NFC_INTERFACE_ISODEP) ? gNfcDev.rxBuf.isoDepBuf.inf : + ((gNfcDev.activeDev->rfInterface == RFAL_NFC_INTERFACE_NFCDEP) ? gNfcDev.rxBuf.nfcDepBuf.inf : gNfcDev.rxBuf.rfBuf) ); + return ERR_NONE; + } + + + /*******************************************************************************/ + switch( gNfcDev.activeDev->rfInterface ) /* Check which RF interface shall be used/has been activated */ + { + /*******************************************************************************/ + case RFAL_NFC_INTERFACE_RF: + + rfalCreateByteFlagsTxRxContext( ctx, (uint8_t*)txData, txDataLen, gNfcDev.rxBuf.rfBuf, sizeof(gNfcDev.rxBuf.rfBuf), &gNfcDev.rxLen, RFAL_TXRX_FLAGS_DEFAULT, fwt ); + *rxData = (uint8_t*)gNfcDev.rxBuf.rfBuf; + *rvdLen = (uint16_t*)&gNfcDev.rxLen; + err = rfalStartTransceive( &ctx ); + break; + + #if RFAL_FEATURE_ISO_DEP + /*******************************************************************************/ + case RFAL_NFC_INTERFACE_ISODEP: + { + rfalIsoDepTxRxParam isoDepTxRx; + + if( txDataLen > 0U ) + { + ST_MEMCPY( (uint8_t*)gNfcDev.txBuf.isoDepBuf.inf, txData, txDataLen ); + } + + isoDepTxRx.DID = RFAL_ISODEP_NO_DID; + isoDepTxRx.ourFSx = RFAL_ISODEP_FSX_KEEP; + isoDepTxRx.FSx = gNfcDev.activeDev->proto.isoDep.info.FSx; + isoDepTxRx.dFWT = gNfcDev.activeDev->proto.isoDep.info.dFWT; + isoDepTxRx.FWT = gNfcDev.activeDev->proto.isoDep.info.FWT; + isoDepTxRx.txBuf = &gNfcDev.txBuf.isoDepBuf; + isoDepTxRx.txBufLen = txDataLen; + isoDepTxRx.isTxChaining = false; + isoDepTxRx.rxBuf = &gNfcDev.rxBuf.isoDepBuf; + isoDepTxRx.rxLen = &gNfcDev.rxLen; + isoDepTxRx.isRxChaining = &gNfcDev.isRxChaining; + *rxData = (uint8_t*)gNfcDev.rxBuf.isoDepBuf.inf; + *rvdLen = (uint16_t*)&gNfcDev.rxLen; + + /*******************************************************************************/ + /* Trigger a RFAL ISO-DEP Transceive */ + err = rfalIsoDepStartTransceive( isoDepTxRx ); + break; + } + #endif /* RFAL_FEATURE_ISO_DEP */ + + #if RFAL_FEATURE_NFC_DEP + /*******************************************************************************/ + case RFAL_NFC_INTERFACE_NFCDEP: + { + rfalNfcDepTxRxParam nfcDepTxRx; + + if( txDataLen > 0U) + { + ST_MEMCPY( (uint8_t*)gNfcDev.txBuf.nfcDepBuf.inf, txData, txDataLen ); + } + + nfcDepTxRx.DID = RFAL_NFCDEP_DID_KEEP; + nfcDepTxRx.FSx = rfalNfcDepLR2FS( (uint8_t)rfalNfcDepPP2LR( gNfcDev.activeDev->proto.nfcDep.activation.Target.ATR_RES.PPt ) ); + nfcDepTxRx.dFWT = gNfcDev.activeDev->proto.nfcDep.info.dFWT; + nfcDepTxRx.FWT = gNfcDev.activeDev->proto.nfcDep.info.FWT; + nfcDepTxRx.txBuf = &gNfcDev.txBuf.nfcDepBuf; + nfcDepTxRx.txBufLen = txDataLen; + nfcDepTxRx.isTxChaining = false; + nfcDepTxRx.rxBuf = &gNfcDev.rxBuf.nfcDepBuf; + nfcDepTxRx.rxLen = &gNfcDev.rxLen; + nfcDepTxRx.isRxChaining = &gNfcDev.isRxChaining; + *rxData = (uint8_t*)gNfcDev.rxBuf.nfcDepBuf.inf; + *rvdLen = (uint16_t*)&gNfcDev.rxLen; + + /*******************************************************************************/ + /* Trigger a RFAL NFC-DEP Transceive */ + err = rfalNfcDepStartTransceive( &nfcDepTxRx ); + break; + } + #endif /* RFAL_FEATURE_NFC_DEP */ + + /*******************************************************************************/ + default: + err = ERR_PARAM; + break; + } + + /* If a transceive has succesfully started flag Data Exchange as ongoing */ + if( err == ERR_NONE ) + { + gNfcDev.dataExErr = ERR_BUSY; + gNfcDev.state = RFAL_NFC_STATE_DATAEXCHANGE; + } + + return err; + } + + return ERR_WRONG_STATE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDataExchangeGetStatus( void ) +{ + /*******************************************************************************/ + /* Check if it's the first frame received in Listen mode */ + if( gNfcDev.state == RFAL_NFC_STATE_ACTIVATED ) + { + /* Continue data exchange as normal */ + gNfcDev.dataExErr = ERR_BUSY; + gNfcDev.state = RFAL_NFC_STATE_DATAEXCHANGE; + + /* Check if we performing in T3T CE */ + if( (gNfcDev.activeDev->type == RFAL_NFC_POLL_TYPE_NFCF) && (gNfcDev.activeDev->rfInterface == RFAL_NFC_INTERFACE_RF) ) + { + /* The first frame has been retrieved by rfalListenMode, flag data immediately */ + /* Can only call rfalGetTransceiveStatus() after starting a transceive with rfalStartTransceive */ + gNfcDev.dataExErr = ERR_NONE; + } + } + + + /*******************************************************************************/ + /* Check if we are in we have been placed to sleep, and return last error */ + if( gNfcDev.state == RFAL_NFC_STATE_LISTEN_SLEEP ) + { + return gNfcDev.dataExErr; /* ERR_SLEEP_REQ */ + } + + + /*******************************************************************************/ + /* Check if Data exchange has been started */ + if( (gNfcDev.state != RFAL_NFC_STATE_DATAEXCHANGE) && (gNfcDev.state != RFAL_NFC_STATE_DATAEXCHANGE_DONE) ) + { + return ERR_WRONG_STATE; + } + + /* Check if Data exchange is still ongoing */ + if( gNfcDev.dataExErr == ERR_BUSY ) + { + switch( gNfcDev.activeDev->rfInterface ) + { + /*******************************************************************************/ + case RFAL_NFC_INTERFACE_RF: + gNfcDev.dataExErr = rfalGetTransceiveStatus(); + break; + + #if RFAL_FEATURE_ISO_DEP + /*******************************************************************************/ + case RFAL_NFC_INTERFACE_ISODEP: + gNfcDev.dataExErr = rfalIsoDepGetTransceiveStatus(); + break; + #endif /* RFAL_FEATURE_ISO_DEP */ + + /*******************************************************************************/ + #if RFAL_FEATURE_NFC_DEP + case RFAL_NFC_INTERFACE_NFCDEP: + gNfcDev.dataExErr = rfalNfcDepGetTransceiveStatus(); + break; + #endif /* RFAL_FEATURE_NFC_DEP */ + + /*******************************************************************************/ + default: + gNfcDev.dataExErr = ERR_PARAM; + break; + } + + + #if RFAL_FEATURE_LISTEN_MODE + /*******************************************************************************/ + /* If a Sleep request has been received (Listen Mode) go to sleep immediately */ + if( gNfcDev.dataExErr == ERR_SLEEP_REQ ) + { + EXIT_ON_ERR( gNfcDev.dataExErr, rfalListenSleepStart( RFAL_LM_STATE_SLEEP_A, gNfcDev.rxBuf.rfBuf, sizeof(gNfcDev.rxBuf.rfBuf), &gNfcDev.rxLen ) ); + + /* If set Sleep was succesfull keep restore the Sleep request signal */ + gNfcDev.dataExErr = ERR_SLEEP_REQ; + } + #endif /* RFAL_FEATURE_LISTEN_MODE */ + + } + + return gNfcDev.dataExErr; +} + +/*! + ****************************************************************************** + * \brief Poller Technology Detection + * + * This method implements the Technology Detection / Poll for different + * device technologies. + * + * \return ERR_NONE : Operation completed with no error + * \return ERR_BUSY : Operation ongoing + * \return ERR_XXXX : Error occurred + * + ****************************************************************************** + */ +static ReturnCode rfalNfcPollTechDetetection( void ) +{ + ReturnCode err; + + err = ERR_NONE; + + /* Supress warning when specific RFAL features have been disabled */ + NO_WARNING(err); + + + /*******************************************************************************/ + /* AP2P Technology Detection */ + /*******************************************************************************/ + if( ((gNfcDev.disc.techs2Find & RFAL_NFC_POLL_TECH_AP2P) != 0U) && ((gNfcDev.techs2do & RFAL_NFC_POLL_TECH_AP2P) != 0U) ) + { + gNfcDev.techs2do &= ~RFAL_NFC_POLL_TECH_AP2P; + + #if RFAL_FEATURE_NFC_DEP + + EXIT_ON_ERR( err, rfalSetMode( RFAL_MODE_POLL_ACTIVE_P2P, gNfcDev.disc.ap2pBR, gNfcDev.disc.ap2pBR ) ); + rfalSetErrorHandling( RFAL_ERRORHANDLING_NFC ); + rfalSetFDTListen( RFAL_FDT_LISTEN_AP2P_POLLER ); + rfalSetFDTPoll( RFAL_TIMING_NONE ); + rfalSetGT( RFAL_GT_AP2P_ADJUSTED ); + EXIT_ON_ERR( err, rfalFieldOnAndStartGT() ); /* Turns the Field On and starts GT timer */ + + err = rfalNfcNfcDepActivate( gNfcDev.devList, RFAL_NFCDEP_COMM_ACTIVE, NULL, 0 );/* Poll for NFC-A devices */ + if( err == ERR_NONE ) + { + gNfcDev.techsFound |= RFAL_NFC_POLL_TECH_AP2P; + + gNfcDev.devList->type = RFAL_NFC_LISTEN_TYPE_AP2P; + gNfcDev.devList->rfInterface = RFAL_NFC_INTERFACE_NFCDEP; + gNfcDev.devCnt++; + + return ERR_NONE; + } + + rfalFieldOff(); + return ERR_BUSY; + + #endif /* RFAL_FEATURE_NFC_DEP */ + } + + + /*******************************************************************************/ + /* Passive NFC-A Technology Detection */ + /*******************************************************************************/ + if( ((gNfcDev.disc.techs2Find & RFAL_NFC_POLL_TECH_A) != 0U) && ((gNfcDev.techs2do & RFAL_NFC_POLL_TECH_A) != 0U) ) + { + gNfcDev.techs2do &= ~RFAL_NFC_POLL_TECH_A; + + #if RFAL_FEATURE_NFCA + { + rfalNfcaSensRes sensRes; + + EXIT_ON_ERR( err, rfalNfcaPollerInitialize() ); /* Initialize RFAL for NFC-A */ + EXIT_ON_ERR( err, rfalFieldOnAndStartGT() ); /* Turns the Field On and starts GT timer */ + + err = rfalNfcaPollerTechnologyDetection( gNfcDev.disc.compMode, &sensRes );/* Poll for NFC-A devices */ + if( err == ERR_NONE ) + { + gNfcDev.techsFound |= RFAL_NFC_POLL_TECH_A; + } + + return ERR_BUSY; + } + + #endif /* RFAL_FEATURE_NFCA */ + } + + + /*******************************************************************************/ + /* Passive NFC-B Technology Detection */ + /*******************************************************************************/ + if( ((gNfcDev.disc.techs2Find & RFAL_NFC_POLL_TECH_B) != 0U) && ((gNfcDev.techs2do & RFAL_NFC_POLL_TECH_B) != 0U) ) + { + gNfcDev.techs2do &= ~RFAL_NFC_POLL_TECH_B; + + #if RFAL_FEATURE_NFCB + { + rfalNfcbSensbRes sensbRes; + uint8_t sensbResLen; + + EXIT_ON_ERR( err, rfalNfcbPollerInitialize() ); /* Initialize RFAL for NFC-B */ + EXIT_ON_ERR( err, rfalFieldOnAndStartGT() ); /* As field is already On only starts GT timer */ + + err = rfalNfcbPollerTechnologyDetection( gNfcDev.disc.compMode, &sensbRes, &sensbResLen ); /* Poll for NFC-B devices */ + if( err == ERR_NONE ) + { + gNfcDev.techsFound |= RFAL_NFC_POLL_TECH_B; + } + + return ERR_BUSY; + } + + #endif /* RFAL_FEATURE_NFCB */ + } + + /*******************************************************************************/ + /* Passive NFC-F Technology Detection */ + /*******************************************************************************/ + if( ((gNfcDev.disc.techs2Find & RFAL_NFC_POLL_TECH_F) != 0U) && ((gNfcDev.techs2do & RFAL_NFC_POLL_TECH_F) != 0U) ) + { + gNfcDev.techs2do &= ~RFAL_NFC_POLL_TECH_F; + + #if RFAL_FEATURE_NFCF + + EXIT_ON_ERR( err, rfalNfcfPollerInitialize( gNfcDev.disc.nfcfBR ) ); /* Initialize RFAL for NFC-F */ + EXIT_ON_ERR( err, rfalFieldOnAndStartGT() ); /* As field is already On only starts GT timer */ + + err = rfalNfcfPollerCheckPresence(); /* Poll for NFC-F devices */ + if( err == ERR_NONE ) + { + gNfcDev.techsFound |= RFAL_NFC_POLL_TECH_F; + } + + return ERR_BUSY; + + #endif /* RFAL_FEATURE_NFCF */ + } + + + /*******************************************************************************/ + /* Passive NFC-V Technology Detection */ + /*******************************************************************************/ + if( ((gNfcDev.disc.techs2Find & RFAL_NFC_POLL_TECH_V) != 0U) && ((gNfcDev.techs2do & RFAL_NFC_POLL_TECH_V) != 0U) ) + { + gNfcDev.techs2do &= ~RFAL_NFC_POLL_TECH_V; + + #if RFAL_FEATURE_NFCV + { + rfalNfcvInventoryRes invRes; + + EXIT_ON_ERR( err, rfalNfcvPollerInitialize() ); /* Initialize RFAL for NFC-V */ + EXIT_ON_ERR( err, rfalFieldOnAndStartGT() ); /* As field is already On only starts GT timer */ + + err = rfalNfcvPollerCheckPresence( &invRes ); /* Poll for NFC-V devices */ + if( err == ERR_NONE ) + { + gNfcDev.techsFound |= RFAL_NFC_POLL_TECH_V; + } + + return ERR_BUSY; + } + + #endif /* RFAL_FEATURE_NFCV */ + } + + + /*******************************************************************************/ + /* Passive Proprietary Technology ST25TB */ + /*******************************************************************************/ + if( ((gNfcDev.disc.techs2Find & RFAL_NFC_POLL_TECH_ST25TB) != 0U) && ((gNfcDev.techs2do & RFAL_NFC_POLL_TECH_ST25TB) != 0U) ) + { + gNfcDev.techs2do &= ~RFAL_NFC_POLL_TECH_ST25TB; + + #if RFAL_FEATURE_ST25TB + + EXIT_ON_ERR( err, rfalSt25tbPollerInitialize() ); /* Initialize RFAL for NFC-V */ + EXIT_ON_ERR( err, rfalFieldOnAndStartGT() ); /* As field is already On only starts GT timer */ + + err = rfalSt25tbPollerCheckPresence( NULL ); /* Poll for ST25TB devices */ + if( err == ERR_NONE ) + { + gNfcDev.techsFound |= RFAL_NFC_POLL_TECH_ST25TB; + } + + #endif /* RFAL_FEATURE_ST25TB */ + } + + return ERR_NONE; +} + +/*! + ****************************************************************************** + * \brief Poller Collision Resolution + * + * This method implements the Collision Resolution on all technologies that + * have been detected before. + * + * \return ERR_NONE : Operation completed with no error + * \return ERR_BUSY : Operation ongoing + * \return ERR_XXXX : Error occurred + * + ****************************************************************************** + */ +static ReturnCode rfalNfcPollCollResolution( void ) +{ + uint8_t i; + uint8_t devCnt; + ReturnCode err; + + err = ERR_NONE; + devCnt = 0; + i = 0; + + /* Supress warning when specific RFAL features have been disabled */ + NO_WARNING(err); + NO_WARNING(devCnt); + NO_WARNING(i); + + /* Check if device limit has been reached */ + if( gNfcDev.devCnt >= gNfcDev.disc.devLimit ) + { + return ERR_NONE; + } + + /*******************************************************************************/ + /* NFC-A Collision Resolution */ + /*******************************************************************************/ +#if RFAL_FEATURE_NFCA + if( ((gNfcDev.techsFound & RFAL_NFC_POLL_TECH_A) != 0U) && ((gNfcDev.techs2do & RFAL_NFC_POLL_TECH_A) != 0U) ) /* If a NFC-A device was found/detected, perform Collision Resolution */ + { + rfalNfcaListenDevice nfcaDevList[RFAL_NFC_MAX_DEVICES]; + + gNfcDev.techs2do &= ~RFAL_NFC_POLL_TECH_A; + + EXIT_ON_ERR( err, rfalNfcaPollerInitialize()); /* Initialize RFAL for NFC-A */ + EXIT_ON_ERR( err, rfalFieldOnAndStartGT() ); /* Ensure GT again as other technologies have also been polled */ + + err = rfalNfcaPollerFullCollisionResolution( gNfcDev.disc.compMode, (gNfcDev.disc.devLimit - gNfcDev.devCnt), nfcaDevList, &devCnt ); + if( (err == ERR_NONE) && (devCnt != 0U) ) + { + for( i=0; i gNfcDev.devCnt ) + { + return ERR_WRONG_STATE; + } + + switch( gNfcDev.devList[devIt].type ) + { + /*******************************************************************************/ + /* AP2P Activation */ + /*******************************************************************************/ + #if RFAL_FEATURE_NFC_DEP + case RFAL_NFC_LISTEN_TYPE_AP2P: + /* Activation has already been perfomed (ATR_REQ) */ + + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].proto.nfcDep.activation.Target.ATR_RES.NFCID3; + gNfcDev.devList[devIt].nfcidLen = RFAL_NFCDEP_NFCID3_LEN; + break; + #endif /* RFAL_FEATURE_NFC_DEP */ + + + /*******************************************************************************/ + /* Passive NFC-A Activation */ + /*******************************************************************************/ + #if RFAL_FEATURE_NFCA + case RFAL_NFC_LISTEN_TYPE_NFCA: + + rfalNfcaPollerInitialize(); + if( gNfcDev.devList[devIt].dev.nfca.isSleep ) /* Check if desired device is in Sleep */ + { + rfalNfcaSensRes sensRes; + rfalNfcaSelRes selRes; + + EXIT_ON_ERR( err, rfalNfcaPollerCheckPresence( RFAL_14443A_SHORTFRAME_CMD_WUPA, &sensRes ) ); /* Wake up all cards */ + EXIT_ON_ERR( err, rfalNfcaPollerSelect( gNfcDev.devList[devIt].dev.nfca.nfcId1, gNfcDev.devList[devIt].dev.nfca.nfcId1Len, &selRes ) ); /* Select specific device */ + } + + /* Set NFCID */ + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].dev.nfca.nfcId1; + gNfcDev.devList[devIt].nfcidLen = gNfcDev.devList[devIt].dev.nfca.nfcId1Len; + + /*******************************************************************************/ + /* Perform protocol specific activation */ + switch( gNfcDev.devList[devIt].dev.nfca.type ) + { + /*******************************************************************************/ + case RFAL_NFCA_T1T: + + /* No further activation needed for T1T (RID already performed) */ + + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].dev.nfca.ridRes.uid; + gNfcDev.devList[devIt].nfcidLen = RFAL_T1T_UID_LEN; + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_RF; + break; + + case RFAL_NFCA_T2T: + + /* No further activation needed for a T2T */ + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_RF; + break; + + + /*******************************************************************************/ + case RFAL_NFCA_T4T: /* Device supports ISO-DEP */ + + #if RFAL_FEATURE_ISO_DEP_POLL + /* Perform ISO-DEP (ISO14443-4) activation: RATS and PPS if supported */ + rfalIsoDepInitialize(); + EXIT_ON_ERR( err, rfalIsoDepPollAHandleActivation( (rfalIsoDepFSxI)RFAL_ISODEP_FSDI_DEFAULT, RFAL_ISODEP_NO_DID, RFAL_BR_424, &gNfcDev.devList[devIt].proto.isoDep ) ); + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_ISODEP; /* NFC-A T4T device activated */ + #else + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_RF; /* No ISO-DEP supported activate using RF interface */ + #endif /* RFAL_FEATURE_ISO_DEP_POLL */ + break; + + + + /*******************************************************************************/ + case RFAL_NFCA_T4T_NFCDEP: /* Device supports both T4T and NFC-DEP */ + case RFAL_NFCA_NFCDEP: /* Device supports NFC-DEP */ + + #if RFAL_FEATURE_NFC_DEP + /* Perform NFC-DEP (P2P) activation: ATR and PSL if supported */ + EXIT_ON_ERR( err, rfalNfcNfcDepActivate( &gNfcDev.devList[devIt], RFAL_NFCDEP_COMM_PASSIVE, NULL, 0 ) ); + + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].proto.nfcDep.activation.Target.ATR_RES.NFCID3; + gNfcDev.devList[devIt].nfcidLen = RFAL_NFCDEP_NFCID3_LEN; + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_NFCDEP; /* NFC-A P2P device activated */ + #else + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_RF; /* No NFC-DEP supported activate using RF interface */ + #endif /* RFAL_FEATURE_NFC_DEP */ + break; + + /*******************************************************************************/ + default: + return ERR_WRONG_STATE; + } + break; + #endif /* RFAL_FEATURE_NFCA */ + + + /*******************************************************************************/ + /* Passive NFC-B Activation */ + /*******************************************************************************/ + #if RFAL_FEATURE_NFCB + case RFAL_NFC_LISTEN_TYPE_NFCB: + + rfalNfcbPollerInitialize(); + if( gNfcDev.devList[devIt].dev.nfcb.isSleep ) /* Check if desired device is in Sleep */ + { + rfalNfcbSensbRes sensbRes; + uint8_t sensbResLen; + + /* Wake up all cards. SENSB_RES may return collision but the NFCID0 is available to explicitly select NFC-B card via ATTRIB; so error will be ignored here */ + rfalNfcbPollerCheckPresence( RFAL_NFCB_SENS_CMD_ALLB_REQ, RFAL_NFCB_SLOT_NUM_1, &sensbRes, &sensbResLen ); + } + + /* Set NFCID */ + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].dev.nfcb.sensbRes.nfcid0; + gNfcDev.devList[devIt].nfcidLen = RFAL_NFCB_NFCID0_LEN; + + #if RFAL_FEATURE_ISO_DEP_POLL + /* Check if device supports ISO-DEP (ISO14443-4) */ + if( (gNfcDev.devList[devIt].dev.nfcb.sensbRes.protInfo.FsciProType & RFAL_NFCB_SENSB_RES_PROTO_ISO_MASK) != 0U ) + { + rfalIsoDepInitialize(); + /* Perform ISO-DEP (ISO14443-4) activation: RATS and PPS if supported */ + EXIT_ON_ERR( err, rfalIsoDepPollBHandleActivation( (rfalIsoDepFSxI)RFAL_ISODEP_FSDI_DEFAULT, RFAL_ISODEP_NO_DID, RFAL_BR_424, 0x00, &gNfcDev.devList[devIt].dev.nfcb, NULL, 0, &gNfcDev.devList[devIt].proto.isoDep ) ); + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_ISODEP; /* NFC-B T4T device activated */ + break; + } + #endif /* RFAL_FEATURE_ISO_DEP_POLL */ + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_RF; /* NFC-B device activated */ + break; + + #endif /* RFAL_FEATURE_NFCB */ + + + /*******************************************************************************/ + /* Passive NFC-F Activation */ + /*******************************************************************************/ + #if RFAL_FEATURE_NFCF + case RFAL_NFC_LISTEN_TYPE_NFCF: + + rfalNfcfPollerInitialize( gNfcDev.disc.nfcfBR ); + + #if RFAL_FEATURE_NFC_DEP + if( rfalNfcfIsNfcDepSupported( &gNfcDev.devList[devIt].dev.nfcf ) ) + { + /* Perform NFC-DEP (P2P) activation: ATR and PSL if supported */ + EXIT_ON_ERR( err, rfalNfcNfcDepActivate( &gNfcDev.devList[devIt], RFAL_NFCDEP_COMM_PASSIVE, NULL, 0 ) ); + + /* Set NFCID */ + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].proto.nfcDep.activation.Target.ATR_RES.NFCID3; + gNfcDev.devList[devIt].nfcidLen = RFAL_NFCDEP_NFCID3_LEN; + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_NFCDEP; /* NFC-F P2P device activated */ + break; + } + #endif /* RFAL_FEATURE_NFC_DEP */ + + /* Set NFCID */ + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].dev.nfcf.sensfRes.NFCID2; + gNfcDev.devList[devIt].nfcidLen = RFAL_NFCF_NFCID2_LEN; + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_RF; /* NFC-F T3T device activated */ + break; + #endif /* RFAL_FEATURE_NFCF */ + + + /*******************************************************************************/ + /* Passive NFC-V Activation */ + /*******************************************************************************/ + #if RFAL_FEATURE_NFCV + case RFAL_NFC_LISTEN_TYPE_NFCV: + + rfalNfcvPollerInitialize(); + + /* No specific activation needed for a T5T */ + + /* Set NFCID */ + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].dev.nfcv.InvRes.UID; + gNfcDev.devList[devIt].nfcidLen = RFAL_NFCV_UID_LEN; + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_RF; /* NFC-V T5T device activated */ + break; + #endif /* RFAL_FEATURE_NFCV */ + + + /*******************************************************************************/ + /* Passive ST25TB Activation */ + /*******************************************************************************/ + #if RFAL_FEATURE_ST25TB + case RFAL_NFC_LISTEN_TYPE_ST25TB: + + rfalSt25tbPollerInitialize(); + + /* No specific activation needed for a ST25TB */ + + /* Set NFCID */ + gNfcDev.devList[devIt].nfcid = gNfcDev.devList[devIt].dev.st25tb.UID; + gNfcDev.devList[devIt].nfcidLen = RFAL_ST25TB_UID_LEN; + + gNfcDev.devList[devIt].rfInterface = RFAL_NFC_INTERFACE_RF; /* ST25TB device activated */ + break; + #endif /* RFAL_FEATURE_ST25TB */ + + /*******************************************************************************/ + default: + return ERR_WRONG_STATE; + } + + gNfcDev.activeDev = &gNfcDev.devList[devIt]; /* Assign active device to be used further on */ + return ERR_NONE; +} + + +/*! + ****************************************************************************** + * \brief Listener Activation + * + * This method handles the listen mode Activation according to the different + * protocols the Reader/Initiator performs + * + * \return ERR_NONE : Operation completed with no error + * \return ERR_BUSY : Operation ongoing + * \return ERR_PROTO : Unexpected frame received + * \return ERR_XXXX : Error occurred + * + ****************************************************************************** + */ +#if RFAL_FEATURE_LISTEN_MODE +static ReturnCode rfalNfcListenActivation( void ) +{ + bool isDataRcvd; + uint8_t hdrLen; + ReturnCode ret; + rfalLmState lmSt; + rfalBitRate bitRate; + + lmSt = rfalListenGetState( &isDataRcvd, &bitRate ); + switch(lmSt) + { + /*******************************************************************************/ + case RFAL_LM_STATE_ACTIVE_A: /* NFC-A CE activation */ + case RFAL_LM_STATE_ACTIVE_Ax: + + if( isDataRcvd ) /* Check if Reader/Initator has sent some data */ + { + /* Set the header length in NFC-A */ + hdrLen = (RFAL_NFCDEP_SB_LEN + RFAL_NFCDEP_LEN_LEN); + + NO_WARNING(hdrLen); /* Supress warning if feature switch is disabled */ + + /* Check if received data is a Sleep request */ + if( rfalNfcaListenerIsSleepReq( gNfcDev.rxBuf.rfBuf, rfalConvBitsToBytes(gNfcDev.rxLen)) ) /* Check if received data is a SLP_REQ */ + { + /* Set the Listen Mode in Sleep state */ + EXIT_ON_ERR( ret, rfalListenSleepStart( RFAL_LM_STATE_SLEEP_A, gNfcDev.rxBuf.rfBuf, sizeof(gNfcDev.rxBuf.rfBuf), &gNfcDev.rxLen ) ); + } + + #if RFAL_FEATURE_ISO_DEP_LISTEN + /* Check if received data is a valid RATS */ + else if( rfalIsoDepIsRats( gNfcDev.rxBuf.rfBuf, (uint8_t)rfalConvBitsToBytes(gNfcDev.rxLen) ) ) + { + rfalIsoDepAtsParam atsParam; + rfalIsoDepListenActvParam rxParam; + + /* Set ATS parameters */ + atsParam.fsci = (uint8_t)RFAL_ISODEP_DEFAULT_FSCI; + atsParam.fwi = RFAL_ISODEP_DEFAULT_FWI; + atsParam.sfgi = RFAL_ISODEP_DEFAULT_SFGI; + atsParam.didSupport = false; + atsParam.ta = RFAL_ISODEP_ATS_TA_SAME_D; + atsParam.hb = NULL; + atsParam.hbLen = 0; + + /* Set Rx parameters */ + rxParam.rxBuf = (rfalIsoDepBufFormat*) &gNfcDev.rxBuf.isoDepBuf; + rxParam.rxLen = &gNfcDev.rxLen; + rxParam.isoDepDev = &gNfcDev.devList->proto.isoDep; + rxParam.isRxChaining = &gNfcDev.isRxChaining; + + rfalListenSetState( RFAL_LM_STATE_CARDEMU_4A ); /* Set next state CE T4T */ + rfalIsoDepInitialize(); /* Initialize ISO-DEP layer to handle ISO14443-a activation / RATS */ + + /* Set ISO-DEP layer to digest RATS and handle activation */ + EXIT_ON_ERR( ret, rfalIsoDepListenStartActivation( &atsParam, NULL, gNfcDev.rxBuf.rfBuf, gNfcDev.rxLen, rxParam ) ); + } + #endif /* RFAL_FEATURE_ISO_DEP_LISTEN */ + + #if RFAL_FEATURE_NFC_DEP + /* Check if received data is a valid ATR_REQ */ + else if( rfalNfcDepIsAtrReq( &gNfcDev.rxBuf.rfBuf[hdrLen], (rfalConvBitsToBytes(gNfcDev.rxLen) - hdrLen), gNfcDev.devList->nfcid ) ) + { + gNfcDev.devList->type = RFAL_NFC_POLL_TYPE_NFCA; + EXIT_ON_ERR( ret, rfalNfcNfcDepActivate( gNfcDev.devList, RFAL_NFCDEP_COMM_PASSIVE, &gNfcDev.rxBuf.rfBuf[hdrLen], (rfalConvBitsToBytes(gNfcDev.rxLen) - hdrLen) ) ); + } + #endif /* RFAL_FEATURE_NFC_DEP */ + + else + { + return ERR_PROTO; + } + } + return ERR_BUSY; + + #if RFAL_FEATURE_ISO_DEP_LISTEN + /*******************************************************************************/ + case RFAL_LM_STATE_CARDEMU_4A: /* T4T ISO-DEP activation */ + + ret = rfalIsoDepListenGetActivationStatus(); + if( ret == ERR_NONE ) + { + gNfcDev.devList->type = RFAL_NFC_POLL_TYPE_NFCA; + gNfcDev.devList->rfInterface = RFAL_NFC_INTERFACE_ISODEP; + gNfcDev.devList->nfcid = NULL; + gNfcDev.devList->nfcidLen = 0; + } + return ret; + #endif /* RFAL_FEATURE_ISO_DEP_LISTEN */ + + /*******************************************************************************/ + case RFAL_LM_STATE_READY_F: /* NFC-F CE activation */ + + if( isDataRcvd ) /* Wait for the first received data */ + { + #if RFAL_FEATURE_NFC_DEP + /* Set the header length in NFC-F */ + hdrLen = RFAL_NFCDEP_LEN_LEN; + + if( rfalNfcDepIsAtrReq( &gNfcDev.rxBuf.rfBuf[hdrLen], (rfalConvBitsToBytes(gNfcDev.rxLen) - hdrLen), gNfcDev.devList->nfcid ) ) + { + gNfcDev.devList->type = RFAL_NFC_POLL_TYPE_NFCF; + EXIT_ON_ERR( ret, rfalNfcNfcDepActivate( gNfcDev.devList, RFAL_NFCDEP_COMM_PASSIVE, &gNfcDev.rxBuf.rfBuf[hdrLen], (rfalConvBitsToBytes(gNfcDev.rxLen) - hdrLen) ) ); + } + else + #endif /* RFAL_FEATURE_NFC_DEP */ + { + rfalListenSetState( RFAL_LM_STATE_CARDEMU_3 ); /* First data already received - set T3T CE */ + } + } + return ERR_BUSY; + + /*******************************************************************************/ + case RFAL_LM_STATE_CARDEMU_3: /* T3T activated */ + + gNfcDev.devList->type = RFAL_NFC_POLL_TYPE_NFCF; + gNfcDev.devList->rfInterface = RFAL_NFC_INTERFACE_RF; + gNfcDev.devList->nfcid = NULL; + gNfcDev.devList->nfcidLen = 0; + + return ERR_NONE; + + #if RFAL_FEATURE_NFC_DEP + /*******************************************************************************/ + case RFAL_LM_STATE_TARGET_A: /* NFC-DEP activation */ + case RFAL_LM_STATE_TARGET_F: + + ret = rfalNfcDepListenGetActivationStatus(); + if( ret == ERR_NONE ) + { + gNfcDev.devList->rfInterface = RFAL_NFC_INTERFACE_NFCDEP; + gNfcDev.devList->nfcidLen = RFAL_NFCDEP_NFCID3_LEN; + } + return ret; + #endif /* RFAL_FEATURE_NFC_DEP */ + + /*******************************************************************************/ + case RFAL_LM_STATE_IDLE: /* AP2P activation */ + if( isDataRcvd ) /* Check if Reader/Initator has sent some data */ + { + + if( (gNfcDev.lmMask & RFAL_LM_MASK_ACTIVE_P2P) != 0U ) /* Check if AP2P is enabled */ + { + + #if RFAL_FEATURE_NFC_DEP + /* Calculate the header length in NFC-A or NFC-F mode*/ + hdrLen = ( (bitRate == RFAL_BR_106) ? (RFAL_NFCDEP_SB_LEN + RFAL_NFCDEP_LEN_LEN) : RFAL_NFCDEP_LEN_LEN ); + + if( rfalNfcDepIsAtrReq( &gNfcDev.rxBuf.rfBuf[hdrLen], (rfalConvBitsToBytes(gNfcDev.rxLen) - hdrLen), NULL) ) + { + gNfcDev.devList->type = RFAL_NFC_POLL_TYPE_AP2P; + EXIT_ON_ERR( ret, rfalNfcNfcDepActivate( gNfcDev.devList, RFAL_NFCDEP_COMM_ACTIVE, &gNfcDev.rxBuf.rfBuf[hdrLen], (rfalConvBitsToBytes(gNfcDev.rxLen) - hdrLen) ) ); + } + else + #endif /* RFAL_FEATURE_NFC_DEP */ + { + return ERR_PROTO; + } + } + } + return ERR_BUSY; + + /*******************************************************************************/ + case RFAL_LM_STATE_READY_A: + case RFAL_LM_STATE_READY_Ax: + case RFAL_LM_STATE_SLEEP_A: + case RFAL_LM_STATE_SLEEP_AF: + return ERR_BUSY; + + /*******************************************************************************/ + case RFAL_LM_STATE_POWER_OFF: + return ERR_LINK_LOSS; + + default: /* Wait for activation */ + break; + } + + return ERR_INTERNAL; +} +#endif /* RFAL_FEATURE_LISTEN_MODE */ + + +/*! + ****************************************************************************** + * \brief Poller NFC DEP Activate + * + * This method performs NFC-DEP Activation + * + * \param[in] device : device info + * \param[in] commMode : communication mode (Passive/Active) + * \param[in] atrReq : received ATR_REQ + * \param[in] atrReqLen : received ATR_REQ size + * + * \return ERR_NONE : Operation completed with no error + * \return ERR_BUSY : Operation ongoing + * \return ERR_XXXX : Error occurred + * + ****************************************************************************** + */ +#if RFAL_FEATURE_NFC_DEP +static ReturnCode rfalNfcNfcDepActivate( rfalNfcDevice *device, rfalNfcDepCommMode commMode, const uint8_t *atrReq, uint16_t atrReqLen ) +{ + rfalNfcDepAtrParam initParam; + + /* If we are in Poll mode */ + if( rfalNfcIsRemDevListener( device->type ) ) + { + /*******************************************************************************/ + /* If Passive F use the NFCID2 retrieved from SENSF */ + if( device->type == RFAL_NFC_LISTEN_TYPE_NFCF ) + { + initParam.nfcid = device->dev.nfcf.sensfRes.NFCID2; + initParam.nfcidLen = RFAL_NFCF_NFCID2_LEN; + } + else + { + initParam.nfcid = gNfcDev.disc.nfcid3; + initParam.nfcidLen = RFAL_NFCDEP_NFCID3_LEN; + } + + initParam.BS = RFAL_NFCDEP_Bx_NO_HIGH_BR; + initParam.BitRate = RFAL_NFCDEP_Bx_NO_HIGH_BR; + initParam.DID = RFAL_NFCDEP_DID_NO; + initParam.NAD = RFAL_NFCDEP_NAD_NO; + initParam.LR = RFAL_NFCDEP_LR_254; + initParam.GB = gNfcDev.disc.GB; + initParam.GBLen = gNfcDev.disc.GBLen; + initParam.commMode = commMode; + initParam.operParam = (RFAL_NFCDEP_OPER_FULL_MI_EN | RFAL_NFCDEP_OPER_EMPTY_DEP_DIS | RFAL_NFCDEP_OPER_ATN_EN | RFAL_NFCDEP_OPER_RTOX_REQ_EN); + + rfalNfcDepInitialize(); + /* Perform NFC-DEP (P2P) activation: ATR and PSL if supported */ + return rfalNfcDepInitiatorHandleActivation( &initParam, RFAL_BR_424, &device->proto.nfcDep ); + } + + /* If we are in Listen mode */ +#if RFAL_FEATURE_LISTEN_MODE + else if( rfalNfcIsRemDevPoller( device->type ) ) + { + rfalNfcDepListenActvParam actvParams; + rfalNfcDepTargetParam targetParam; + + ST_MEMCPY(targetParam.nfcid3, (uint8_t*)gNfcDev.disc.nfcid3, RFAL_NFCDEP_NFCID3_LEN); + targetParam.bst = RFAL_NFCDEP_Bx_NO_HIGH_BR; + targetParam.brt = RFAL_NFCDEP_Bx_NO_HIGH_BR; + targetParam.to = RFAL_NFCDEP_WT_TRG_MAX; + targetParam.ppt = rfalNfcDepLR2PP(RFAL_NFCDEP_LR_254); + targetParam.GBtLen = 0; + targetParam.operParam = (RFAL_NFCDEP_OPER_FULL_MI_EN | RFAL_NFCDEP_OPER_EMPTY_DEP_DIS | RFAL_NFCDEP_OPER_ATN_EN | RFAL_NFCDEP_OPER_RTOX_REQ_EN); + targetParam.commMode = commMode; + + + /* Set activation buffer (including header) for NFC-DEP */ + actvParams.rxBuf = &gNfcDev.rxBuf.nfcDepBuf; + actvParams.rxLen = &gNfcDev.rxLen; + actvParams.isRxChaining = &gNfcDev.isRxChaining; + actvParams.nfcDepDev = &gNfcDev.devList->proto.nfcDep; + + rfalListenSetState( ((device->type == RFAL_NFC_POLL_TYPE_NFCA) ? RFAL_LM_STATE_TARGET_A : RFAL_LM_STATE_TARGET_F) ); + + rfalNfcDepInitialize(); + /* Perform NFC-DEP (P2P) activation: send ATR_RES and handle activation */ + return rfalNfcDepListenStartActivation( &targetParam, atrReq, atrReqLen, actvParams ); + } +#endif /* RFAL_FEATURE_LISTEN_MODE */ + + else + { + return ERR_INTERNAL; + } +} +#endif /* RFAL_FEATURE_NFC_DEP */ + + +/*! + ****************************************************************************** + * \brief Poller NFC Deactivate + * + * This method Deactivates the device if a deactivation procedure exists + * + * \return ERR_NONE : Operation completed with no error + * \return ERR_BUSY : Operation ongoing + * \return ERR_XXXX : Error occurred + * + ****************************************************************************** + */ +static ReturnCode rfalNfcDeactivation( void ) +{ + /* Check if a device has been activated */ + if( gNfcDev.activeDev != NULL ) + { + switch( gNfcDev.activeDev->rfInterface ) + { + /*******************************************************************************/ + case RFAL_NFC_INTERFACE_RF: + break; /* No specific deactivation to be performed */ + + /*******************************************************************************/ + #if RFAL_FEATURE_ISO_DEP_POLL + case RFAL_NFC_INTERFACE_ISODEP: + rfalIsoDepDeselect(); /* Send a Deselect to device */ + break; + #endif /* RFAL_FEATURE_ISO_DEP_POLL */ + + /*******************************************************************************/ + #if RFAL_FEATURE_NFC_DEP + case RFAL_NFC_INTERFACE_NFCDEP: + rfalNfcDepRLS(); /* Send a Release to device */ + break; + #endif /* RFAL_FEATURE_NFC_DEP */ + + default: + return ERR_REQUEST; + } + } + + #if RFAL_FEATURE_WAKEUP_MODE + rfalWakeUpModeStop(); + #endif /* RFAL_FEATURE_WAKEUP_MODE */ + + #if RFAL_FEATURE_LISTEN_MODE + rfalListenStop(); + #else + rfalFieldOff(); + #endif + + gNfcDev.activeDev = NULL; + return ERR_NONE; +} diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_nfcDep.c b/Software/fab-reader2-c/components/rfal/Src/rfal_nfcDep.c new file mode 100644 index 0000000..c92c877 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_nfcDep.c @@ -0,0 +1,2530 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: NFCC firmware + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfcDep.c + * + * \author Gustavo Patricio + * + * \brief Implementation of NFC-DEP protocol + * + * NFC-DEP is also known as NFCIP - Near Field Communication + * Interface and Protocol + * + * This implementation was based on the following specs: + * - NFC Forum Digital 1.1 + * - ECMA 340 3rd Edition 2013 + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_nfcDep.h" +#include "rfal_nfcf.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_NFC_DEP + #define RFAL_FEATURE_NFC_DEP false /* NFC-DEP module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_NFC_DEP + +/* + ****************************************************************************** + * DEFINES + ****************************************************************************** + */ +#define NFCIP_ATR_RETRY_MAX 2U /*!< Max consecutive retrys of an ATR REQ with transm error*/ + +#define NFCIP_PSLPAY_LEN (2U) /*!< PSL Payload length (BRS + FSL) */ +#define NFCIP_PSLREQ_LEN (3U + RFAL_NFCDEP_LEN_LEN) /*!< PSL REQ length (incl LEN) */ +#define NFCIP_PSLRES_LEN (3U + RFAL_NFCDEP_LEN_LEN) /*!< PSL RES length (incl LEN) */ + +#define NFCIP_ATRREQ_BUF_LEN (RFAL_NFCDEP_ATRREQ_MAX_LEN + RFAL_NFCDEP_LEN_LEN) /*!< ATR REQ max length (incl LEN) */ +#define NFCIP_ATRRES_BUF_LEN (RFAL_NFCDEP_ATRRES_MAX_LEN + RFAL_NFCDEP_LEN_LEN) /*!< ATR RES max length (incl LEN) */ + +#define NFCIP_RLSREQ_LEN (3U + RFAL_NFCDEP_LEN_LEN) /*!< RLS REQ length (incl LEN) */ +#define NFCIP_RLSRES_LEN (3U + RFAL_NFCDEP_LEN_LEN) /*!< RSL RES length (incl LEN) */ +#define NFCIP_RLSRES_MIN (2U + RFAL_NFCDEP_LEN_LEN) /*!< Minimum length for a RLS RES (incl LEN) */ + +#define NFCIP_DSLREQ_LEN (3U + RFAL_NFCDEP_LEN_LEN) /*!< DSL REQ length (incl LEN) */ +#define NFCIP_DSLRES_LEN (3U + RFAL_NFCDEP_LEN_LEN) /*!< DSL RES length (incl LEN) */ +#define NFCIP_DSLRES_MIN (2U + RFAL_NFCDEP_LEN_LEN) /*!< Minimum length for a DSL RES (incl LEN) */ + +#define NFCIP_DSLRES_MAX_LEN (3U + RFAL_NFCDEP_LEN_LEN) /*!< Maximum length for a DSL RES (incl LEN) */ +#define NFCIP_RLSRES_MAX_LEN (3U + RFAL_NFCDEP_LEN_LEN) /*!< Minimum length for a RLS RES (incl LEN) */ +#define NFCIP_TARGET_RES_MAX ( MAX( NFCIP_RLSRES_MAX_LEN, NFCIP_DSLRES_MAX_LEN) ) /*!< Max target control res length */ + + + +#define NFCIP_NO_FWT RFAL_FWT_NONE /*!< No FWT value - Target Mode */ +#define NFCIP_INIT_MIN_RTOX 1U /*!< Minimum RTOX value Digital 1.0 14.8.4.1 */ +#define NFCIP_INIT_MAX_RTOX 59U /*!< Maximum RTOX value Digital 1.0 14.8.4.1 */ + +#define NFCIP_TARG_MIN_RTOX 1U /*!< Minimum target RTOX value Digital 1.0 14.8.4.1 */ +#define NFCIP_TARG_MAX_RTOX 59U /*!< Maximum target RTOX value Digital 1.0 14.8.4.1 */ + +#define NFCIP_TRECOV 1280U /*!< Digital 1.0 A.10 Trecov */ + +#define NFCIP_TIMEOUT_ADJUSTMENT 512U /*!< Timeout Adjustment to compensate timing from end of Tx to end of frame */ +#define NFCIP_RWT_ACTIVATION (0x1000001U + NFCIP_TIMEOUT_ADJUSTMENT) /*!< Digital 2.0 B.10 RWT ACTIVATION 2^24 + RWT Delta + Adjustment*/ +#define NFCIP_RWT_ACM_ACTIVATION (0x200001U + NFCIP_TIMEOUT_ADJUSTMENT) /*!< Digital 2.0 B.10 RWT ACTIVATION 2^21 + RWT Delta + Adjustment*/ + +#define RFAL_NFCDEP_HEADER_PAD (RFAL_NFCDEP_DEPREQ_HEADER_LEN - RFAL_NFCDEP_LEN_MIN) /*!< Difference between expected rcvd header len and max foreseen */ + + +#define NFCIP_MAX_TX_RETRYS (uint8_t)3U /*!< Number of retransmit retyrs */ +#define NFCIP_MAX_TO_RETRYS (uint8_t)3U /*!< Number of retrys for Timeout */ +#define NFCIP_MAX_RTOX_RETRYS (uint8_t)3U /*!< Number of retrys for RTOX */ +#define NFCIP_MAX_NACK_RETRYS (uint8_t)3U /*!< Number of retrys for NACK */ +#define NFCIP_MAX_ATN_RETRYS (uint8_t)3U /*!< Number of retrys for ATN */ + +#define NFCIP_MIN_TXERROR_LEN 4U /*!< Minimum frame length with error to be ignored Digital 1.0 14.12.5.4 */ + +#define NFCIP_REQ (uint8_t)0xD4U /*!= NFCIP_ST_INIT_IDLE) && ((st) <= NFCIP_ST_INIT_RLS) ) /*!< Checks if module is set as Initiator */ +#define nfcipIsTarget( st ) (!nfcipIsInitiator(st)) /*!< Checks if module is set as Target */ + +#define nfcipIsBRAllowed( br, mBR ) (((1U<<(br)) & (mBR)) != 0U) /*!< Checks bit rate is allowed by given mask */ + +#define nfcipIsEmptyDEPEnabled( op ) (!nfcipIsEmptyDEPDisabled(op)) /*!< Checks if empty payload is allowed by operation config NCI 1.0 Table 81 */ +#define nfcipIsEmptyDEPDisabled( op ) (((op) & RFAL_NFCDEP_OPER_EMPTY_DEP_DIS) != 0U) /*!< Checks if empty payload is not allowed by operation config NCI 1.0 Table 81 */ + +#define nfcipIsRTOXReqEnabled( op ) (!nfcipIsRTOXReqDisabled(op)) /*!< Checks if send a RTOX_REQ is allowed by operation config NCI 1.0 Table 81 */ +#define nfcipIsRTOXReqDisabled( op ) (((op) & RFAL_NFCDEP_OPER_RTOX_REQ_DIS) != 0U) /*!< Checks if send a RTOX_REQ is not allowed by operation config NCI 1.0 Table 81 */ + + +/*! Checks if isDeactivating callback is set and calls it, otherwise returns false */ +#define nfcipIsDeactivationPending() ( (gNfcip.isDeactivating == NULL) ? false : gNfcip.isDeactivating() ) + +/*! Returns the RWT Activation according to the current communication mode */ +#define nfcipRWTActivation() ((gNfcip.cfg.commMode == RFAL_NFCDEP_COMM_ACTIVE) ? NFCIP_RWT_ACM_ACTIVATION : NFCIP_RWT_ACTIVATION) + + +#define nfcipRTOXAdjust( v ) ((v) - ((v)>>3)) /*!< Adjust RTOX timer value to a percentage of the total, current 88% */ + +/*******************************************************************************/ + +// timerPollTimeoutValue is necessary after timerCalculateTimeout so that system will wake up upon timer timeout. +#define nfcipTimerStart( timer, time_ms ) (timer) = platformTimerCreate((uint16_t)(time_ms)) /*!< Configures and starts the RTOX timer */ +#define nfcipTimerisExpired( timer ) platformTimerIsExpired( timer ) /*!< Checks RTOX timer has expired */ + +#define nfcipLogE(...) /*!< Macro for the error log method */ +#define nfcipLogW(...) /*!< Macro for the warning log method */ +#define nfcipLogI(...) /*!< Macro for the info log method */ +#define nfcipLogD(...) /*!< Macro for the debug log method */ + + +/*! Digital 1.1 - 16.12.5.2 The Target SHALL NOT attempt any error recovery and remains in Rx mode upon Transmission or a Protocol Error */ +#define nfcDepReEnableRx( rxB, rxBL, rxL ) rfalTransceiveBlockingTx( NULL, 0, (rxB), (rxBL), (rxL), ( RFAL_TXRX_FLAGS_DEFAULT | (uint32_t)RFAL_TXRX_FLAGS_NFCIP1_ON ), RFAL_FWT_NONE ) + +/* + ****************************************************************************** + * LOCAL DATA TYPES + ****************************************************************************** + */ + +/*! Struct that holds all DEP parameters/configs for the following communications */ +typedef struct{ + uint8_t did; /*!< Device ID (DID) to be used */ + + uint8_t* txBuf; /*!< Pointer to the Tx buffer to be sent */ + uint16_t txBufLen; /*!< Length of the data in the txBuf */ + uint8_t txBufPaylPos; /*!< Position inside txBuf where data starts */ + bool txChaining; /*!< Flag indicating chaining on transmission */ + + uint8_t* rxBuf; /*!< Pointer to the Rx buffer for incoming data */ + uint16_t rxBufLen; /*!< Length of the data in the rxBuf */ + uint8_t rxBufPaylPos; /*!< Position inside rxBuf where data is to be placed*/ + + uint32_t fwt; /*!< Frame Waiting Time (FWT) to be used */ + uint32_t dFwt; /*!< Delta Frame Waiting Time (dFWT) to be used */ + uint16_t fsc; /*!< Frame Size (FSC) to be used */ + +} rfalNfcDepDEPParams; + +/*! NFCIP module states */ +typedef enum +{ + NFCIP_ST_IDLE, + NFCIP_ST_INIT_IDLE, + NFCIP_ST_INIT_ATR, + NFCIP_ST_INIT_PSL, + NFCIP_ST_INIT_DEP_IDLE, + NFCIP_ST_INIT_DEP_TX, + NFCIP_ST_INIT_DEP_RX, + NFCIP_ST_INIT_DEP_ATN, + NFCIP_ST_INIT_DSL, + NFCIP_ST_INIT_RLS, + + NFCIP_ST_TARG_WAIT_ATR, + NFCIP_ST_TARG_WAIT_ACTV, + NFCIP_ST_TARG_DEP_IDLE, + NFCIP_ST_TARG_DEP_RX, + NFCIP_ST_TARG_DEP_RTOX, + NFCIP_ST_TARG_DEP_TX, + NFCIP_ST_TARG_DEP_SLEEP +} rfalNfcDepState; + +/*! NFCIP commands (Request, Response) */ +typedef enum{ + NFCIP_CMD_ATR_REQ = 0x00, + NFCIP_CMD_ATR_RES = 0x01, + NFCIP_CMD_WUP_REQ = 0x02, + NFCIP_CMD_WUP_RES = 0x03, + NFCIP_CMD_PSL_REQ = 0x04, + NFCIP_CMD_PSL_RES = 0x05, + NFCIP_CMD_DEP_REQ = 0x06, + NFCIP_CMD_DEP_RES = 0x07, + NFCIP_CMD_DSL_REQ = 0x08, + NFCIP_CMD_DSL_RES = 0x09, + NFCIP_CMD_RLS_REQ = 0x0A, + NFCIP_CMD_RLS_RES = 0x0B +} rfalNfcDepCmd; + + +/*! Struct that holds all NFCIP data */ +typedef struct{ + rfalNfcDepConfigs cfg; /*!< Holds the current configuration to be used */ + + rfalNfcDepState state; /*!< Current state of the NFCIP module */ + uint8_t pni; /*!< Packet Number Information (PNI) counter */ + + uint8_t lastCmd; /*!< Last command sent */ + uint8_t lastPFB; /*!< Last PFB sent */ + uint8_t lastPFBnATN; /*!< Last PFB sent (excluding ATN) */ + uint8_t lastRTOX; /*!< Last RTOX value sent */ + + uint8_t cntTxRetrys; /*!< Retransmissions counter */ + uint8_t cntTORetrys; /*!< Timeouts counter */ + uint8_t cntRTOXRetrys; /*!< RTOX counter */ + uint8_t cntNACKRetrys; /*!< NACK counter */ + uint8_t cntATNRetrys; /*!< Attention (ATN) counter */ + + uint16_t fsc; /*!< Current Frame Size (FSC) to be used */ + bool isTxChaining; /*!< Flag for chaining on Transmission */ + bool isRxChaining; /*!< Flag for chaining on Reception */ + uint8_t* txBuf; /*!< Pointer to the Tx buffer to be sent */ + uint8_t* rxBuf; /*!< Pointer to the Rx buffer for incoming data */ + uint16_t txBufLen; /*!< Length of the data in the txBuf */ + uint16_t rxBufLen; /*!< Length of rxBuf buffer */ + uint16_t* rxRcvdLen; /*!< Length of the data in the rxBuf */ + uint8_t txBufPaylPos; /*!< Position in txBuf where data starts */ + uint8_t rxBufPaylPos; /*!< Position in rxBuf where data is to be placed */ + bool *isChaining; /*!< Flag for chaining on Reception */ + + rfalNfcDepDevice *nfcDepDev; /*!< Pointer to NFC-DEP device info */ + + uint32_t RTOXTimer; /*!< Timer used for RTOX */ + rfalNfcDepDeactCallback isDeactivating; /*!< Deactivating flag check callback */ + + bool isReqPending; /*!< Flag pending REQ from Target activation */ + bool isTxPending; /*!< Flag pending DEP Block while waiting RTOX Ack */ + bool isWait4RTOX; /*!< Flag for waiting RTOX Ack */ +}rfalNfcDep; + + +/* + ****************************************************************************** + * LOCAL VARIABLES + ****************************************************************************** + */ + +static rfalNfcDep gNfcip; /*!< NFCIP module instance */ + + +/* + ****************************************************************************** + * LOCAL FUNCTION PROTOTYPES + ****************************************************************************** + */ + +static ReturnCode nfcipTxRx( rfalNfcDepCmd cmd, uint8_t* txBuf, uint32_t fwt, uint8_t* paylBuf, uint8_t paylBufLen, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rxActLen ); +static ReturnCode nfcipTx( rfalNfcDepCmd cmd, uint8_t* txBuf, uint8_t *paylBuf, uint16_t paylLen, uint8_t pfbData, uint32_t fwt ); +static ReturnCode nfcipDEPControlMsg( uint8_t pfb, uint8_t RTOX ); +static ReturnCode nfcipInitiatorHandleDEP( ReturnCode rxRes, uint16_t rxLen, uint16_t *outActRxLen, bool *outIsChaining ); +static ReturnCode nfcipTargetHandleRX( ReturnCode rxRes, uint16_t *outActRxLen, bool *outIsChaining ); +static ReturnCode nfcipTargetHandleActivation( rfalNfcDepDevice *nfcDepDev, uint8_t *outBRS ); + + +/*! + ****************************************************************************** + * \brief NFCIP Configure + * + * Configures the nfcip layer with the given configurations + * + * \param[in] cfg : nfcip configuration for following communication + ****************************************************************************** + */ +static void nfcipConfig( const rfalNfcDepConfigs * cfg ); + + +/*! + ****************************************************************************** + * \brief Set DEP parameters + * + * This method sets the parameters/configs for following Data Exchange + * Sets the nfcip module state according to the role it is configured + * + * + * \warning To be used only after proper Initiator/Target activation: + * nfcipTargetHandleActivation() or nfcipInitiatorActivate() has + * returned success + * + * This must be called before nfcipRun() in case of Target to pass + * rxBuffer + * + * Everytime some data needs to be transmitted call this to set it and + * call nfcipRun() until done or error + * + * \param[in] DEPParams : the parameters to be used during Data Exchange + ****************************************************************************** + */ +static void nfcipSetDEPParams( rfalNfcDepDEPParams *DEPParams ); + + +/*! + ****************************************************************************** + * \brief NFCIP run protocol + * + * This method handles all the nfcip protocol during Data Exchange (DEP + * requests and responses). + * + * A data exchange cycle is considered a DEP REQ and a DEP RES. + * + * In case of Tx chaining(MI) must signal it with nfcipSetDEPParams() + * In case of Rx chaining(MI) outIsChaining will be set to true and the + * current data returned + * + * \param[out] outActRxLen : data received length + * \param[out] outIsChaining : true if other peer is performing chaining(MI) + * + * \return ERR_NONE : Data exchange cycle completed successfully + * \return ERR_TIMEOUT : Timeout occurred + * \return ERR_PROTO : Protocol error occurred + * \return ERR_AGAIN : Other peer is doing chaining(MI), current block + * was received successfully call again until complete + * + ****************************************************************************** + */ +static ReturnCode nfcipRun( uint16_t *outActRxLen, bool *outIsChaining ); + + +/*! + ****************************************************************************** + * \brief Transmission method + * + * This method checks if the current communication is Active or Passive + * and performs the necessary procedures for each communication type + * + * Transmits the data hold in txBuf + * + * \param[in] txBuf : buffer to transmit + * \param[in] txBufLen : txBuffer capacity + * \param[in] fwt : fwt for current Tx + * + * \return ERR_NONE : No error + ****************************************************************************** + */ +static ReturnCode nfcipDataTx( uint8_t* txBuf, uint16_t txBufLen, uint32_t fwt ); + + +/*! + ****************************************************************************** + * \brief Reception method + * + * This method checks if the current communication is Active or Passive + * and calls the appropriate reception method + * + * Copies incoming data to rxBuf + * + * \param[in] blocking : reception is to be done blocking or non-blocking + * + * \return ERR_BUSY : Busy + * \return ERR_NONE : No error + ****************************************************************************** + */ +static ReturnCode nfcipDataRx( bool blocking ); + + +/* + ****************************************************************************** + * LOCAL FUNCTIONS + ****************************************************************************** + */ + +/*******************************************************************************/ + + +/*******************************************************************************/ +static bool nfcipDxIsSupported( uint8_t Dx, uint8_t BRx, uint8_t BSx ) +{ + uint8_t Bx; + + /* Take the min of the possible bit rates, we'll use one for both directions */ + Bx = MIN(BRx, BSx); + + /* Lower bit rates must be supported for P2P */ + if( (Dx <= (uint8_t)RFAL_NFCDEP_Dx_04_424) ) + { + return true; + } + + if( (Dx == (uint8_t)RFAL_NFCDEP_Dx_08_848) && (Bx >= (uint8_t)RFAL_NFCDEP_Bx_08_848) ) + { + return true; + } + + return false; +} + + +/*******************************************************************************/ +static ReturnCode nfcipTxRx( rfalNfcDepCmd cmd, uint8_t* txBuf, uint32_t fwt, uint8_t* paylBuf, uint8_t paylBufLen, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rxActLen ) +{ + ReturnCode ret; + + if( (cmd == NFCIP_CMD_DEP_REQ) || (cmd == NFCIP_CMD_DEP_RES) ) /* this method cannot be used for DEPs */ + { + return ERR_PARAM; + } + + /* Assign the global params for this TxRx */ + gNfcip.rxBuf = rxBuf; + gNfcip.rxBufLen = rxBufLen; + gNfcip.rxRcvdLen = rxActLen; + + + /*******************************************************************************/ + /* Transmission */ + /*******************************************************************************/ + if(txBuf != NULL) /* if nothing to Tx, just do Rx */ + { + EXIT_ON_ERR( ret, nfcipTx( cmd, txBuf, paylBuf, paylBufLen, 0, fwt ) ); + } + + /*******************************************************************************/ + /* Reception */ + /*******************************************************************************/ + ret = nfcipDataRx( true ); + if( ret != ERR_NONE ) + { + return ret; + } + + /*******************************************************************************/ + *rxActLen = *rxBuf; /* Use LEN byte instead due to with/without CRC modes */ + return ERR_NONE; /* Tx and Rx completed successfully */ +} + + +/*******************************************************************************/ +static ReturnCode nfcipDEPControlMsg( uint8_t pfb, uint8_t RTOX ) +{ + uint8_t ctrlMsg[20]; + rfalNfcDepCmd depCmd; + uint32_t fwt; + + + /*******************************************************************************/ + /* Calculate Cmd and fwt to be used */ + /*******************************************************************************/ + depCmd = ((gNfcip.cfg.role == RFAL_NFCDEP_ROLE_TARGET) ? NFCIP_CMD_DEP_RES : NFCIP_CMD_DEP_REQ); + fwt = ((gNfcip.cfg.role == RFAL_NFCDEP_ROLE_TARGET) ? NFCIP_NO_FWT : (nfcip_PFBisSTO( pfb ) ? ( (RTOX*gNfcip.cfg.fwt) + gNfcip.cfg.dFwt) : (gNfcip.cfg.fwt + gNfcip.cfg.dFwt) ) ); + + if( nfcip_PFBisSTO( pfb ) ) + { + ctrlMsg[RFAL_NFCDEP_DEPREQ_HEADER_LEN] = RTOX; + return nfcipTx( depCmd, ctrlMsg, &ctrlMsg[RFAL_NFCDEP_DEPREQ_HEADER_LEN], sizeof(uint8_t), pfb, fwt ); + } + else + { + return nfcipTx( depCmd, ctrlMsg, NULL, 0, pfb, fwt ); + } +} + +/*******************************************************************************/ +static void nfcipClearCounters( void ) +{ + gNfcip.cntATNRetrys = 0; + gNfcip.cntNACKRetrys = 0; + gNfcip.cntTORetrys = 0; + gNfcip.cntTxRetrys = 0; + gNfcip.cntRTOXRetrys = 0; +} + +/*******************************************************************************/ +static ReturnCode nfcipInitiatorHandleDEP( ReturnCode rxRes, uint16_t rxLen, uint16_t *outActRxLen, bool *outIsChaining ) +{ + ReturnCode ret; + uint8_t nfcDepLen; + uint8_t rxMsgIt; + uint8_t rxPFB; + uint8_t rxRTOX; + uint8_t optHdrLen; + + ret = ERR_INTERNAL; + rxMsgIt = 0; + optHdrLen = 0; + + *outActRxLen = 0; + *outIsChaining = false; + + + /*******************************************************************************/ + /* Handle reception errors */ + /*******************************************************************************/ + switch( rxRes ) + { + /*******************************************************************************/ + /* Timeout -> Digital 1.0 14.15.5.6 */ + case ERR_TIMEOUT: + + nfcipLogI( " NFCIP(I) TIMEOUT TORetrys:%d \r\n", gNfcip.cntTORetrys ); + + /* Digital 1.0 14.15.5.6 - If nTO >= Max raise protocol error */ + if( gNfcip.cntTORetrys++ >= NFCIP_MAX_TO_RETRYS ) + { + return ERR_PROTO; + } + + /*******************************************************************************/ + /* Upon Timeout error, if Deactivation is pending, no more error recovery + * will be done #54. + * This is used to address the issue some devices that havea big TO. + * Normally LLCP layer has timeout already, and NFCIP layer is still + * running error handling, retrying ATN/NACKs */ + /*******************************************************************************/ + if( nfcipIsDeactivationPending() ) + { + nfcipLogI( " skipping error recovery due deactivation pending \r\n"); + return ERR_TIMEOUT; + } + + /* Digital 1.0 14.15.5.6 1) If last PDU was NACK */ + if( nfcip_PFBisRNACK(gNfcip.lastPFB) ) + { + /* Digital 1.0 14.15.5.6 2) if NACKs failed raise protocol error */ + if( gNfcip.cntNACKRetrys++ >= NFCIP_MAX_NACK_RETRYS ) + { + return ERR_PROTO; + } + + /* Send NACK */ + nfcipLogI( " NFCIP(I) Sending NACK retry: %d \r\n", gNfcip.cntNACKRetrys ); + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBRPDU_NACK(gNfcip.pni), 0 ) ); + return ERR_BUSY; + } + + nfcipLogI( " NFCIP(I) Checking if to send ATN ATNRetrys: %d \r\n", gNfcip.cntATNRetrys ); + + /* Digital 1.0 14.15.5.6 3) Otherwise send ATN */ + if( gNfcip.cntATNRetrys++ >= NFCIP_MAX_NACK_RETRYS ) + { + return ERR_PROTO; + } + + /* Send ATN */ + nfcipLogI( " NFCIP(I) Sending ATN \r\n" ); + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBSPDU_ATN(), 0 ) ); + return ERR_BUSY; + + /*******************************************************************************/ + /* Data rcvd with error -> Digital 1.0 14.12.5.4 */ + case ERR_CRC: + case ERR_PAR: + case ERR_FRAMING: + case ERR_RF_COLLISION: + + nfcipLogI( " NFCIP(I) rx Error: %d \r\n", rxRes ); + + /* Digital 1.0 14.12.5.4 Tx Error with data, ignore */ + if( rxLen < NFCIP_MIN_TXERROR_LEN ) + { + nfcipLogI( " NFCIP(I) Transmission error w data \r\n" ); +#if 0 + if(gNfcip.cfg.commMode == RFAL_NFCDEP_COMM_PASSIVE) + { + nfcipLogI( " NFCIP(I) Transmission error w data -> reEnabling Rx \r\n" ); + nfcipReEnableRxTout( NFCIP_TRECOV ); + return ERR_BUSY; + } +#endif /* 0 */ + } + + /* Digital 1.1 16.12.5.4 if NACKs failed raise Transmission error */ + if( gNfcip.cntNACKRetrys++ >= NFCIP_MAX_NACK_RETRYS ) + { + return ERR_FRAMING; + } + + /* Send NACK */ + nfcipLogI( " NFCIP(I) Sending NACK \r\n" ); + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBRPDU_NACK(gNfcip.pni), 0 ) ); + return ERR_BUSY; + + case ERR_NONE: + break; + + case ERR_BUSY: + return ERR_BUSY; /* Debug purposes */ + + default: + nfcipLogW( " NFCIP(I) Error: %d \r\n", rxRes ); + return rxRes; + } + + /*******************************************************************************/ + /* Rx OK check if valid DEP PDU */ + /*******************************************************************************/ + + /* Due to different modes on ST25R391x (with/without CRC) use NFC-DEP LEN instead of bytes retrieved */ + nfcDepLen = gNfcip.rxBuf[rxMsgIt++]; + + nfcipLogD( " NFCIP(I) rx OK: %d bytes \r\n", nfcDepLen ); + + /* Digital 1.0 14.15.5.5 Protocol Error */ + if( gNfcip.rxBuf[rxMsgIt++] != NFCIP_RES ) + { + nfcipLogW( " NFCIP(I) error %02X instead of %02X \r\n", gNfcip.rxBuf[--rxMsgIt], NFCIP_RES ); + return ERR_PROTO; + } + + /* Digital 1.0 14.15.5.5 Protocol Error */ + if( gNfcip.rxBuf[rxMsgIt++] != (uint8_t)NFCIP_CMD_DEP_RES ) + { + nfcipLogW( " NFCIP(I) error %02X instead of %02X \r\n", gNfcip.rxBuf[--rxMsgIt], NFCIP_CMD_DEP_RES ); + return ERR_PROTO; + } + + rxPFB = gNfcip.rxBuf[rxMsgIt++]; + + /*******************************************************************************/ + /* Check for valid PFB type */ + if( !(nfcip_PFBisSPDU( rxPFB ) || nfcip_PFBisRPDU( rxPFB ) || nfcip_PFBisIPDU( rxPFB )) ) + { + return ERR_PROTO; + } + + /*******************************************************************************/ + /* Digital 1.0 14.8.2.1 check if DID is expected and match -> Protocol Error */ + if( gNfcip.cfg.did != RFAL_NFCDEP_DID_NO ) + { + if( (gNfcip.rxBuf[rxMsgIt++] != gNfcip.cfg.did) || !nfcip_PFBhasDID( rxPFB ) ) + { + return ERR_PROTO; + } + optHdrLen++; /* Inc header optional field cnt*/ + } + else if( nfcip_PFBhasDID( rxPFB ) ) /* DID not expected but rcv */ + { + return ERR_PROTO; + } + else + { + /* MISRA 15.7 - Empty else */ + } + + /*******************************************************************************/ + /* Digital 1.0 14.6.2.8 & 14.6.3.11 NAD must not be used */ + if( gNfcip.cfg.nad != RFAL_NFCDEP_NAD_NO ) + { + if( (gNfcip.rxBuf[rxMsgIt++] != gNfcip.cfg.nad) || !nfcip_PFBhasNAD( rxPFB ) ) + { + return ERR_PROTO; + } + optHdrLen++; /* Inc header optional field cnt*/ + } + else if( nfcip_PFBhasNAD( rxPFB ) ) /* NAD not expected but rcv */ + { + return ERR_PROTO; + } + else + { + /* MISRA 15.7 - Empty else */ + } + + /*******************************************************************************/ + /* Process R-PDU */ + /*******************************************************************************/ + if( nfcip_PFBisRPDU( rxPFB ) ) + { + /*******************************************************************************/ + /* R ACK */ + /*******************************************************************************/ + if( nfcip_PFBisRACK( rxPFB ) ) + { + nfcipLogI( " NFCIP(I) Rcvd ACK \r\n" ); + if( gNfcip.pni == nfcip_PBF_PNI( rxPFB ) ) + { + /* 14.12.3.3 R-ACK with correct PNI -> Increment */ + gNfcip.pni = nfcip_PNIInc( gNfcip.pni ); + + /* R-ACK while not performing chaining -> Protocol error*/ + if( !gNfcip.isTxChaining ) + { + return ERR_PROTO; + } + + nfcipClearCounters(); + gNfcip.state = NFCIP_ST_INIT_DEP_IDLE; + return ERR_NONE; /* This block has been transmitted */ + } + else /* Digital 1.0 14.12.4.5 ACK with wrong PNI Initiator may retransmit */ + { + if( gNfcip.cntTxRetrys++ >= NFCIP_MAX_TX_RETRYS ) + { + return ERR_PROTO; + } + + /* Extended the MAY in Digital 1.0 14.12.4.5 to only reTransmit if the ACK + * is for the previous DEP, otherwise raise Protocol immediately + * If the PNI difference is more than 1 it is worthless to reTransmit 3x + * and after raise the error */ + + if( nfcip_PNIDec( gNfcip.pni ) == nfcip_PBF_PNI( rxPFB ) ) + { + /* ReTransmit */ + nfcipLogI( " NFCIP(I) Rcvd ACK prev PNI -> reTx \r\n" ); + gNfcip.state = NFCIP_ST_INIT_DEP_TX; + return ERR_BUSY; + } + + nfcipLogI( " NFCIP(I) Rcvd ACK unexpected far PNI -> Error \r\n" ); + return ERR_PROTO; + } + } + else /* Digital 1.0 - 14.12.5.2 Target must never send NACK */ + { + return ERR_PROTO; + } + } + + /*******************************************************************************/ + /* Process S-PDU */ + /*******************************************************************************/ + if( nfcip_PFBisSPDU( rxPFB ) ) + { + nfcipLogI( " NFCIP(I) Rcvd S-PDU \r\n" ); + /*******************************************************************************/ + /* S ATN */ + /*******************************************************************************/ + if( nfcip_PFBisSATN( rxPFB ) ) /* If is a S-ATN */ + { + nfcipLogI( " NFCIP(I) Rcvd ATN \r\n" ); + if( nfcip_PFBisSATN( gNfcip.lastPFB ) ) /* Check if is expected */ + { + gNfcip.cntATNRetrys = 0; /* Clear ATN counter */ + + /* Although spec is not clear NFC Forum Digital test is expecting to + * retransmit upon receiving ATN_RES */ + if( nfcip_PFBisSTO( gNfcip.lastPFBnATN ) ) + { + nfcipLogI( " NFCIP(I) Rcvd ATN -> reTx RTOX_RES \r\n" ); + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBSPDU_TO(), gNfcip.lastRTOX ) ); + } + else + { + /* ReTransmit ? */ + if( gNfcip.cntTxRetrys++ >= NFCIP_MAX_TX_RETRYS ) + { + return ERR_PROTO; + } + + nfcipLogI( " NFCIP(I) Rcvd ATN -> reTx PNI: %d \r\n", gNfcip.pni ); + gNfcip.state = NFCIP_ST_INIT_DEP_TX; + } + + return ERR_BUSY; + } + else /* Digital 1.0 14.12.4.4 & 14.12.4.8 */ + { + return ERR_PROTO; + } + } + /*******************************************************************************/ + /* S TO */ + /*******************************************************************************/ + else if( nfcip_PFBisSTO( rxPFB ) ) /* If is a S-TO (RTOX) */ + { + nfcipLogI( " NFCIP(I) Rcvd TO \r\n" ); + + rxRTOX = gNfcip.rxBuf[rxMsgIt++]; + + /* Digital 1.1 16.12.4.3 - Initiator MAY stop accepting subsequent RTOX Req * + * - RTOX request to an ATN -> Protocol error */ + if( (gNfcip.cntRTOXRetrys++ > NFCIP_MAX_RTOX_RETRYS) || nfcip_PFBisSATN( gNfcip.lastPFB ) ) + { + return ERR_PROTO; + } + + /* Digital 1.1 16.8.4.1 RTOX must be between [1,59] */ + if( (rxRTOX < NFCIP_INIT_MIN_RTOX) || (rxRTOX > NFCIP_INIT_MAX_RTOX) ) + { + return ERR_PROTO; + } + + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBSPDU_TO(), rxRTOX ) ); + gNfcip.lastRTOX = rxRTOX; + + return ERR_BUSY; + } + else + { + /* Unexpected S-PDU */ + return ERR_PROTO; /* PRQA S 2880 # MISRA 2.1 - Guard code to prevent unexpected behavior */ + } + } + + /*******************************************************************************/ + /* Process I-PDU */ + /*******************************************************************************/ + if( nfcip_PFBisIPDU( rxPFB ) ) + { + if( gNfcip.pni != nfcip_PBF_PNI( rxPFB ) ) + { + nfcipLogI( " NFCIP(I) Rcvd IPDU wrong PNI curPNI: %d rxPNI: %d \r\n", gNfcip.pni , nfcip_PBF_PNI( rxPFB ) ); + return ERR_PROTO; + } + + nfcipLogD( " NFCIP(I) Rcvd IPDU OK PNI: %d \r\n", gNfcip.pni ); + + /* 14.12.3.3 I-PDU with correct PNI -> Increment */ + gNfcip.pni = nfcip_PNIInc( gNfcip.pni ); + + + /* Successful data Exchange */ + nfcipClearCounters(); + *outActRxLen = ((uint16_t)nfcDepLen - RFAL_NFCDEP_DEP_HEADER - (uint16_t)optHdrLen); + + if( (&gNfcip.rxBuf[gNfcip.rxBufPaylPos] != &gNfcip.rxBuf[RFAL_NFCDEP_DEP_HEADER + optHdrLen]) && (*outActRxLen > 0U) ) + { + ST_MEMMOVE( &gNfcip.rxBuf[gNfcip.rxBufPaylPos], &gNfcip.rxBuf[RFAL_NFCDEP_DEP_HEADER + optHdrLen], *outActRxLen ); + } + + /*******************************************************************************/ + /* Check if target is indicating chaining MI */ + /*******************************************************************************/ + if( nfcip_PFBisIMI( rxPFB ) ) + { + gNfcip.isRxChaining = true; + *outIsChaining = true; + + nfcipLogD( " NFCIP(I) Rcvd IPDU OK w MI -> ACK \r\n" ); + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBRPDU_ACK( gNfcip.pni ), gNfcip.rxBuf[rxMsgIt++] ) ); + + return ERR_AGAIN; /* Send Again signalling to run again, but some chaining data has arrived*/ + } + else + { + gNfcip.isRxChaining = false; + gNfcip.state = NFCIP_ST_INIT_DEP_IDLE; + + ret = ERR_NONE; /* Data exchange done */ + } + } + return ret; +} + + +/*******************************************************************************/ +static ReturnCode nfcipTargetHandleRX( ReturnCode rxRes, uint16_t *outActRxLen, bool *outIsChaining ) +{ + ReturnCode ret; + uint8_t nfcDepLen; + uint8_t rxMsgIt; + uint8_t rxPFB; + uint8_t optHdrLen; + uint8_t resBuf[RFAL_NFCDEP_HEADER_PAD + NFCIP_TARGET_RES_MAX]; + + + ret = ERR_INTERNAL; + rxMsgIt = 0; + optHdrLen = 0; + + *outActRxLen = 0; + *outIsChaining = false; + + + /*******************************************************************************/ + /* Handle reception errors */ + /*******************************************************************************/ + switch( rxRes ) + { + /*******************************************************************************/ + case ERR_NONE: + break; + + case ERR_LINK_LOSS: + nfcipLogW( " NFCIP(T) Error: %d \r\n", rxRes ); + return rxRes; + + case ERR_BUSY: + return ERR_BUSY; /* Debug purposes */ + + case ERR_TIMEOUT: + case ERR_CRC: + case ERR_PAR: + case ERR_FRAMING: + case ERR_PROTO: + default: + /* Digital 1.1 16.12.5.2 The Target MUST NOT attempt any error recovery. * + * The Target MUST always stay in receive mode when a * + * Transmission Error or a Protocol Error occurs. * + * * + * Do not push Transmission/Protocol Errors to upper layer in Listen Mode #766 */ + + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; + } + + /*******************************************************************************/ + /* Rx OK check if valid DEP PDU */ + /*******************************************************************************/ + + /* Due to different modes on ST25R391x (with/without CRC) use NFC-DEP LEN instead of bytes retrieved */ + nfcDepLen = gNfcip.rxBuf[rxMsgIt++]; + + nfcipLogD( " NFCIP(T) rx OK: %d bytes \r\n", nfcDepLen ); + + if( gNfcip.rxBuf[rxMsgIt++] != NFCIP_REQ ) + { + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore bad request */ + } + + + /*******************************************************************************/ + /* Check whether target rcvd a normal DEP or deactivation request */ + /*******************************************************************************/ + switch( gNfcip.rxBuf[rxMsgIt++] ) + { + /*******************************************************************************/ + case (uint8_t)NFCIP_CMD_DEP_REQ: + break; /* Continue to normal DEP processing */ + + /*******************************************************************************/ + case (uint8_t)NFCIP_CMD_DSL_REQ: + + nfcipLogI( " NFCIP(T) rx DSL \r\n" ); + + /* Digital 1.0 14.9.1.2 If DID is used and incorrect ignore it */ + /* [Digital 1.0, 16.9.1.2]: If DID == 0, Target SHALL ignore DSL_REQ with DID */ + if ( (((gNfcip.rxBuf[rxMsgIt++] != gNfcip.cfg.did) || (nfcDepLen != RFAL_NFCDEP_DSL_RLS_LEN_DID)) && (gNfcip.cfg.did != RFAL_NFCDEP_DID_NO) ) + || ((gNfcip.cfg.did == RFAL_NFCDEP_DID_NO) && (nfcDepLen != RFAL_NFCDEP_DSL_RLS_LEN_NO_DID)) + ) + { + nfcipLogI( " NFCIP(T) DSL wrong DID, ignoring \r\n" ); + return ERR_BUSY; + } + + nfcipTx( NFCIP_CMD_DSL_RES, resBuf, NULL, 0, 0, NFCIP_NO_FWT ); + + gNfcip.state = NFCIP_ST_TARG_DEP_SLEEP; + return ERR_SLEEP_REQ; + + /*******************************************************************************/ + case (uint8_t)NFCIP_CMD_RLS_REQ: + + nfcipLogI( " NFCIP(T) rx RLS \r\n" ); + + /* Digital 1.0 14.10.1.2 If DID is used and incorrect ignore it */ + /* [Digital 1.0, 16.10.2.2]: If DID == 0, Target SHALL ignore DSL_REQ with DID */ + if ( (((gNfcip.rxBuf[rxMsgIt++] != gNfcip.cfg.did) || (nfcDepLen != RFAL_NFCDEP_DSL_RLS_LEN_DID)) && (gNfcip.cfg.did != RFAL_NFCDEP_DID_NO) ) + || ((gNfcip.cfg.did == RFAL_NFCDEP_DID_NO) && (nfcDepLen > RFAL_NFCDEP_DSL_RLS_LEN_NO_DID)) + ) + { + nfcipLogI( " NFCIP(T) RLS wrong DID, ignoring \r\n" ); + return ERR_BUSY; + } + + nfcipTx( NFCIP_CMD_RLS_RES, resBuf, NULL, 0, 0, NFCIP_NO_FWT ); + + gNfcip.state = NFCIP_ST_TARG_DEP_IDLE; + return ERR_RELEASE_REQ; + + /*******************************************************************************/ + /*case NFCIP_CMD_PSL_REQ: PSL must be handled in Activation only */ + /*case NFCIP_CMD_WUP_REQ: WUP not in NFC Forum Digital 1.0 */ + default: + + /* Don't go to NFCIP_ST_TARG_DEP_IDLE state as it needs to ignore this * + * invalid frame, and keep waiting for more frames */ + + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore bad frame */ + } + + /*******************************************************************************/ + + rxPFB = gNfcip.rxBuf[rxMsgIt++]; /* Store rcvd PFB */ + + /*******************************************************************************/ + /* Check for valid PFB type */ + if( !(nfcip_PFBisSPDU( rxPFB ) || nfcip_PFBisRPDU( rxPFB ) || nfcip_PFBisIPDU( rxPFB )) ) + { + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore invalid PFB */ + } + + /*******************************************************************************/ + if( gNfcip.cfg.did != RFAL_NFCDEP_DID_NO ) + { + if( !nfcip_PFBhasDID( rxPFB ) ) + { + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore bad/missing DID */ + } + if( gNfcip.rxBuf[rxMsgIt++] != gNfcip.cfg.did ) /* MISRA 13.5 */ + { + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore bad/missing DID */ + } + optHdrLen++; /* Inc header optional field cnt*/ + } + else if( nfcip_PFBhasDID( rxPFB ) ) /* DID not expected but rcv */ + { + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore unexpected DID */ + } + else + { + /* MISRA 15.7 - Empty else */ + } + + + /*******************************************************************************/ + if( gNfcip.cfg.nad != RFAL_NFCDEP_NAD_NO ) + { + if( (gNfcip.rxBuf[rxMsgIt++] != gNfcip.cfg.did) || !nfcip_PFBhasDID( rxPFB ) ) + { + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore bad/missing DID */ + } + optHdrLen++; /* Inc header optional field cnt*/ + } + else if( nfcip_PFBhasNAD( rxPFB ) ) /* NAD not expected but rcv */ + { + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore unexpected NAD */ + } + else + { + /* MISRA 15.7 - Empty else */ + } + + + /*******************************************************************************/ + /* Process R-PDU */ + /*******************************************************************************/ + if( nfcip_PFBisRPDU( rxPFB ) ) + { + nfcipLogD( " NFCIP(T) Rcvd R-PDU \r\n" ); + /*******************************************************************************/ + /* R ACK */ + /*******************************************************************************/ + if( nfcip_PFBisRACK( rxPFB ) ) + { + nfcipLogI( " NFCIP(T) Rcvd ACK \r\n" ); + if( gNfcip.pni == nfcip_PBF_PNI( rxPFB ) ) + { + /* R-ACK while not performing chaining -> Protocol error */ + if( !gNfcip.isTxChaining ) + { + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore unexpected ACK */ + } + + /* This block has been transmitted and acknowledged, perform RTOX until next data is provided */ + + /* Digital 1.1 16.12.4.7 - If ACK rcvd continue with chaining or an RTOX */ + nfcipTimerStart( gNfcip.RTOXTimer, nfcipRTOXAdjust( nfcipConv1FcToMs( rfalNfcDepWT2RWT( gNfcip.cfg.to ) )) ); + gNfcip.state = NFCIP_ST_TARG_DEP_RTOX; + + return ERR_NONE; /* This block has been transmitted */ + } + + /* Digital 1.0 14.12.3.4 - If last send was ATN and rx PNI is minus 1 */ + else if( nfcip_PFBisSATN( gNfcip.lastPFB ) && (nfcip_PNIDec(gNfcip.pni) == nfcip_PBF_PNI( rxPFB )) ) + { + nfcipLogI( " NFCIP(T) wrong PNI, last was ATN reTx \r\n" ); + /* Spec says to leave current PNI as is, but will be Inc after Tx, remaining the same */ + gNfcip.pni = nfcip_PNIDec( gNfcip.pni ); + + gNfcip.state = NFCIP_ST_TARG_DEP_TX; + return ERR_BUSY; + } + else + { + /* MISRA 15.7 - Empty else */ + } + } + /*******************************************************************************/ + /* R NACK */ + /*******************************************************************************/ + /* ISO 18092 12.6.1.3.3 When rcv NACK if PNI = prev PNI sent -> reTx */ + else if( nfcip_PFBisRNACK( rxPFB ) && (nfcip_PNIDec(gNfcip.pni) == nfcip_PBF_PNI( rxPFB ) ) ) + { + nfcipLogI( " NFCIP(T) Rcvd NACK \r\n" ); + + gNfcip.pni = nfcip_PNIDec( gNfcip.pni ); /* Dec so that has the prev PNI */ + + gNfcip.state = NFCIP_ST_TARG_DEP_TX; + return ERR_BUSY; + } + else + { + nfcipLogI( " NFCIP(T) Unexpected R-PDU \r\n" ); + + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore unexpected R-PDU */ + } + } + + /*******************************************************************************/ + /* Process S-PDU */ + /*******************************************************************************/ + if( nfcip_PFBisSPDU( rxPFB ) ) + { + nfcipLogD( " NFCIP(T) Rcvd S-PDU \r\n" ); + + /*******************************************************************************/ + /* S ATN */ + /*******************************************************************************/ + /* ISO 18092 12.6.3 Attention */ + if( nfcip_PFBisSATN( rxPFB ) ) /* If is a S-ATN */ + { + nfcipLogI( " NFCIP(T) Rcvd ATN curPNI: %d \r\n", gNfcip.pni ); + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBSPDU_ATN(), 0 ) ); + return ERR_BUSY; + } + + /*******************************************************************************/ + /* S TO */ + /*******************************************************************************/ + else if( nfcip_PFBisSTO( rxPFB ) ) /* If is a S-TO (RTOX) */ + { + if( nfcip_PFBisSTO( gNfcip.lastPFBnATN ) ) + { + nfcipLogI( " NFCIP(T) Rcvd TO \r\n" ); + + /* Digital 1.1 16.8.4.6 RTOX value in RES different that in REQ -> Protocol Error */ + if( gNfcip.lastRTOX != gNfcip.rxBuf[rxMsgIt++] ) + { + nfcipLogI( " NFCIP(T) Mismatched RTOX value \r\n" ); + + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore unexpected RTOX value */ + } + + /* Clear waiting for RTOX Ack Flag */ + gNfcip.isWait4RTOX = false; + + /* Check if a Tx is already pending */ + if( gNfcip.isTxPending ) + { + nfcipLogW( " NFCIP(T) Tx pending, go immediately to TX \r\n" ); + + gNfcip.state = NFCIP_ST_TARG_DEP_TX; + return ERR_BUSY; + } + + /* Start RTOX timer and change to check state */ + nfcipTimerStart( gNfcip.RTOXTimer, nfcipRTOXAdjust( nfcipConv1FcToMs( gNfcip.lastRTOX * rfalNfcDepWT2RWT(gNfcip.cfg.to ) ) ) ); + gNfcip.state = NFCIP_ST_TARG_DEP_RTOX; + + return ERR_BUSY; + } + } + else + { + /* Unexpected S-PDU */ + nfcipLogI( " NFCIP(T) Unexpected S-PDU \r\n" ); /* PRQA S 2880 # MISRA 2.1 - Guard code to prevent unexpected behavior */ + + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore unexpected S-PDU */ + } + } + + /*******************************************************************************/ + /* Process I-PDU */ + /*******************************************************************************/ + if( nfcip_PFBisIPDU( rxPFB ) ) + { + if( gNfcip.pni != nfcip_PBF_PNI( rxPFB ) ) + { + nfcipLogI( " NFCIP(T) Rcvd IPDU wrong PNI curPNI: %d rxPNI: %d \r\n", gNfcip.pni, nfcip_PBF_PNI( rxPFB ) ); + + /* Digital 1.1 16.12.3.4 - If last send was ATN and rx PNI is minus 1 */ + if( nfcip_PFBisSATN(gNfcip.lastPFB ) && (nfcip_PNIDec(gNfcip.pni) == nfcip_PBF_PNI( rxPFB )) ) + { + /* Spec says to leave current PNI as is, but will be Inc after Data Tx, remaining the same */ + gNfcip.pni = nfcip_PNIDec(gNfcip.pni); + + if( nfcip_PFBisIMI( rxPFB ) ) + { + nfcipLogI( " NFCIP(T) PNI = prevPNI && ATN before && chaining -> send ACK \r\n" ); + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBRPDU_ACK( gNfcip.pni ), gNfcip.rxBuf[rxMsgIt++] ) ); + + /* Digital 1.1 16.12.3.4 (...) leave the current PNI unchanged afterwards */ + gNfcip.pni = nfcip_PNIInc( gNfcip.pni ); + } + else + { + nfcipLogI( " NFCIP(T) PNI = prevPNI && ATN before -> reTx last I-PDU \r\n" ); + gNfcip.state = NFCIP_ST_TARG_DEP_TX; + } + + return ERR_BUSY; + } + + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + return ERR_BUSY; /* ERR_PROTO - Ignore bad PNI value */ + } + + nfcipLogD( " NFCIP(T) Rcvd IPDU OK PNI: %d \r\n", gNfcip.pni ); + + /*******************************************************************************/ + /* Successful data exchange */ + /*******************************************************************************/ + *outActRxLen = ((uint16_t)nfcDepLen - RFAL_NFCDEP_DEP_HEADER - (uint16_t)optHdrLen); + + nfcipClearCounters(); + + if( (&gNfcip.rxBuf[gNfcip.rxBufPaylPos] != &gNfcip.rxBuf[RFAL_NFCDEP_DEP_HEADER + optHdrLen]) && (*outActRxLen > 0U) ) + { + ST_MEMMOVE( &gNfcip.rxBuf[gNfcip.rxBufPaylPos], &gNfcip.rxBuf[RFAL_NFCDEP_DEP_HEADER + optHdrLen], *outActRxLen ); + } + + + /*******************************************************************************/ + /* Check if Initiator is indicating chaining MI */ + /*******************************************************************************/ + if( nfcip_PFBisIMI( rxPFB ) ) + { + gNfcip.isRxChaining = true; + *outIsChaining = true; + + nfcipLogD( " NFCIP(T) Rcvd IPDU OK w MI -> ACK \r\n" ); + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBRPDU_ACK( gNfcip.pni ), gNfcip.rxBuf[rxMsgIt++] ) ); + + gNfcip.pni = nfcip_PNIInc( gNfcip.pni ); + + return ERR_AGAIN; /* Send Again signalling to run again, but some chaining data has arrived*/ + } + else + { + if(gNfcip.isRxChaining) + { + nfcipLogI( " NFCIP(T) Rcvd last IPDU chaining finished \r\n" ); + } + + /*******************************************************************************/ + /* Reception done, send to DH and start RTOX timer */ + /*******************************************************************************/ + nfcipTimerStart( gNfcip.RTOXTimer, nfcipRTOXAdjust( nfcipConv1FcToMs( rfalNfcDepWT2RWT( gNfcip.cfg.to ) )) ); + gNfcip.state = NFCIP_ST_TARG_DEP_RTOX; + + gNfcip.isRxChaining = false; + ret = ERR_NONE; /* Data exchange done */ + } + } + return ret; +} + + +/*******************************************************************************/ +static ReturnCode nfcipTx( rfalNfcDepCmd cmd, uint8_t* txBuf, uint8_t *paylBuf, uint16_t paylLen, uint8_t pfbData, uint32_t fwt ) +{ + uint16_t txBufIt; + uint8_t *txBlock; + uint8_t *payloadBuf; + uint8_t pfb; + + + if( txBuf == NULL ) + { + return ERR_PARAM; + } + + + payloadBuf = paylBuf; /* MISRA 17.8: Use intermediate variable */ + + if( (paylLen == 0U) || (payloadBuf == NULL) ) + { + payloadBuf = (uint8_t*) &txBuf[RFAL_NFCDEP_DEPREQ_HEADER_LEN]; /* If not a DEP (no Data) ensure enough space for header */ + } + + + txBufIt = 0; + pfb = pfbData; /* MISRA 17.8: Use intermediate variable */ + + txBlock = payloadBuf; /* Point to beginning of the Data, and go backwards */ + + + gNfcip.lastCmd = (uint8_t)cmd; /* Store last cmd sent */ + gNfcip.lastPFB = NFCIP_PFB_INVALID; /* Reset last pfb sent */ + + /*******************************************************************************/ + /* Compute outgoing NFCIP message */ + /*******************************************************************************/ + switch( cmd ) + { + /*******************************************************************************/ + case NFCIP_CMD_ATR_RES: + case NFCIP_CMD_ATR_REQ: + + rfalNfcDepSetNFCID( payloadBuf, gNfcip.cfg.nfcid, gNfcip.cfg.nfcidLen ); /* NFCID */ + txBufIt += RFAL_NFCDEP_NFCID3_LEN; + + payloadBuf[txBufIt++] = gNfcip.cfg.did; /* DID */ + payloadBuf[txBufIt++] = gNfcip.cfg.bs; /* BS */ + payloadBuf[txBufIt++] = gNfcip.cfg.br; /* BR */ + + if( cmd == NFCIP_CMD_ATR_RES ) + { + payloadBuf[txBufIt++] = gNfcip.cfg.to; /* ATR_RES[ TO ] */ + } + + if( gNfcip.cfg.gbLen > 0U) + { + payloadBuf[txBufIt++] = nfcip_PPwGB( gNfcip.cfg.lr ); /* PP signalling GB */ + ST_MEMCPY( &payloadBuf[txBufIt], gNfcip.cfg.gb, gNfcip.cfg.gbLen ); /* set General Bytes */ + txBufIt += gNfcip.cfg.gbLen; + } + else + { + payloadBuf[txBufIt++] = rfalNfcDepLR2PP( gNfcip.cfg.lr ); /* PP without GB */ + } + + if( (txBufIt + RFAL_NFCDEP_CMDTYPE_LEN + RFAL_NFCDEP_CMD_LEN) > RFAL_NFCDEP_ATRREQ_MAX_LEN ) /* Check max ATR length (ATR_REQ = ATR_RES)*/ + { + return ERR_PARAM; + } + break; + + /*******************************************************************************/ + case NFCIP_CMD_WUP_REQ: /* ISO 18092 - 12.5.2.1 */ + + rfalNfcDepSetNFCID( (payloadBuf), gNfcip.cfg.nfcid, gNfcip.cfg.nfcidLen ); /* NFCID */ + txBufIt += RFAL_NFCDEP_NFCID3_LEN; + + *(--txBlock) = gNfcip.cfg.did; /* DID */ + break; + + /*******************************************************************************/ + case NFCIP_CMD_WUP_RES: /* ISO 18092 - 12.5.2.2 */ + case NFCIP_CMD_PSL_REQ: + case NFCIP_CMD_PSL_RES: + + *(--txBlock) = gNfcip.cfg.did; /* DID */ + break; + + /*******************************************************************************/ + case NFCIP_CMD_RLS_REQ: + case NFCIP_CMD_RLS_RES: + case NFCIP_CMD_DSL_REQ: + case NFCIP_CMD_DSL_RES: + + /* Digital 1.0 - 14.8.1.1 & 14.9.1.1 & 14.10.1.1 Only add DID if not 0 */ + if( gNfcip.cfg.did != RFAL_NFCDEP_DID_NO ) + { + *(--txBlock) = gNfcip.cfg.did; /* DID */ + } + break; + + /*******************************************************************************/ + case NFCIP_CMD_DEP_REQ: + case NFCIP_CMD_DEP_RES: + + /* Compute optional PFB bits */ + if (gNfcip.cfg.did != RFAL_NFCDEP_DID_NO) { pfb |= NFCIP_PFB_DID_BIT; } + if (gNfcip.cfg.nad != RFAL_NFCDEP_NAD_NO) { pfb |= NFCIP_PFB_NAD_BIT; } + if ((gNfcip.isTxChaining) && (nfcip_PFBisIPDU(pfb)) ) { pfb |= NFCIP_PFB_MI_BIT; } + + /* Store PFB for future handling */ + gNfcip.lastPFB = pfb; /* store PFB sent */ + + if( !nfcip_PFBisSATN(pfb) ) + { + gNfcip.lastPFBnATN = pfb; /* store last PFB different then ATN */ + } + + + /* Add NAD if it is to be supported */ + if( gNfcip.cfg.nad != RFAL_NFCDEP_NAD_NO ) + { + *(--txBlock) = gNfcip.cfg.nad; /* NAD */ + } + + /* Digital 1.0 - 14.8.1.1 & 14.8.1.1 Only add DID if not 0 */ + if( gNfcip.cfg.did != RFAL_NFCDEP_DID_NO ) + { + *(--txBlock) = gNfcip.cfg.did; /* DID */ + } + + *(--txBlock) = pfb; /* PFB */ + + + /* NCI 1.0 - Check if Empty frames are allowed */ + if( (paylLen == 0U) && nfcipIsEmptyDEPDisabled(gNfcip.cfg.oper) && nfcip_PFBisIPDU(pfb) ) + { + return ERR_PARAM; + } + break; + + /*******************************************************************************/ + default: + return ERR_PARAM; + } + + /*******************************************************************************/ + /* Prepend Header */ + /*******************************************************************************/ + *(--txBlock) = (uint8_t)cmd; /* CMD */ + *(--txBlock) = (uint8_t)( nfcipCmdIsReq(cmd) ? NFCIP_REQ : NFCIP_RES ); /* CMDType */ + + + txBufIt += paylLen + (uint16_t)((uint32_t)payloadBuf - (uint32_t)txBlock); /* Calculate overall buffer size */ + + + if( txBufIt > gNfcip.fsc ) /* Check if msg length violates the maximum payload size FSC */ + { + return ERR_NOTSUPP; + } + + /*******************************************************************************/ + return nfcipDataTx( txBlock, txBufIt, fwt ); +} + +/* + ****************************************************************************** + * GLOBAL FUNCTIONS + ****************************************************************************** + */ + +/*******************************************************************************/ +static void nfcipConfig( const rfalNfcDepConfigs * cfg ) +{ + if (cfg == NULL) + { + return; + } + + ST_MEMCPY(&gNfcip.cfg, cfg, sizeof(rfalNfcDepConfigs)); /* Copy given config to local */ + + gNfcip.cfg.to = MIN( RFAL_NFCDEP_WT_TRG_MAX, gNfcip.cfg.to); /* Ensure proper WT value */ + gNfcip.cfg.did = nfcip_DIDMax( gNfcip.cfg.did ); /* Ensure proper DID value */ + gNfcip.fsc = rfalNfcDepLR2FS( gNfcip.cfg.lr ); /* Calculate FSC based on given LR */ + + gNfcip.state = ( ( gNfcip.cfg.role == RFAL_NFCDEP_ROLE_TARGET) ? NFCIP_ST_TARG_WAIT_ATR : NFCIP_ST_INIT_IDLE ); +} + + +/*******************************************************************************/ +static ReturnCode nfcipRun( uint16_t *outActRxLen, bool *outIsChaining ) +{ + ReturnCode ret; + + ret = ERR_SYNTAX; + + nfcipLogD( " NFCIP Run() state: %d \r\n", gNfcip.state ); + + switch( gNfcip.state ) + { + /*******************************************************************************/ + case NFCIP_ST_IDLE: + case NFCIP_ST_INIT_DEP_IDLE: + case NFCIP_ST_TARG_DEP_IDLE: + case NFCIP_ST_TARG_DEP_SLEEP: + return ERR_NONE; + + /*******************************************************************************/ + case NFCIP_ST_INIT_DEP_TX: + + nfcipLogD( " NFCIP(I) Tx PNI: %d txLen: %d \r\n", gNfcip.pni, gNfcip.txBufLen ); + ret = nfcipTx( NFCIP_CMD_DEP_REQ, gNfcip.txBuf, &gNfcip.txBuf[gNfcip.txBufPaylPos], gNfcip.txBufLen, nfcip_PFBIPDU( gNfcip.pni ), (gNfcip.cfg.fwt + gNfcip.cfg.dFwt) ); + + switch( ret ) + { + case ERR_PARAM: + default: + gNfcip.state = NFCIP_ST_INIT_DEP_IDLE; + return ret; + + case ERR_NONE: + gNfcip.state = NFCIP_ST_INIT_DEP_RX; + break; + } + /* fall through */ + + /*******************************************************************************/ + case NFCIP_ST_INIT_DEP_RX: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + ret = nfcipDataRx( false ); + + if( ret != ERR_BUSY ) + { + ret = nfcipInitiatorHandleDEP( ret, *gNfcip.rxRcvdLen, outActRxLen, outIsChaining ); + } + + break; + + /*******************************************************************************/ + case NFCIP_ST_TARG_DEP_RTOX: + + if( !nfcipTimerisExpired( gNfcip.RTOXTimer ) ) /* Do nothing until RTOX timer has expired */ + { + return ERR_BUSY; + } + + /* If we cannot send a RTOX raise a Timeout error so that we do not + * hold the field On forever in AP2P */ + if( nfcipIsRTOXReqDisabled(gNfcip.cfg.oper) ) + { + /* We should reEnable Rx, and measure time between our field Off to + * either report link loss or recover #287 */ + nfcipLogI( " NFCIP(T) RTOX not sent due to config, NOT reenabling Rx \r\n" ); + return ERR_TIMEOUT; + } + + if( gNfcip.cntRTOXRetrys++ > NFCIP_MAX_RTOX_RETRYS ) /* Check maximum consecutive RTOX requests */ + { + return ERR_PROTO; + } + + nfcipLogI( " NFCIP(T) RTOX sent \r\n" ); + + gNfcip.lastRTOX = nfcip_RTOXTargMax(gNfcip.cfg.to); /* Calculate requested RTOX value, and send it */ + EXIT_ON_ERR( ret, nfcipDEPControlMsg( nfcip_PFBSPDU_TO(), gNfcip.lastRTOX ) ); + + /* Set waiting for RTOX Ack Flag */ + gNfcip.isWait4RTOX = true; + + gNfcip.state = NFCIP_ST_TARG_DEP_RX; /* Go back to Rx to process RTOX ack */ + return ERR_BUSY; + + /*******************************************************************************/ + case NFCIP_ST_TARG_DEP_TX: + + nfcipLogD( " NFCIP(T) Tx PNI: %d txLen: %d \r\n", gNfcip.pni, gNfcip.txBufLen ); + ret = nfcipTx( NFCIP_CMD_DEP_RES, gNfcip.txBuf, &gNfcip.txBuf[gNfcip.txBufPaylPos], gNfcip.txBufLen, nfcip_PFBIPDU( gNfcip.pni ), NFCIP_NO_FWT ); + + /* Clear flags */ + gNfcip.isTxPending = false; + gNfcip.isWait4RTOX = false; + + /* Digital 1.0 14.12.3.4 Increment the current PNI after Tx */ + gNfcip.pni = nfcip_PNIInc( gNfcip.pni ); + + switch( ret ) + { + case ERR_PARAM: + default: + gNfcip.state = NFCIP_ST_TARG_DEP_IDLE; /* Upon Tx error, goto IDLE state */ + return ret; + + case ERR_NONE: + gNfcip.state = NFCIP_ST_TARG_DEP_RX; /* All OK, goto Rx state */ + break; + } + /* fall through */ + + /*******************************************************************************/ + case NFCIP_ST_TARG_DEP_RX: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + if( gNfcip.isReqPending ) /* if already has Data should be from a DEP from nfcipTargetHandleActivation() */ + { + nfcipLogD( " NFCIP(T) Skipping Rx Using DEP from Activation \r\n" ); + + gNfcip.isReqPending = false; + ret = ERR_NONE; + } + else + { + ret = nfcipDataRx( false ); + } + + if( ret != ERR_BUSY ) + { + ret = nfcipTargetHandleRX( ret, outActRxLen, outIsChaining ); + } + + break; + + /*******************************************************************************/ + default: + /* MISRA 16.4: no empty default statement (a comment being enough) */ + break; + } + return ret; +} + + +/*******************************************************************************/ +void rfalNfcDepSetDeactivatingCallback( rfalNfcDepDeactCallback pFunc ) +{ + gNfcip.isDeactivating = pFunc; +} + + +/*******************************************************************************/ +void rfalNfcDepInitialize( void ) +{ + nfcipLogD( " NFCIP Ini() \r\n" ); + + gNfcip.state = NFCIP_ST_IDLE; + gNfcip.isDeactivating = NULL; + + gNfcip.isTxPending = false; + gNfcip.isWait4RTOX = false; + gNfcip.isReqPending = false; + + + gNfcip.cfg.oper = (RFAL_NFCDEP_OPER_FULL_MI_DIS | RFAL_NFCDEP_OPER_EMPTY_DEP_EN | RFAL_NFCDEP_OPER_ATN_EN | RFAL_NFCDEP_OPER_RTOX_REQ_EN); + + gNfcip.cfg.did = RFAL_NFCDEP_DID_NO; + gNfcip.cfg.nad = RFAL_NFCDEP_NAD_NO; + + gNfcip.cfg.br = RFAL_NFCDEP_Bx_NO_HIGH_BR; + gNfcip.cfg.bs = RFAL_NFCDEP_Bx_NO_HIGH_BR; + + gNfcip.cfg.lr = RFAL_NFCDEP_LR_254; + gNfcip.fsc = rfalNfcDepLR2FS( gNfcip.cfg.lr ); + + gNfcip.cfg.gbLen = 0; + + gNfcip.cfg.fwt = RFAL_NFCDEP_MAX_FWT; + gNfcip.cfg.dFwt = RFAL_NFCDEP_MAX_FWT; + + gNfcip.pni = 0; + gNfcip.RTOXTimer = 0; + + nfcipClearCounters(); +} + + +/*******************************************************************************/ +static void nfcipSetDEPParams( rfalNfcDepDEPParams *DEPParams ) +{ + nfcipLogD( " NFCIP SetDEP() txLen: %d \r\n", DEPParams->txBufLen ); + + gNfcip.isTxChaining = DEPParams->txChaining; + gNfcip.txBuf = DEPParams->txBuf; + gNfcip.rxBuf = DEPParams->rxBuf; + gNfcip.txBufLen = DEPParams->txBufLen; + gNfcip.rxBufLen = DEPParams->rxBufLen; + gNfcip.txBufPaylPos = DEPParams->txBufPaylPos; + gNfcip.rxBufPaylPos = DEPParams->rxBufPaylPos; + + if( DEPParams->did != RFAL_NFCDEP_DID_KEEP ) + { + gNfcip.cfg.did = nfcip_DIDMax( DEPParams->did ); + } + + gNfcip.cfg.fwt = DEPParams->fwt; + gNfcip.cfg.dFwt = DEPParams->dFwt; + gNfcip.fsc = DEPParams->fsc; + + + + if(gNfcip.cfg.role == RFAL_NFCDEP_ROLE_TARGET) + { + /* If there's any data to be sent go for Tx */ + if(DEPParams->txBufLen > 0U) + { + /* Ensure that an RTOX Ack is not being expected at moment */ + if( !gNfcip.isWait4RTOX ) + { + gNfcip.state = NFCIP_ST_TARG_DEP_TX; + return; + } + else + { + /* If RTOX Ack is expected, signal a pending Tx to be transmitted right after */ + gNfcip.isTxPending = true; + nfcipLogW( " NFCIP(T) Waiting RTOX, queueing outgoing DEP Block \r\n" ); + } + } + + /*Digital 1.0 14.12.4.1 In target mode the first PDU MUST be sent by the Initiator */ + gNfcip.state = NFCIP_ST_TARG_DEP_RX; + return; + } + + /* New data TxRx request clear previous error counters for consecutive TxRx without reseting communication/protocol layer*/ + nfcipClearCounters(); + + gNfcip.state = NFCIP_ST_INIT_DEP_TX; +} + + +/*******************************************************************************/ +bool rfalNfcDepTargetRcvdATR( void ) +{ + return ( (gNfcip.cfg.role == RFAL_NFCDEP_ROLE_TARGET) && nfcipIsTarget(gNfcip.state) && (gNfcip.state > NFCIP_ST_TARG_WAIT_ATR) ); +} + + +/*******************************************************************************/ +bool rfalNfcDepIsAtrReq( const uint8_t* buf, uint16_t bufLen, uint8_t* nfcid3 ) +{ + uint8_t msgIt; + + msgIt = 0; + + if ( (bufLen < RFAL_NFCDEP_ATRREQ_MIN_LEN) || (bufLen > RFAL_NFCDEP_ATRREQ_MAX_LEN) ) + { + return false; + } + + if ( buf[msgIt++] != NFCIP_REQ ) + { + return false; + } + + if( buf[msgIt++] != (uint8_t)NFCIP_CMD_ATR_REQ ) + { + return false; + } + + /* Output NFID3 if requested */ + if( nfcid3 != NULL ) + { + ST_MEMCPY( nfcid3, &buf[RFAL_NFCDEP_ATR_REQ_NFCID3_POS], RFAL_NFCDEP_NFCID3_LEN ); + } + + return true; +} + + +/*******************************************************************************/ +static ReturnCode nfcipTargetHandleActivation( rfalNfcDepDevice *nfcDepDev, uint8_t *outBRS ) +{ + ReturnCode ret; + uint8_t msgIt; + uint8_t txBuf[RFAL_NFCDEP_HEADER_PAD + NFCIP_PSLRES_LEN]; + + /*******************************************************************************/ + /* Check if we are in correct state */ + /*******************************************************************************/ + if( gNfcip.state != NFCIP_ST_TARG_WAIT_ACTV ) + { + return ERR_WRONG_STATE; + } + + + /*******************************************************************************/ + /* Check required parameters */ + /*******************************************************************************/ + if( outBRS == NULL ) + { + return ERR_PARAM; + } + + /*******************************************************************************/ + /* Wait and process incoming cmd (PSL / DEP) */ + /*******************************************************************************/ + ret = nfcipDataRx( false ); + + if( ret != ERR_NONE ) + { + return ret; + } + + msgIt = 0; + *outBRS = RFAL_NFCDEP_BRS_MAINTAIN; /* set out BRS to be maintained */ + + msgIt++; /* Skip LEN byte */ + + if ( gNfcip.rxBuf[msgIt++] != NFCIP_REQ ) + { + return ERR_PROTO; + } + + if( gNfcip.rxBuf[msgIt] == (uint8_t)NFCIP_CMD_PSL_REQ ) + { + msgIt++; + + if( gNfcip.rxBuf[msgIt++] != gNfcip.cfg.did ) /* Checking DID */ + { + return ERR_PROTO; + } + + nfcipLogI( " NFCIP(T) PSL REQ rcvd \r\n" ); + + *outBRS = gNfcip.rxBuf[msgIt++]; /* assign output BRS value */ + + /* Store FSL(LR) and update current config */ + gNfcip.cfg.lr = (gNfcip.rxBuf[msgIt++] & RFAL_NFCDEP_LR_VAL_MASK); + gNfcip.fsc = rfalNfcDepLR2FS( gNfcip.cfg.lr ); + + /*******************************************************************************/ + /* Update NFC-DDE Device info */ + if( nfcDepDev != NULL ) + { + /* Update Bitrate info */ + /* PRQA S 4342 2 # MISRA 10.5 - Layout of enum rfalBitRate and definition of rfalNfcDepBRS2DSI guarantee no invalid enum values to be created */ + nfcDepDev->info.DSI = (rfalBitRate)rfalNfcDepBRS2DSI( *outBRS ); /* DSI codes the bit rate from Initiator to Target */ + nfcDepDev->info.DRI = (rfalBitRate)rfalNfcDepBRS2DRI( *outBRS ); /* DRI codes the bit rate from Target to Initiator */ + + /* Update Length Reduction and Frame Size */ + nfcDepDev->info.LR = gNfcip.cfg.lr; + nfcDepDev->info.FS = gNfcip.fsc; + + /* Update PPi byte */ + nfcDepDev->activation.Initiator.ATR_REQ.PPi &= ~RFAL_NFCDEP_PP_LR_MASK; + nfcDepDev->activation.Initiator.ATR_REQ.PPi |= rfalNfcDepLR2PP( gNfcip.cfg.lr ); + } + + EXIT_ON_ERR( ret, nfcipTx( NFCIP_CMD_PSL_RES, txBuf, NULL, 0, 0, NFCIP_NO_FWT ) ); + } + else + { + if( gNfcip.rxBuf[msgIt] == (uint8_t)NFCIP_CMD_DEP_REQ ) + { + msgIt++; + + /*******************************************************************************/ + /* Digital 1.0 14.12.3.1 PNI must be initialized to 0 */ + if( nfcip_PBF_PNI( gNfcip.rxBuf[msgIt] ) != 0U ) + { + return ERR_PROTO; + } + + /*******************************************************************************/ + /* Digital 1.0 14.8.2.1 check if DID is expected and match -> Protocol Error */ + if( nfcip_PFBhasDID( gNfcip.rxBuf[ msgIt] ) ) + { + if( gNfcip.rxBuf[++msgIt] != gNfcip.cfg.did ) + { + return ERR_PROTO; + } + } + else if( gNfcip.cfg.did != RFAL_NFCDEP_DID_NO ) /* DID expected but not rcv */ + { + return ERR_PROTO; + } + else + { + /* MISRA 15.7 - Empty else */ + } + } + + /* Signal Request pending to be digested on normal Handling (DEP_REQ, DSL_REQ, RLS_REQ) */ + gNfcip.isReqPending = true; + } + + gNfcip.state = NFCIP_ST_TARG_DEP_RX; + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepATR( const rfalNfcDepAtrParam* param, rfalNfcDepAtrRes *atrRes, uint8_t* atrResLen ) +{ + ReturnCode ret; + rfalNfcDepConfigs cfg; + uint16_t rxLen; + uint8_t msgIt; + uint8_t txBuf[RFAL_NFCDEP_ATRREQ_MAX_LEN]; + uint8_t rxBuf[NFCIP_ATRRES_BUF_LEN]; + + + if( (param == NULL) || (atrRes == NULL) || (atrResLen == NULL) ) + { + return ERR_PARAM; + } + + /*******************************************************************************/ + /* Configure NFC-DEP layer */ + /*******************************************************************************/ + + cfg.did = param->DID; + cfg.nad = param->NAD; + cfg.fwt = RFAL_NFCDEP_MAX_FWT; + cfg.dFwt = RFAL_NFCDEP_MAX_FWT; + cfg.br = param->BR; + cfg.bs = param->BS; + cfg.lr = param->LR; + cfg.to = RFAL_NFCDEP_WT_TRG_MAX; /* Not used in Initiator mode */ + + + cfg.gbLen = param->GBLen; + if( cfg.gbLen > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY( cfg.gb, param->GB, cfg.gbLen ); + } + + cfg.nfcidLen = param->nfcidLen; + if( cfg.nfcidLen > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY( cfg.nfcid, param->nfcid, cfg.nfcidLen ); + } + + cfg.role = RFAL_NFCDEP_ROLE_INITIATOR; + cfg.oper = param->operParam; + cfg.commMode = param->commMode; + + rfalNfcDepInitialize(); + nfcipConfig( &cfg ); + + /*******************************************************************************/ + /* Send ATR_REQ */ + /*******************************************************************************/ + + EXIT_ON_ERR( ret, nfcipTxRx(NFCIP_CMD_ATR_REQ, txBuf, nfcipRWTActivation(), NULL, 0, rxBuf, NFCIP_ATRRES_BUF_LEN, &rxLen ) ); + + + /*******************************************************************************/ + /* ATR sent, check response */ + /*******************************************************************************/ + msgIt = 0; + rxLen = ((uint16_t)rxBuf[msgIt++] - RFAL_NFCDEP_LEN_LEN); /* use LEN byte */ + + if( (rxLen < RFAL_NFCDEP_ATRRES_MIN_LEN) || (rxLen > RFAL_NFCDEP_ATRRES_MAX_LEN) ) /* Checking length: ATR_RES */ + { + return ERR_PROTO; + } + + if( rxBuf[msgIt++] != NFCIP_RES ) /* Checking if is a response*/ + { + return ERR_PROTO; + } + + if( rxBuf[msgIt++] != (uint8_t)NFCIP_CMD_ATR_RES ) /* Checking if is a ATR RES */ + { + return ERR_PROTO; + } + + ST_MEMCPY( (uint8_t*)atrRes, (rxBuf + RFAL_NFCDEP_LEN_LEN), rxLen ); + *atrResLen = (uint8_t)rxLen; + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepPSL( uint8_t BRS, uint8_t FSL ) +{ + ReturnCode ret; + uint16_t rxLen; + uint8_t msgIt; + uint8_t txBuf[NFCIP_PSLREQ_LEN + NFCIP_PSLPAY_LEN]; + uint8_t rxBuf[NFCIP_PSLRES_LEN]; + + msgIt = NFCIP_PSLREQ_LEN; + + txBuf[msgIt++] = BRS; + txBuf[msgIt++] = FSL; + + /*******************************************************************************/ + /* Send PSL REQ and wait for response */ + /*******************************************************************************/ + EXIT_ON_ERR( ret, nfcipTxRx( NFCIP_CMD_PSL_REQ, txBuf, nfcipRWTActivation(), &txBuf[NFCIP_PSLREQ_LEN], (msgIt - NFCIP_PSLREQ_LEN), rxBuf, NFCIP_PSLRES_LEN, &rxLen ) ); + + + /*******************************************************************************/ + /* PSL sent, check response */ + /*******************************************************************************/ + msgIt = 0; + rxLen = (uint16_t)(rxBuf[msgIt++]); /* use LEN byte */ + + if( rxLen < NFCIP_PSLRES_LEN ) /* Checking length: LEN + RLS_RES */ + { + return ERR_PROTO; + } + + if( rxBuf[msgIt++] != NFCIP_RES ) /* Checking if is a response */ + { + return ERR_PROTO; + } + + if( rxBuf[msgIt++] != (uint8_t)NFCIP_CMD_PSL_RES ) /* Checking if is a PSL RES */ + { + return ERR_PROTO; + } + + if( rxBuf[msgIt++] != gNfcip.cfg.did ) /* Checking DID */ + { + return ERR_PROTO; + } + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepDSL( void ) +{ + ReturnCode ret; + uint8_t txBuf[ RFAL_NFCDEP_HEADER_PAD + NFCIP_DSLREQ_LEN]; + uint8_t rxBuf[NFCIP_DSLRES_LEN]; + uint8_t rxMsgIt; + uint16_t rxLen = 0; + + if( gNfcip.cfg.role == RFAL_NFCDEP_ROLE_TARGET ) + { + return ERR_NONE; /* Target has no deselect procedure */ + } + + /* Repeating a DSL REQ is optional, not doing it */ + EXIT_ON_ERR( ret, nfcipTxRx( NFCIP_CMD_DSL_REQ, txBuf, nfcipRWTActivation(), NULL, 0, rxBuf, RFAL_NFCDEP_ATRRES_MAX_LEN, &rxLen ) ); + + /*******************************************************************************/ + rxMsgIt = 0; + + if( rxBuf[rxMsgIt++] < NFCIP_DSLRES_MIN ) /* Checking length: LEN + DSL_RES */ + { + return ERR_PROTO; + } + + if( rxBuf[rxMsgIt++] != NFCIP_RES ) /* Checking if is a response */ + { + return ERR_PROTO; + } + + if( rxBuf[rxMsgIt++] != (uint8_t)NFCIP_CMD_DSL_RES ) /* Checking if is DSL RES */ + { + return ERR_PROTO; + } + + if( gNfcip.cfg.did != RFAL_NFCDEP_DID_NO ) + { + if ( rxBuf[rxMsgIt++] != gNfcip.cfg.did ) + { + return ERR_PROTO; + } + } + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepRLS( void ) +{ + ReturnCode ret; + uint8_t txBuf[RFAL_NFCDEP_HEADER_PAD + NFCIP_RLSREQ_LEN]; + uint8_t rxBuf[NFCIP_RLSRES_LEN]; + uint8_t rxMsgIt; + uint16_t rxLen = 0; + + if ( gNfcip.cfg.role == RFAL_NFCDEP_ROLE_TARGET ) /* Target has no release procedure */ + { + return ERR_NONE; + } + + /* Repeating a RLS REQ is optional, not doing it */ + EXIT_ON_ERR( ret, nfcipTxRx( NFCIP_CMD_RLS_REQ, txBuf, nfcipRWTActivation(), NULL, 0, rxBuf, RFAL_NFCDEP_ATRRES_MAX_LEN, &rxLen ) ); + + /*******************************************************************************/ + rxMsgIt = 0; + + if( rxBuf[rxMsgIt++] < NFCIP_RLSRES_MIN ) /* Checking length: LEN + RLS_RES */ + { + return ERR_PROTO; + } + + if( rxBuf[rxMsgIt++] != NFCIP_RES ) /* Checking if is a response */ + { + return ERR_PROTO; + } + + if( rxBuf[rxMsgIt++] != (uint8_t)NFCIP_CMD_RLS_RES ) /* Checking if is RLS RES */ + { + return ERR_PROTO; + } + + if( gNfcip.cfg.did != RFAL_NFCDEP_DID_NO ) + { + if ( rxBuf[rxMsgIt++] != gNfcip.cfg.did ) + { + return ERR_PROTO; + } + } + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepInitiatorHandleActivation( rfalNfcDepAtrParam* param, rfalBitRate desiredBR, rfalNfcDepDevice* nfcDepDev ) +{ + ReturnCode ret; + uint8_t maxRetyrs; + uint8_t PSL_BRS; + uint8_t PSL_FSL; + bool sendPSL; + + if( (param == NULL) || (nfcDepDev == NULL) ) + { + return ERR_PARAM; + } + + param->NAD = RFAL_NFCDEP_NAD_NO; /* Digital 1.1 16.6.2.9 Initiator SHALL NOT use NAD */ + maxRetyrs = NFCIP_ATR_RETRY_MAX; + + /*******************************************************************************/ + /* Send ATR REQ and wait for response */ + /*******************************************************************************/ + do{ /* Upon transmission error ATR REQ should be retried */ + + ret = rfalNfcDepATR( param, &nfcDepDev->activation.Target.ATR_RES, &nfcDepDev->activation.Target.ATR_RESLen ); + + if( nfcipIsTransmissionError(ret) ) + { + continue; + } + break; + } + while( (maxRetyrs--) != 0U ); + + if( ret != ERR_NONE ) + { + return ret; + } + + /*******************************************************************************/ + /* Compute NFC-DEP device with ATR_RES */ + /*******************************************************************************/ + nfcDepDev->info.GBLen = (nfcDepDev->activation.Target.ATR_RESLen - RFAL_NFCDEP_ATRRES_MIN_LEN); + nfcDepDev->info.DID = nfcDepDev->activation.Target.ATR_RES.DID; + nfcDepDev->info.NAD = RFAL_NFCDEP_NAD_NO; /* Digital 1.1 16.6.3.11 Initiator SHALL ignore b1 of PPt */ + nfcDepDev->info.LR = rfalNfcDepPP2LR( nfcDepDev->activation.Target.ATR_RES.PPt ); + nfcDepDev->info.FS = rfalNfcDepLR2FS( nfcDepDev->info.LR ); + nfcDepDev->info.WT = (nfcDepDev->activation.Target.ATR_RES.TO & RFAL_NFCDEP_WT_MASK); + nfcDepDev->info.FWT = rfalNfcDepCalculateRWT( nfcDepDev->info.WT ); + nfcDepDev->info.dFWT = RFAL_NFCDEP_WT_DELTA; + + rfalGetBitRate( &nfcDepDev->info.DSI, &nfcDepDev->info.DRI ); + + + + /*******************************************************************************/ + /* Check if a PSL needs to be sent */ + /*******************************************************************************/ + sendPSL = false; + PSL_BRS = rfalNfcDepDx2BRS( nfcDepDev->info.DSI ); /* Set current bit rate divisor on both directions */ + PSL_FSL = nfcDepDev->info.LR; /* Set current Frame Size */ + + + + /* Activity 1.0 9.4.4.15 & 9.4.6.3 NFC-DEP Activation PSL + * Activity 2.0 9.4.4.17 & 9.4.6.6 NFC-DEP Activation PSL + * + * PSL_REQ shall only be sent if desired bit rate is different from current (Activity 1.0) + * PSL_REQ shall be sent to update LR or bit rate (Activity 2.0) + * */ + +#if 0 /* PSL due to LR is disabled, can be enabled if desired*/ + /*******************************************************************************/ + /* Check Frame Size */ + /*******************************************************************************/ + if( gNfcip.cfg.lr < nfcDepDev->info.LR ) /* If our Length reduction is smaller */ + { + sendPSL = true; + + nfcDepDev->info.LR = MIN( nfcDepDev->info.LR, gNfcip.cfg.lr ); + + gNfcip.cfg.lr = nfcDepDev->info.LR; /* Update nfcip LR to be used */ + gNfcip.fsc = rfalNfcDepLR2FS( gNfcip.cfg.lr ); /* Update nfcip FSC to be used */ + + PSL_FSL = gNfcip.cfg.lr; /* Set LR to be sent */ + + nfcipLogI( " NFCIP(I) Frame Size differ, PSL new fsc: %d \r\n", gNfcip.fsc ); + } +#endif + + + /*******************************************************************************/ + /* Check Baud rates */ + /*******************************************************************************/ + if( nfcDepDev->info.DSI != desiredBR ) /* if desired BR is different */ + { + /* || (target->brt != RFAL_NFCDEP_Bx_NO_HIGH_BR) || (target->bst != RFAL_NFCDEP_Bx_NO_HIGH_BR) */ /* if target supports higher BR, must send PSL? */ + if( nfcipDxIsSupported( (uint8_t)desiredBR, nfcDepDev->activation.Target.ATR_RES.BRt, nfcDepDev->activation.Target.ATR_RES.BSt ) ) /* if desired BR is supported */ /* MISRA 13.5 */ + { + sendPSL = true; + PSL_BRS = rfalNfcDepDx2BRS( desiredBR ); + + nfcipLogI( " NFCIP(I) BR differ, PSL BR: 0x%02X \r\n", PSL_BRS ); + } + } + + + /*******************************************************************************/ + if( sendPSL ) + { + /*******************************************************************************/ + /* Send PSL REQ and wait for response */ + /*******************************************************************************/ + EXIT_ON_ERR( ret, rfalNfcDepPSL(PSL_BRS, PSL_FSL) ); + + /* Check if bit rate has been changed */ + if( nfcDepDev->info.DSI != desiredBR ) + { + /* Check if device was in Passive NFC-A and went to higher bit rates, use NFC-F */ + if( (nfcDepDev->info.DSI == RFAL_BR_106) && (gNfcip.cfg.commMode == RFAL_NFCDEP_COMM_PASSIVE) ) + { + + #if RFAL_FEATURE_NFCF + /* If Passive initialize NFC-F module */ + rfalNfcfPollerInitialize( desiredBR ); + #else /* RFAL_FEATURE_NFCF */ + return ERR_NOTSUPP; + #endif /* RFAL_FEATURE_NFCF */ + + } + + nfcDepDev->info.DRI = desiredBR; /* DSI Bit Rate coding from Initiator to Target */ + nfcDepDev->info.DSI = desiredBR; /* DRI Bit Rate coding from Target to Initiator */ + + rfalSetBitRate( nfcDepDev->info.DSI, nfcDepDev->info.DRI ); + } + + + return ERR_NONE; /* PSL has been sent */ + } + + return ERR_NONE; /* No PSL has been sent */ +} + + +/*******************************************************************************/ +uint32_t rfalNfcDepCalculateRWT( uint8_t wt ) +{ + /* Digital 1.0 14.6.3.8 & Digital 1.1 16.6.3.9 */ + /* Digital 1.1 16.6.3.9 treat all RFU values as WT=14 */ + uint8_t responseWaitTime = MIN( RFAL_NFCDEP_WT_INI_MAX, wt ); + + return (uint32_t)rfalNfcDepWT2RWT(responseWaitTime); +} + + + +/*******************************************************************************/ +static ReturnCode nfcipDataTx( uint8_t* txBuf, uint16_t txBufLen, uint32_t fwt ) +{ + return rfalTransceiveBlockingTx( txBuf, txBufLen, gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen, (RFAL_TXRX_FLAGS_DEFAULT | (uint32_t)RFAL_TXRX_FLAGS_NFCIP1_ON), ((fwt == NFCIP_NO_FWT) ? RFAL_FWT_NONE : fwt) ); +} + + +/*******************************************************************************/ +static ReturnCode nfcipDataRx( bool blocking ) +{ + ReturnCode ret; + + /* Perform Rx either blocking or non-blocking */ + if( blocking ) + { + ret = rfalTransceiveBlockingRx(); + } + else + { + ret = rfalGetTransceiveStatus(); + } + + if( ret != ERR_BUSY ) + { + if( gNfcip.rxRcvdLen != NULL ) + { + (*gNfcip.rxRcvdLen) = rfalConvBitsToBytes( *gNfcip.rxRcvdLen ); + + if( (ret == ERR_NONE) && (gNfcip.rxBuf != NULL) ) + { + /* Digital 1.1 16.4.1.3 - Length byte LEN SHALL have a value between 3 and 255 -> otherwise treat as Transmission Error * + * - Ensure that actual received and frame length do match, otherwise treat as Transmission error */ + if( (*gNfcip.rxRcvdLen != (uint16_t)*gNfcip.rxBuf) || (*gNfcip.rxRcvdLen < RFAL_NFCDEP_LEN_MIN) || (*gNfcip.rxRcvdLen > RFAL_NFCDEP_LEN_MAX) ) + { + return ERR_FRAMING; + } + } + } + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepListenStartActivation( const rfalNfcDepTargetParam *param, const uint8_t *atrReq, uint16_t atrReqLength, rfalNfcDepListenActvParam rxParam ) +{ + ReturnCode ret; + rfalNfcDepConfigs cfg; + + + if( (param == NULL) || (atrReq == NULL) || (rxParam.rxLen == NULL) ) + { + return ERR_PARAM; + } + + + /*******************************************************************************/ + /* Check whether is a valid ATR_REQ Compute NFC-DEP device */ + if( !rfalNfcDepIsAtrReq( atrReq, atrReqLength, NULL ) ) + { + return ERR_PARAM; + } + + rxParam.nfcDepDev->activation.Initiator.ATR_REQLen = (uint8_t)atrReqLength; /* nfcipIsAtrReq() is already checking Min and Max buffer lengths */ + if( atrReqLength > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY( (uint8_t*)&rxParam.nfcDepDev->activation.Initiator.ATR_REQ, atrReq, atrReqLength ); + } + + rxParam.nfcDepDev->info.GBLen = (uint8_t)(atrReqLength - RFAL_NFCDEP_ATRREQ_MIN_LEN); + rxParam.nfcDepDev->info.DID = rxParam.nfcDepDev->activation.Initiator.ATR_REQ.DID; + rxParam.nfcDepDev->info.NAD = RFAL_NFCDEP_NAD_NO; /* Digital 1.1 16.6.2.9 Initiator SHALL NOT use NAD */ + rxParam.nfcDepDev->info.LR = rfalNfcDepPP2LR( rxParam.nfcDepDev->activation.Initiator.ATR_REQ.PPi ); + rxParam.nfcDepDev->info.FS = rfalNfcDepLR2FS( rxParam.nfcDepDev->info.LR ); + rxParam.nfcDepDev->info.WT = 0; + rxParam.nfcDepDev->info.FWT = NFCIP_NO_FWT; + rxParam.nfcDepDev->info.dFWT = NFCIP_NO_FWT; + + rfalGetBitRate( &rxParam.nfcDepDev->info.DSI, &rxParam.nfcDepDev->info.DRI ); + + + /* Store Device Info location, updated upon a PSL */ + gNfcip.nfcDepDev = rxParam.nfcDepDev; + + + /*******************************************************************************/ + cfg.did = rxParam.nfcDepDev->activation.Initiator.ATR_REQ.DID; + cfg.nad = RFAL_NFCDEP_NAD_NO; + + cfg.fwt = RFAL_NFCDEP_MAX_FWT; + cfg.dFwt = RFAL_NFCDEP_MAX_FWT; + + cfg.br = param->brt; + cfg.bs = param->bst; + + cfg.lr = rfalNfcDepPP2LR(param->ppt); + + cfg.gbLen = param->GBtLen; + if( cfg.gbLen > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY(cfg.gb, param->GBt, cfg.gbLen); + } + + cfg.nfcidLen = RFAL_NFCDEP_NFCID3_LEN; + ST_MEMCPY(cfg.nfcid, param->nfcid3, RFAL_NFCDEP_NFCID3_LEN); + + cfg.to = param->to; + + cfg.role = RFAL_NFCDEP_ROLE_TARGET; + cfg.oper = param->operParam; + cfg.commMode = param->commMode; + + rfalNfcDepInitialize(); + nfcipConfig( &cfg ); + + + /*******************************************************************************/ + /* Reply with ATR RES to Initiator */ + /*******************************************************************************/ + gNfcip.rxBuf = (uint8_t*)rxParam.rxBuf; + gNfcip.rxBufLen = sizeof(rfalNfcDepBufFormat); + gNfcip.rxRcvdLen = rxParam.rxLen; + gNfcip.rxBufPaylPos = RFAL_NFCDEP_DEPREQ_HEADER_LEN; + gNfcip.isChaining = rxParam.isRxChaining; + gNfcip.txBufPaylPos = RFAL_NFCDEP_DEPREQ_HEADER_LEN; + + EXIT_ON_ERR( ret, nfcipTx( NFCIP_CMD_ATR_RES, (uint8_t*) gNfcip.rxBuf, NULL, 0, 0, NFCIP_NO_FWT ) ); + + gNfcip.state = NFCIP_ST_TARG_WAIT_ACTV; + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepListenGetActivationStatus( void ) +{ + ReturnCode err; + uint8_t BRS; + + BRS = RFAL_NFCDEP_BRS_MAINTAIN; + + err = nfcipTargetHandleActivation( gNfcip.nfcDepDev, &BRS ); + + switch (err) + { + case ERR_NONE: + + if( BRS != RFAL_NFCDEP_BRS_MAINTAIN ) + { + /* DSI codes the bit rate from Initiator to Target */ + /* DRI codes the bit rate from Target to Initiator */ + + if( gNfcip.cfg.commMode == RFAL_NFCDEP_COMM_ACTIVE ) + { + EXIT_ON_ERR( err, rfalSetMode( RFAL_MODE_LISTEN_ACTIVE_P2P, gNfcip.nfcDepDev->info.DRI, gNfcip.nfcDepDev->info.DSI )); + } + else + { + EXIT_ON_ERR( err, rfalSetMode( ((RFAL_BR_106 == gNfcip.nfcDepDev->info.DRI) ? RFAL_MODE_LISTEN_NFCA : RFAL_MODE_LISTEN_NFCF), gNfcip.nfcDepDev->info.DRI, gNfcip.nfcDepDev->info.DSI )); + } + } + break; + + case ERR_BUSY: + // do nothing + break; + + case ERR_PROTO: + default: + // re-enable receiving of data + nfcDepReEnableRx( gNfcip.rxBuf, gNfcip.rxBufLen, gNfcip.rxRcvdLen ); + break; + } // if (no err) + + return err; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepStartTransceive( rfalNfcDepTxRxParam *param ) +{ + rfalNfcDepDEPParams nfcDepParams; + + nfcDepParams.txBuf = (uint8_t *)param->txBuf; + nfcDepParams.txBufLen = param->txBufLen; + nfcDepParams.txChaining = param->isTxChaining; + nfcDepParams.txBufPaylPos = RFAL_NFCDEP_DEPREQ_HEADER_LEN; /* position in txBuf where actual outgoing data is located */ + nfcDepParams.did = RFAL_NFCDEP_DID_KEEP; + nfcDepParams.rxBufPaylPos = RFAL_NFCDEP_DEPREQ_HEADER_LEN; + nfcDepParams.rxBuf = (uint8_t *)param->rxBuf; + nfcDepParams.rxBufLen = sizeof(rfalNfcDepBufFormat); + nfcDepParams.fsc = param->FSx; + nfcDepParams.fwt = param->FWT; + nfcDepParams.dFwt = param->dFWT; + + gNfcip.rxRcvdLen = param->rxLen; + gNfcip.isChaining = param->isRxChaining; + + nfcipSetDEPParams(&nfcDepParams); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcDepGetTransceiveStatus( void ) +{ + return nfcipRun( gNfcip.rxRcvdLen, gNfcip.isChaining ); +} + +#endif /* RFAL_FEATURE_NFC_DEP */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_nfca.c b/Software/fab-reader2-c/components/rfal/Src/rfal_nfca.c new file mode 100644 index 0000000..03cb2e9 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_nfca.c @@ -0,0 +1,630 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfca.c + * + * \author Gustavo Patricio + * + * \brief Provides several NFC-A convenience methods and definitions + * + * It provides a Poller (ISO14443A PCD) interface and as well as + * some NFC-A Listener (ISO14443A PICC) helpers. + * + * The definitions and helpers methods provided by this module are only + * up to ISO14443-3 layer + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_nfca.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_NFCA + #define RFAL_FEATURE_NFCA false /* NFC-A module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_NFCA + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_NFCA_SLP_FWT rfalConvMsTo1fc(1) /*!< Check 1ms for any modulation ISO14443-3 6.4.3 */ +#define RFAL_NFCA_SLP_CMD 0x50U /*!< SLP cmd (byte1) Digital 1.1 6.9.1 & Table 20 */ +#define RFAL_NFCA_SLP_BYTE2 0x00U /*!< SLP byte2 Digital 1.1 6.9.1 & Table 20 */ +#define RFAL_NFCA_SLP_CMD_POS 0U /*!< SLP cmd position Digital 1.1 6.9.1 & Table 20 */ +#define RFAL_NFCA_SLP_BYTE2_POS 1U /*!< SLP byte2 position Digital 1.1 6.9.1 & Table 20 */ + +#define RFAL_NFCA_SDD_CT 0x88U /*!< Cascade Tag value Digital 1.1 6.7.2 */ +#define RFAL_NFCA_SDD_CT_LEN 1U /*!< Cascade Tag length */ + +#define RFAL_NFCA_SLP_REQ_LEN 2U /*!< SLP_REQ length */ + +#define RFAL_NFCA_SEL_CMD_LEN 1U /*!< SEL_CMD length */ +#define RFAL_NFCA_SEL_PAR_LEN 1U /*!< SEL_PAR length */ +#define RFAL_NFCA_SEL_SELPAR rfalNfcaSelPar(7U, 0U)/*!< SEL_PAR on Select is always with 4 data/nfcid */ +#define RFAL_NFCA_BCC_LEN 1U /*!< BCC length */ + +#define RFAL_NFCA_SDD_REQ_LEN (RFAL_NFCA_SEL_CMD_LEN + RFAL_NFCA_SEL_PAR_LEN) /*!< SDD_REQ length */ +#define RFAL_NFCA_SDD_RES_LEN (RFAL_NFCA_CASCADE_1_UID_LEN + RFAL_NFCA_BCC_LEN) /*!< SDD_RES length */ + +#define RFAL_NFCA_T_RETRANS 5U /*!< t RETRANSMISSION [3, 33]ms EMVCo 2.6 A.5 */ +#define RFAL_NFCA_N_RETRANS 2U /*!< Number of retries EMVCo 2.6 9.6.1.3 */ + + +/*! SDD_REQ (Select) Cascade Levels */ +enum +{ + RFAL_NFCA_SEL_CASCADE_L1 = 0, /*!< SDD_REQ Cascade Level 1 */ + RFAL_NFCA_SEL_CASCADE_L2 = 1, /*!< SDD_REQ Cascade Level 2 */ + RFAL_NFCA_SEL_CASCADE_L3 = 2 /*!< SDD_REQ Cascade Level 3 */ +}; + +/*! SDD_REQ (Select) request Cascade Level command Digital 1.1 Table 15 */ +enum +{ + RFAL_NFCA_CMD_SEL_CL1 = 0x93, /*!< SDD_REQ command Cascade Level 1 */ + RFAL_NFCA_CMD_SEL_CL2 = 0x95, /*!< SDD_REQ command Cascade Level 2 */ + RFAL_NFCA_CMD_SEL_CL3 = 0x97, /*!< SDD_REQ command Cascade Level 3 */ +}; + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ +#define rfalNfcaSelPar( nBy, nbi ) (uint8_t)((((nBy)<<4U) & 0xF0U) | ((nbi)&0x0FU) ) /*!< Calculates SEL_PAR with the bytes/bits to be sent */ +#define rfalNfcaCLn2SELCMD( cl ) (uint8_t)((uint8_t)(RFAL_NFCA_CMD_SEL_CL1) + (2U*(cl))) /*!< Calculates SEL_CMD with the given cascade level */ +#define rfalNfcaNfcidLen2CL( len ) ((len) / 5U) /*!< Calculates cascade level by the NFCID length */ + +/*! Executes the given Tx method (f) and if a Timeout error is detected it retries (rt) times performing a delay of (dl) in between */ +#define rfalNfcaTxRetry( r, f, rt, dl ) \ + { \ + uint8_t rts = (uint8_t)(rt); \ + do { \ + (r)=(f); \ + if (((rt)!=0U) && ((dl)!=0U)) { \ + platformDelay(dl); \ + } \ + } while( ((rts--) != 0U) && ((r)==ERR_TIMEOUT) ); \ + } + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! SLP_REQ (HLTA) format Digital 1.1 6.9.1 & Table 20 */ +typedef struct +{ + uint8_t frame[RFAL_NFCA_SLP_REQ_LEN]; /*!< SLP: 0x50 0x00 */ +} rfalNfcaSlpReq; + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +static uint8_t rfalNfcaCalculateBcc( const uint8_t* buf, uint8_t bufLen ); + + +/* + ****************************************************************************** + * LOCAL FUNCTIONS + ****************************************************************************** + */ + +static uint8_t rfalNfcaCalculateBcc( const uint8_t* buf, uint8_t bufLen ) +{ + uint8_t i; + uint8_t BCC; + + BCC = 0; + + /* BCC is XOR over first 4 bytes of the SDD_RES Digital 1.1 6.7.2 */ + for(i = 0; i < bufLen; i++) + { + BCC ^= buf[i]; + } + + return BCC; +} + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +ReturnCode rfalNfcaPollerInitialize( void ) +{ + ReturnCode ret; + + EXIT_ON_ERR( ret, rfalSetMode( RFAL_MODE_POLL_NFCA, RFAL_BR_106, RFAL_BR_106 ) ); + rfalSetErrorHandling( RFAL_ERRORHANDLING_NFC ); + + rfalSetGT( RFAL_GT_NFCA ); + rfalSetFDTListen( RFAL_FDT_LISTEN_NFCA_POLLER ); + rfalSetFDTPoll( RFAL_FDT_POLL_NFCA_POLLER ); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcaPollerCheckPresence( rfal14443AShortFrameCmd cmd, rfalNfcaSensRes *sensRes ) +{ + ReturnCode ret; + uint16_t rcvLen; + + /* Digital 1.1 6.10.1.3 For Commands ALL_REQ, SENS_REQ, SDD_REQ, and SEL_REQ, the NFC Forum Device * + * MUST treat receipt of a Listen Frame at a time after FDT(Listen, min) as a Timeour Error */ + + ret = rfalISO14443ATransceiveShortFrame( cmd, (uint8_t*)sensRes, (uint8_t)rfalConvBytesToBits(sizeof(rfalNfcaSensRes)), &rcvLen, RFAL_NFCA_FDTMIN ); + if( (ret == ERR_RF_COLLISION) || (ret == ERR_CRC) || (ret == ERR_NOMEM) || (ret == ERR_FRAMING) || (ret == ERR_PAR) ) + { + ret = ERR_NONE; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcaPollerTechnologyDetection( rfalComplianceMode compMode, rfalNfcaSensRes *sensRes ) +{ + ReturnCode ret; + + EXIT_ON_ERR( ret, rfalNfcaPollerCheckPresence( ((compMode == RFAL_COMPLIANCE_MODE_EMV) ? RFAL_14443A_SHORTFRAME_CMD_WUPA : RFAL_14443A_SHORTFRAME_CMD_REQA), sensRes ) ); + + /* Send SLP_REQ as Activity 1.1 9.2.3.6 and EMVCo 2.6 9.2.1.3 */ + if( compMode != RFAL_COMPLIANCE_MODE_ISO) + { + rfalNfcaPollerSleep(); + } + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcaPollerSingleCollisionResolution( uint8_t devLimit, bool *collPending, rfalNfcaSelRes *selRes, uint8_t *nfcId1, uint8_t *nfcId1Len ) +{ + uint8_t i; + ReturnCode ret; + rfalNfcaSelReq selReq; + uint16_t bytesRx; + uint8_t bytesTxRx; + uint8_t bitsTxRx; + bool doBacktrack = false; + uint8_t backtrackCnt = 3; + + /* Check parameters */ + if( (collPending == NULL) || (selRes == NULL) || (nfcId1 == NULL) || (nfcId1Len == NULL) ) + { + return ERR_PARAM; + } + + /* Initialize output parameters */ + *collPending = false; /* Activity 1.1 9.3.4.6 */ + *nfcId1Len = 0; + ST_MEMSET( nfcId1, 0x00, RFAL_NFCA_CASCADE_3_UID_LEN ); + + /*******************************************************************************/ + /* Go through all Cascade Levels Activity 1.1 9.3.4 */ + for( i = (uint8_t)RFAL_NFCA_SEL_CASCADE_L1; i <= (uint8_t)RFAL_NFCA_SEL_CASCADE_L3; i++) + { + /* Initialize the SDD_REQ to send for the new cascade level */ + ST_MEMSET( (uint8_t*)&selReq, 0x00, sizeof(rfalNfcaSelReq) ); + selReq.selCmd = rfalNfcaCLn2SELCMD(i); + + bytesTxRx = RFAL_NFCA_SDD_REQ_LEN; + bitsTxRx = 0; + + /*******************************************************************************/ + /* Go through Collision loop */ + do + { + uint8_t collBit = 1; /* standards mandate or recommend collision bit to be set to One. */ + /* Calculate SEL_PAR with the bytes/bits to be sent */ + selReq.selPar = rfalNfcaSelPar(bytesTxRx, bitsTxRx); + + /* Send SDD_REQ (Anticollision frame) - Retry upon timeout EMVCo 2.6 9.6.1.3 */ + rfalNfcaTxRetry( ret, rfalISO14443ATransceiveAnticollisionFrame( (uint8_t*)&selReq, &bytesTxRx, &bitsTxRx, &bytesRx, RFAL_NFCA_FDTMIN ), ((devLimit==0U)?RFAL_NFCA_N_RETRANS:0U), RFAL_NFCA_T_RETRANS ); + + bytesRx = rfalConvBitsToBytes(bytesRx); + + if ((ret == ERR_TIMEOUT) + && (backtrackCnt != 0U) && !doBacktrack + && !((RFAL_NFCA_SDD_REQ_LEN==bytesTxRx) && (0U==bitsTxRx))) + { + /* In multiple card scenarios it may always happen that some + * collisions of a weaker tag go unnoticed. If then a later + * collision is recognized and the strong tag has a 0 at the + * collision position then no tag will respond. Catch this + * corner case and then try with the bit being sent as zero. */ + rfalNfcaSensRes sensRes; + ret = ERR_RF_COLLISION; + rfalNfcaPollerCheckPresence( RFAL_14443A_SHORTFRAME_CMD_REQA, &sensRes ); + /* Algorithm below does a post-increment, decrement to go back to current position */ + if (0U == bitsTxRx) + { + bitsTxRx = 7; + bytesTxRx--; + } + else + { + bitsTxRx--; + } + collBit = (uint8_t)( ((uint8_t*)&selReq)[bytesTxRx] & (1U << bitsTxRx) ); + collBit = (uint8_t)((0U==collBit)?1U:0U); // invert the collision bit + doBacktrack = true; + backtrackCnt--; + } + else + { + doBacktrack = false; + } + + if( ret == ERR_RF_COLLISION ) + { + /* Check received length */ + if( (bytesTxRx + ((bitsTxRx != 0U) ? 1U : 0U)) > (RFAL_NFCA_SDD_RES_LEN + RFAL_NFCA_SDD_REQ_LEN) ) + { + return ERR_PROTO; + } + + if( ((bytesTxRx + ((bitsTxRx != 0U) ? 1U : 0U)) > (RFAL_NFCA_CASCADE_1_UID_LEN + RFAL_NFCA_SDD_REQ_LEN)) && (backtrackCnt != 0U) ) + { /* Collision in BCC: Anticollide only UID part */ + backtrackCnt--; + bytesTxRx = RFAL_NFCA_CASCADE_1_UID_LEN + RFAL_NFCA_SDD_REQ_LEN - 1U; + bitsTxRx = 7; + collBit = (uint8_t)( ((uint8_t*)&selReq)[bytesTxRx] & (1U << bitsTxRx) ); /* Not a real collision, extract the actual bit for the subsequent code */ + } + + if( (devLimit == 0U) && !(*collPending) ) + { + /* Activity 1.0 & 1.1 9.3.4.12: If CON_DEVICES_LIMIT has a value of 0, then + * NFC Forum Device is configured to perform collision detection only */ + *collPending = true; + return ERR_IGNORE; + } + + *collPending = true; + + /* Set and select the collision bit, with the number of bytes/bits successfully TxRx */ + if (collBit != 0U) + { + ((uint8_t*)&selReq)[bytesTxRx] = (uint8_t)(((uint8_t*)&selReq)[bytesTxRx] | (1U << bitsTxRx)); /* MISRA 10.3 */ + } + else + { + ((uint8_t*)&selReq)[bytesTxRx] = (uint8_t)(((uint8_t*)&selReq)[bytesTxRx] & ~(1U << bitsTxRx)); /* MISRA 10.3 */ + } + + bitsTxRx++; + + /* Check if number of bits form a byte */ + if( bitsTxRx == RFAL_BITS_IN_BYTE ) + { + bitsTxRx = 0; + bytesTxRx++; + } + } + }while (ret == ERR_RF_COLLISION); + + + /*******************************************************************************/ + /* Check if Collision loop has failed */ + if( ret != ERR_NONE ) + { + return ret; + } + + + /* If collisions are to be reported check whether the response is complete */ + if( (devLimit == 0U) && (bytesRx != sizeof(rfalNfcaSddRes)) ) + { + return ERR_PROTO; + } + + /* Check if the received BCC match */ + if( selReq.bcc != rfalNfcaCalculateBcc( selReq.nfcid1, RFAL_NFCA_CASCADE_1_UID_LEN ) ) + { + return ERR_PROTO; + } + + /*******************************************************************************/ + /* Anticollision OK, Select this Cascade Level */ + selReq.selPar = RFAL_NFCA_SEL_SELPAR; + + /* Send SEL_REQ (Select command) - Retry upon timeout EMVCo 2.6 9.6.1.3 */ + rfalNfcaTxRetry( ret, rfalTransceiveBlockingTxRx( (uint8_t*)&selReq, sizeof(rfalNfcaSelReq), (uint8_t*)selRes, sizeof(rfalNfcaSelRes), &bytesRx, RFAL_TXRX_FLAGS_DEFAULT, RFAL_NFCA_FDTMIN ), ((devLimit==0U)?RFAL_NFCA_N_RETRANS:0U), RFAL_NFCA_T_RETRANS ); + + if( ret != ERR_NONE ) + { + return ret; + } + + + /* Ensure proper response length */ + if( bytesRx != sizeof(rfalNfcaSelRes) ) + { + return ERR_PROTO; + } + + /*******************************************************************************/ + /* Check cascade byte, if cascade tag then go next cascade level */ + if( (ret == ERR_NONE) && (*selReq.nfcid1 == RFAL_NFCA_SDD_CT) ) + { + /* Cascade Tag present, store nfcid1 bytes (excluding cascade tag) and continue for next CL */ + ST_MEMCPY( &nfcId1[*nfcId1Len], &((uint8_t*)&selReq.nfcid1)[RFAL_NFCA_SDD_CT_LEN], (RFAL_NFCA_CASCADE_1_UID_LEN - RFAL_NFCA_SDD_CT_LEN) ); + *nfcId1Len += (RFAL_NFCA_CASCADE_1_UID_LEN - RFAL_NFCA_SDD_CT_LEN); + } + else + { + /* UID Selection complete, Stop Cascade Level loop */ + ST_MEMCPY( &nfcId1[*nfcId1Len], (uint8_t*)&selReq.nfcid1, RFAL_NFCA_CASCADE_1_UID_LEN ); + *nfcId1Len += RFAL_NFCA_CASCADE_1_UID_LEN; + return ERR_NONE; + } + } + return ERR_INTERNAL; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcaPollerFullCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcaListenDevice *nfcaDevList, uint8_t *devCnt ) +{ + ReturnCode ret; + bool collPending; + rfalNfcaSensRes sensRes; + uint16_t rcvLen; + + if( (nfcaDevList == NULL) || (devCnt == NULL) ) + { + return ERR_PARAM; + } + + *devCnt = 0; + ret = ERR_NONE; + + /*******************************************************************************/ + /* Send ALL_REQ before Anticollision if a Sleep was sent before Activity 1.1 9.3.4.1 and EMVco 2.6 9.3.2.1 */ + if( compMode != RFAL_COMPLIANCE_MODE_ISO ) + { + ret = rfalISO14443ATransceiveShortFrame( RFAL_14443A_SHORTFRAME_CMD_WUPA, (uint8_t*)&nfcaDevList->sensRes, (uint8_t)rfalConvBytesToBits(sizeof(rfalNfcaSensRes)), &rcvLen, RFAL_NFCA_FDTMIN ); + if(ret != ERR_NONE) + { + if( (compMode == RFAL_COMPLIANCE_MODE_EMV) || ((ret != ERR_RF_COLLISION) && (ret != ERR_CRC) && (ret != ERR_FRAMING) && (ret != ERR_PAR)) ) + { + return ret; + } + } + + /* Check proper SENS_RES/ATQA size */ + if( (ret == ERR_NONE) && (rfalConvBytesToBits(sizeof(rfalNfcaSensRes)) != rcvLen) ) + { + return ERR_PROTO; + } + } + + + #if RFAL_FEATURE_T1T + /*******************************************************************************/ + /* Only check for T1T if previous SENS_RES was received without a transmission * + * error. When collisions occur bits in the SENS_RES may look like a T1T */ + /* If T1T Anticollision is not supported Activity 1.1 9.3.4.3 */ + if( rfalNfcaIsSensResT1T( &nfcaDevList->sensRes ) && (devLimit != 0U) && (ret == ERR_NONE) && (compMode != RFAL_COMPLIANCE_MODE_EMV) ) + { + /* RID_REQ shall be performed with rfalT1TPollerRid() Activity 1.1 9.3.4.24 */ + rfalT1TPollerInitialize(); + EXIT_ON_ERR( ret, rfalT1TPollerRid( &nfcaDevList->ridRes ) ); + + /* T1T doesn't support Anticollision */ + *devCnt = 1; + nfcaDevList->isSleep = false; + nfcaDevList->type = RFAL_NFCA_T1T; + nfcaDevList->nfcId1Len = RFAL_NFCA_CASCADE_1_UID_LEN; + ST_MEMCPY( &nfcaDevList->nfcId1, &nfcaDevList->ridRes.uid, RFAL_NFCA_CASCADE_1_UID_LEN ); + + return ERR_NONE; + } + #endif /* RFAL_FEATURE_T1T */ + + /*******************************************************************************/ + /* Store the SENS_RES from Technology Detection or from WUPA */ + sensRes = nfcaDevList->sensRes; + + if( devLimit > 0U ) /* MISRA 21.18 */ + { + ST_MEMSET( nfcaDevList, 0x00, (sizeof(rfalNfcaListenDevice) * devLimit) ); + } + + /* Restore the prev SENS_RES, assuming that the SENS_RES received is from first device + * When only one device is detected it's not woken up then we'll have no SENS_RES (ATQA) */ + nfcaDevList->sensRes = sensRes; + + + /*******************************************************************************/ + do + { + uint8_t newDeviceType; + + EXIT_ON_ERR( ret, rfalNfcaPollerSingleCollisionResolution( devLimit, &collPending, &nfcaDevList[*devCnt].selRes, (uint8_t*)&nfcaDevList[*devCnt].nfcId1, (uint8_t*)&nfcaDevList[*devCnt].nfcId1Len ) ); + + /* Assign Listen Device */ + newDeviceType = ((uint8_t)nfcaDevList[*devCnt].selRes.sak) & RFAL_NFCA_SEL_RES_CONF_MASK; /* MISRA 10.8 */ + /* PRQA S 4342 1 # MISRA 10.5 - Guaranteed that no invalid enum values are created: see guard_eq_RFAL_NFCA_T2T, .... */ + nfcaDevList[*devCnt].type = (rfalNfcaListenDeviceType) (newDeviceType); + nfcaDevList[*devCnt].isSleep = false; + (*devCnt)++; + + + /* If a collision was detected and device counter is lower than limit Activity 1.1 9.3.4.21 */ + if( (*devCnt < devLimit) && ((collPending) || (compMode != RFAL_COMPLIANCE_MODE_ISO) ) ) + { + /* Put this device to Sleep Activity 1.1 9.3.4.22 */ + rfalNfcaPollerSleep(); + nfcaDevList[(*devCnt - 1U)].isSleep = true; + + + /* Send a new SENS_REQ to check for other cards Activity 1.1 9.3.4.23 */ + ret = rfalNfcaPollerCheckPresence( RFAL_14443A_SHORTFRAME_CMD_REQA, &nfcaDevList[*devCnt].sensRes ); + if( ret == ERR_TIMEOUT ) + { + /* No more devices found, exit */ + collPending = false; + } + else + { + /* Another device found, continue loop */ + collPending = true; + } + } + else + { + /* Exit loop */ + collPending = false; + } + }while( (*devCnt < devLimit) && (collPending) ); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcaPollerSelect( const uint8_t *nfcid1, uint8_t nfcidLen, rfalNfcaSelRes *selRes ) +{ + uint8_t i; + uint8_t cl; + uint8_t nfcidOffset; + uint16_t rxLen; + ReturnCode ret; + rfalNfcaSelReq selReq; + + if( (nfcid1 == NULL) || (nfcidLen > RFAL_NFCA_CASCADE_3_UID_LEN) || (selRes == NULL) ) + { + return ERR_PARAM; + } + + + /* Calculate Cascate Level */ + cl = rfalNfcaNfcidLen2CL( nfcidLen ); + nfcidOffset = 0; + + /*******************************************************************************/ + /* Go through all Cascade Levels Activity 1.1 9.4.4 */ + for( i = RFAL_NFCA_SEL_CASCADE_L1; i <= cl; i++ ) + { + /* Assign SEL_CMD according to the CLn and SEL_PAR*/ + selReq.selCmd = rfalNfcaCLn2SELCMD(i); + selReq.selPar = RFAL_NFCA_SEL_SELPAR; + + /* Compute NFCID/Data on the SEL_REQ command Digital 1.1 Table 18 */ + if( cl != i ) + { + *selReq.nfcid1 = RFAL_NFCA_SDD_CT; + ST_MEMCPY( &selReq.nfcid1[RFAL_NFCA_SDD_CT_LEN], &nfcid1[nfcidOffset], (RFAL_NFCA_CASCADE_1_UID_LEN - RFAL_NFCA_SDD_CT_LEN) ); + nfcidOffset += (RFAL_NFCA_CASCADE_1_UID_LEN - RFAL_NFCA_SDD_CT_LEN); + } + else + { + ST_MEMCPY( selReq.nfcid1, &nfcid1[nfcidOffset], RFAL_NFCA_CASCADE_1_UID_LEN ); + } + + /* Calculate nfcid's BCC */ + selReq.bcc = rfalNfcaCalculateBcc( (uint8_t*)&selReq.nfcid1, sizeof(selReq.nfcid1) ); + + /*******************************************************************************/ + /* Send SEL_REQ */ + EXIT_ON_ERR( ret, rfalTransceiveBlockingTxRx( (uint8_t*)&selReq, sizeof(rfalNfcaSelReq), (uint8_t*)selRes, sizeof(rfalNfcaSelRes), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_NFCA_FDTMIN ) ); + + /* Ensure proper response length */ + if( rxLen != sizeof(rfalNfcaSelRes) ) + { + return ERR_PROTO; + } + } + + /* REMARK: Could check if NFCID1 is complete */ + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcaPollerSleep( void ) +{ + rfalNfcaSlpReq slpReq; + uint8_t rxBuf; /* dummy buffer, just to perform Rx */ + + slpReq.frame[RFAL_NFCA_SLP_CMD_POS] = RFAL_NFCA_SLP_CMD; + slpReq.frame[RFAL_NFCA_SLP_BYTE2_POS] = RFAL_NFCA_SLP_BYTE2; + + rfalTransceiveBlockingTxRx( (uint8_t*)&slpReq, sizeof(rfalNfcaSlpReq), &rxBuf, sizeof(rxBuf), NULL, RFAL_TXRX_FLAGS_DEFAULT, RFAL_NFCA_SLP_FWT ); + + /* ISO14443-3 6.4.3 HLTA - If PICC responds with any modulation during 1 ms this response shall be interpreted as not acknowledge + Digital 2.0 6.9.2.1 & EMVCo 3.0 5.6.2.1 - consider the HLTA command always acknowledged + No check to be compliant with NFC and EMVCo, and to improve interoprability (Kovio RFID Tag) + */ + + return ERR_NONE; +} + + +/*******************************************************************************/ +bool rfalNfcaListenerIsSleepReq( const uint8_t *buf, uint16_t bufLen ) +{ + /* Check if length and payload match */ + if( (bufLen != sizeof(rfalNfcaSlpReq)) || (buf[RFAL_NFCA_SLP_CMD_POS] != RFAL_NFCA_SLP_CMD) || (buf[RFAL_NFCA_SLP_BYTE2_POS] != RFAL_NFCA_SLP_BYTE2) ) + { + return false; + } + + return true; +} + +/* If the guards here don't compile then the code above cannot work anymore. */ +extern uint8_t guard_eq_RFAL_NFCA_T2T[((RFAL_NFCA_SEL_RES_CONF_MASK&(uint8_t)RFAL_NFCA_T2T) == (uint8_t)RFAL_NFCA_T2T)?1:(-1)]; +extern uint8_t guard_eq_RFAL_NFCA_T4T[((RFAL_NFCA_SEL_RES_CONF_MASK&(uint8_t)RFAL_NFCA_T4T) == (uint8_t)RFAL_NFCA_T4T)?1:(-1)]; +extern uint8_t guard_eq_RFAL_NFCA_NFCDEP[((RFAL_NFCA_SEL_RES_CONF_MASK&(uint8_t)RFAL_NFCA_NFCDEP) == (uint8_t)RFAL_NFCA_NFCDEP)?1:(-1)]; +extern uint8_t guard_eq_RFAL_NFCA_T4T_NFCDEP[((RFAL_NFCA_SEL_RES_CONF_MASK&(uint8_t)RFAL_NFCA_T4T_NFCDEP) == (uint8_t)RFAL_NFCA_T4T_NFCDEP)?1:(-1)]; +#endif /* RFAL_FEATURE_NFCA */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_nfcb.c b/Software/fab-reader2-c/components/rfal/Src/rfal_nfcb.c new file mode 100644 index 0000000..49abebc --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_nfcb.c @@ -0,0 +1,504 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfcb.c + * + * \author Gustavo Patricio + * + * \brief Implementation of NFC-B (ISO14443B) helpers + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_nfcb.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_NFCB + #define RFAL_FEATURE_NFCB false /* NFC-B module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_NFCB + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_NFCB_SENSB_REQ_EXT_SENSB_RES_SUPPORTED 0x10U /*!< Bit mask for Extended SensB Response support in SENSB_REQ */ +#define RFAL_NFCB_SENSB_RES_PROT_TYPE_RFU 0x08U /*!< Bit mask for Protocol Type RFU in SENSB_RES */ +#define RFAL_NFCB_SLOT_MARKER_SC_SHIFT 4U /*!< Slot Code position on SLOT_MARKER APn */ + +#define RFAL_NFCB_SLOTMARKER_SLOTCODE_MIN 1U /*!< SLOT_MARKER Slot Code minimum Digital 1.1 Table 37 */ +#define RFAL_NFCB_SLOTMARKER_SLOTCODE_MAX 16U /*!< SLOT_MARKER Slot Code maximum Digital 1.1 Table 37 */ + +#define RFAL_NFCB_ACTIVATION_FWT (RFAL_NFCB_FWTSENSB + RFAL_NFCB_DTPOLL_20) /*!< FWT(SENSB) + dTbPoll Digital 2.0 7.9.1.3 */ + +/*! Advanced and Extended bit mask in Parameter of SENSB_REQ */ +#define RFAL_NFCB_SENSB_REQ_PARAM (RFAL_NFCB_SENSB_REQ_ADV_FEATURE | RFAL_NFCB_SENSB_REQ_EXT_SENSB_RES_SUPPORTED) + + +/*! NFC-B commands definition */ +enum +{ + RFAL_NFCB_CMD_SENSB_REQ = 0x05, /*!< SENSB_REQ (REQB) & SLOT_MARKER Digital 1.1 Table 24 */ + RFAL_NFCB_CMD_SENSB_RES = 0x50, /*!< SENSB_RES (ATQB) & SLOT_MARKER Digital 1.1 Table 27 */ + RFAL_NFCB_CMD_SLPB_REQ = 0x50, /*!< SLPB_REQ (HLTB command) Digital 1.1 Table 38 */ + RFAL_NFCB_CMD_SLPB_RES = 0x00 /*!< SLPB_RES (HLTB Answer) Digital 1.1 Table 39 */ +}; + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + +#define rfalNfcbNI2NumberOfSlots( ni ) (uint8_t)(1U << (ni)) /*!< Converts the Number of slots Identifier to slot number */ + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! ALLB_REQ (WUPB) and SENSB_REQ (REQB) Command Format Digital 1.1 7.6.1 */ +typedef struct +{ + uint8_t cmd; /*!< xxxxB_REQ: 05h */ + uint8_t AFI; /*!< NFC Identifier */ + uint8_t PARAM; /*!< Application Data */ +} rfalNfcbSensbReq; + +/*! SLOT_MARKER Command format Digital 1.1 7.7.1 */ +typedef struct +{ + uint8_t APn; /*!< Slot number 2..16 | 0101b */ +} rfalNfcbSlotMarker; + +/*! SLPB_REQ (HLTB) Command Format Digital 1.1 7.8.1 */ +typedef struct +{ + uint8_t cmd; /*!< SLPB_REQ: 50h */ + uint8_t nfcid0[RFAL_NFCB_NFCID0_LEN]; /*!< NFC Identifier (PUPI)*/ +} rfalNfcbSlpbReq; + + +/*! SLPB_RES (HLTB) Response Format Digital 1.1 7.8.2 */ +typedef struct +{ + uint8_t cmd; /*!< SLPB_RES: 00h */ +} rfalNfcbSlpbRes; + + +/*! RFAL NFC-B instance */ +typedef struct +{ + uint8_t AFI; /*!< AFI to be used */ + uint8_t PARAM; /*!< PARAM to be used */ +} rfalNfcb; + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +static ReturnCode rfalNfcbCheckSensbRes( const rfalNfcbSensbRes *sensbRes, uint8_t sensbResLen ); + + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ + +static rfalNfcb gRfalNfcb; /*!< RFAL NFC-B Instance */ + + +/* +****************************************************************************** +* LOCAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +static ReturnCode rfalNfcbCheckSensbRes( const rfalNfcbSensbRes *sensbRes, uint8_t sensbResLen ) +{ + /* Check response length */ + if( ( (sensbResLen != RFAL_NFCB_SENSB_RES_LEN) && (sensbResLen != RFAL_NFCB_SENSB_RES_EXT_LEN) ) ) + { + return ERR_PROTO; + } + + /* Check SENSB_RES and Protocol Type Digital 1.1 7.6.2.19 */ + if( ((sensbRes->protInfo.FsciProType & RFAL_NFCB_SENSB_RES_PROT_TYPE_RFU) != 0U) || (sensbRes->cmd != (uint8_t)RFAL_NFCB_CMD_SENSB_RES) ) + { + return ERR_PROTO; + } + return ERR_NONE; +} + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +ReturnCode rfalNfcbPollerInitialize( void ) +{ + ReturnCode ret; + + EXIT_ON_ERR( ret, rfalSetMode( RFAL_MODE_POLL_NFCB, RFAL_BR_106, RFAL_BR_106 ) ); + rfalSetErrorHandling( RFAL_ERRORHANDLING_NFC ); + + rfalSetGT( RFAL_GT_NFCB ); + rfalSetFDTListen( RFAL_FDT_LISTEN_NFCB_POLLER ); + rfalSetFDTPoll( RFAL_FDT_POLL_NFCB_POLLER ); + + gRfalNfcb.AFI = RFAL_NFCB_AFI; + gRfalNfcb.PARAM = RFAL_NFCB_PARAM; + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcbPollerInitializeWithParams( uint8_t AFI, uint8_t PARAM ) +{ + ReturnCode ret; + + EXIT_ON_ERR( ret, rfalNfcbPollerInitialize() ); + + gRfalNfcb.AFI = AFI; + gRfalNfcb.PARAM = (PARAM & RFAL_NFCB_SENSB_REQ_PARAM); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcbPollerCheckPresence( rfalNfcbSensCmd cmd, rfalNfcbSlots slots, rfalNfcbSensbRes *sensbRes, uint8_t *sensbResLen ) +{ + uint16_t rxLen; + ReturnCode ret; + rfalNfcbSensbReq sensbReq; + + + /* Check if the command requested and given the slot number are valid */ + if( ((RFAL_NFCB_SENS_CMD_SENSB_REQ != cmd) && (RFAL_NFCB_SENS_CMD_ALLB_REQ != cmd)) || + (slots > RFAL_NFCB_SLOT_NUM_16) || (sensbRes == NULL) || (sensbResLen == NULL) ) + { + return ERR_PARAM; + } + + *sensbResLen = 0; + ST_MEMSET(sensbRes, 0x00, sizeof(rfalNfcbSensbRes) ); + + /* Compute SENSB_REQ */ + sensbReq.cmd = RFAL_NFCB_CMD_SENSB_REQ; + sensbReq.AFI = gRfalNfcb.AFI; + sensbReq.PARAM = (((uint8_t)gRfalNfcb.PARAM & RFAL_NFCB_SENSB_REQ_PARAM) | (uint8_t)cmd | (uint8_t)slots); + + /* Send SENSB_REQ and disable AGC to detect collisions */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&sensbReq, sizeof(rfalNfcbSensbReq), (uint8_t*)sensbRes, sizeof(rfalNfcbSensbRes), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_NFCB_FWTSENSB ); + + *sensbResLen = (uint8_t)rxLen; + + /* Check if a transmission error was detected */ + if( (ret == ERR_CRC) || (ret == ERR_FRAMING) ) + { + /* Invalidate received frame as an error was detected (CollisionResolution checks if valid) */ + *sensbResLen = 0; + return ERR_NONE; + } + + if( ret == ERR_NONE ) + { + return rfalNfcbCheckSensbRes( sensbRes, *sensbResLen ); + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcbPollerSleep( const uint8_t* nfcid0 ) +{ + uint16_t rxLen; + ReturnCode ret; + rfalNfcbSlpbReq slpbReq; + rfalNfcbSlpbRes slpbRes; + + if( nfcid0 == NULL ) + { + return ERR_PARAM; + } + + /* Compute SLPB_REQ */ + slpbReq.cmd = RFAL_NFCB_CMD_SLPB_REQ; + ST_MEMCPY( slpbReq.nfcid0, nfcid0, RFAL_NFCB_NFCID0_LEN ); + + EXIT_ON_ERR( ret, rfalTransceiveBlockingTxRx( (uint8_t*)&slpbReq, sizeof(rfalNfcbSlpbReq), (uint8_t*)&slpbRes, sizeof(rfalNfcbSlpbRes), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_NFCB_ACTIVATION_FWT )); + + /* Check SLPB_RES */ + if( (rxLen != sizeof(rfalNfcbSlpbRes)) || (slpbRes.cmd != (uint8_t)RFAL_NFCB_CMD_SLPB_RES) ) + { + return ERR_PROTO; + } + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcbPollerSlotMarker( uint8_t slotCode, rfalNfcbSensbRes *sensbRes, uint8_t *sensbResLen ) +{ + ReturnCode ret; + rfalNfcbSlotMarker slotMarker; + uint16_t rxLen; + + /* Check parameters */ + if( (sensbRes == NULL) || (sensbResLen == NULL) || + (slotCode < RFAL_NFCB_SLOTMARKER_SLOTCODE_MIN) || + (slotCode > RFAL_NFCB_SLOTMARKER_SLOTCODE_MAX) ) + { + return ERR_PARAM; + } + /* Compose and send SLOT_MARKER with disabled AGC to detect collisions */ + slotMarker.APn = ((slotCode << RFAL_NFCB_SLOT_MARKER_SC_SHIFT) | (uint8_t)RFAL_NFCB_CMD_SENSB_REQ); + + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&slotMarker, sizeof(rfalNfcbSlotMarker), (uint8_t*)sensbRes, sizeof(rfalNfcbSensbRes), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_NFCB_ACTIVATION_FWT ); + + *sensbResLen = (uint8_t)rxLen; + + /* Check if a transmission error was detected */ + if( (ret == ERR_CRC) || (ret == ERR_FRAMING) ) + { + return ERR_RF_COLLISION; + } + + if( ret == ERR_NONE ) + { + return rfalNfcbCheckSensbRes( sensbRes, *sensbResLen ); + } + + return ret; +} + + +ReturnCode rfalNfcbPollerTechnologyDetection( rfalComplianceMode compMode, rfalNfcbSensbRes *sensbRes, uint8_t *sensbResLen ) +{ + NO_WARNING(compMode); + + return rfalNfcbPollerCheckPresence( RFAL_NFCB_SENS_CMD_SENSB_REQ, RFAL_NFCB_SLOT_NUM_1, sensbRes, sensbResLen ); +} + + +/*******************************************************************************/ +ReturnCode rfalNfcbPollerCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcbListenDevice *nfcbDevList, uint8_t *devCnt ) +{ + bool colPending; /* dummy */ + return rfalNfcbPollerSlottedCollisionResolution( compMode, devLimit, RFAL_NFCB_SLOT_NUM_1, RFAL_NFCB_SLOT_NUM_16, nfcbDevList, devCnt, &colPending ); +} + + +/*******************************************************************************/ +ReturnCode rfalNfcbPollerSlottedCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcbSlots initSlots, rfalNfcbSlots endSlots, rfalNfcbListenDevice *nfcbDevList, uint8_t *devCnt, bool *colPending ) +{ + ReturnCode ret; + uint8_t slotsNum; + uint8_t slotCode; + uint8_t curDevCnt; + + + /* Check parameters. In ISO | Activity 1.0 mode the initial slots must be 1 as continuation of Technology Detection */ + if( (nfcbDevList == NULL) || (devCnt == NULL) || (colPending == NULL) || (initSlots > RFAL_NFCB_SLOT_NUM_16) || + (endSlots > RFAL_NFCB_SLOT_NUM_16) || ((compMode == RFAL_COMPLIANCE_MODE_ISO) && (initSlots != RFAL_NFCB_SLOT_NUM_1)) ) + { + return ERR_PARAM; + } + + /* Initialise as no error in case Activity 1.0 where the previous SENSB_RES from technology detection should be used */ + ret = ERR_NONE; + *devCnt = 0; + curDevCnt = 0; + *colPending = false; + + + /* Send ALLB_REQ Activity 1.1 9.3.5.2 and 9.3.5.3 (Symbol 1 and 2) */ + if( compMode != RFAL_COMPLIANCE_MODE_ISO ) + { + ret = rfalNfcbPollerCheckPresence( RFAL_NFCB_SENS_CMD_ALLB_REQ, initSlots, &nfcbDevList->sensbRes, &nfcbDevList->sensbResLen ); + if( (ret != ERR_NONE) && (initSlots == RFAL_NFCB_SLOT_NUM_1) ) + { + return ret; + } + } + + + /* Check if there was a transmission error on WUPB EMVCo 2.6 9.3.3.1 */ + if( (compMode == RFAL_COMPLIANCE_MODE_EMV) && (nfcbDevList->sensbResLen == 0U) ) + { + return ERR_FRAMING; + } + + for( slotsNum = (uint8_t)initSlots; slotsNum <= (uint8_t)endSlots; slotsNum++ ) + { + do { + /* Activity 1.1 9.3.5.23 - Symbol 22 */ + if( (compMode == RFAL_COMPLIANCE_MODE_NFC) && (curDevCnt != 0U) ) + { + rfalNfcbPollerSleep( nfcbDevList[(*devCnt-1U)].sensbRes.nfcid0 ); + nfcbDevList[(*devCnt-1U)].isSleep = true; + } + + /* Send SENSB_REQ with number of slots if not the first Activity 1.1 9.3.5.24 - Symbol 23 */ + if( (slotsNum != (uint8_t)initSlots) || *colPending ) + { + /* PRQA S 4342 1 # MISRA 10.5 - Layout of rfalNfcbSlots and above loop guarantee that no invalid enum values are created. */ + ret = rfalNfcbPollerCheckPresence( RFAL_NFCB_SENS_CMD_SENSB_REQ, (rfalNfcbSlots)slotsNum, &nfcbDevList[*devCnt].sensbRes, &nfcbDevList[*devCnt].sensbResLen ); + } + + /* Activity 1.1 9.3.5.6 - Symbol 5 */ + slotCode = 0; + curDevCnt = 0; + *colPending = false; + + do{ + /* Activity 1.1 9.3.5.26 - Symbol 25 */ + if( slotCode != 0U ) + { + ret = rfalNfcbPollerSlotMarker( slotCode, &nfcbDevList[*devCnt].sensbRes, &nfcbDevList[*devCnt].sensbResLen ); + } + + /* Activity 1.1 9.3.5.7 and 9.3.5.8 - Symbol 6 */ + if( ret != ERR_TIMEOUT ) + { + /* Activity 1.1 9.3.5.8 - Symbol 7 */ + if( (rfalNfcbCheckSensbRes( &nfcbDevList[*devCnt].sensbRes, nfcbDevList[*devCnt].sensbResLen) == ERR_NONE) && (ret == ERR_NONE) ) + { + nfcbDevList[*devCnt].isSleep = false; + + if( compMode == RFAL_COMPLIANCE_MODE_EMV ) + { + (*devCnt)++; + return ret; + } + else if( compMode == RFAL_COMPLIANCE_MODE_ISO ) + { + /* Activity 1.0 9.3.5.8 - Symbol 7 */ + (*devCnt)++; + curDevCnt++; + + /* Activity 1.0 9.3.5.10 - Symbol 9 */ + if( (*devCnt >= devLimit) || (slotsNum == (uint8_t)RFAL_NFCB_SLOT_NUM_1) ) + { + return ret; + } + + /* Activity 1.0 9.3.5.11 - Symbol 10 */ + rfalNfcbPollerSleep( nfcbDevList[*devCnt-1U].sensbRes.nfcid0 ); + nfcbDevList[*devCnt-1U].isSleep = true; + } + else if( compMode == RFAL_COMPLIANCE_MODE_NFC ) + { + /* Activity 1.1 9.3.5.10 and 9.3.5.11 - Symbol 9 and Symbol 11*/ + if(curDevCnt != 0U) + { + rfalNfcbPollerSleep( nfcbDevList[*devCnt-1U].sensbRes.nfcid0 ); + nfcbDevList[*devCnt-1U].isSleep = true; + } + + /* Activity 1.1 9.3.5.12 - Symbol 11 */ + (*devCnt)++; + curDevCnt++; + + /* Activity 1.1 9.3.5.6 - Symbol 13 */ + if( (*devCnt >= devLimit) || (slotsNum == (uint8_t)RFAL_NFCB_SLOT_NUM_1) ) + { + return ret; + } + } + else + { + /* MISRA 15.7 - Empty else */ + } + } + else + { + /* If deviceLimit is set to 0 the NFC Forum Device is configured to perform collision detection only Activity 1.0 and 1.1 9.3.5.5 - Symbol 4 */ + if( (devLimit == 0U) && (slotsNum == (uint8_t)RFAL_NFCB_SLOT_NUM_1) ) + { + return ERR_RF_COLLISION; + } + + /* Activity 1.1 9.3.5.9 - Symbol 8 */ + *colPending = true; + } + } + + /* Activity 1.1 9.3.5.15 - Symbol 14 */ + slotCode++; + } + while( slotCode < rfalNfcbNI2NumberOfSlots(slotsNum) ); + + /* Activity 1.1 9.3.5.17 - Symbol 16 */ + if( !(*colPending) ) + { + return ERR_NONE; + } + + /* Activity 1.1 9.3.5.18 - Symbol 17 */ + } while (curDevCnt != 0U); /* If a collision is detected and card(s) were found on this loop keep the same number of available slots */ + } + + return ERR_NONE; +} + + +/*******************************************************************************/ +uint32_t rfalNfcbTR2ToFDT( uint8_t tr2Code ) +{ + /*******************************************************************************/ + /* MISRA 8.9 An object should be defined at block scope if its identifier only appears in a single function */ + /*! TR2 Table according to Digital 1.1 Table 33 */ + const uint16_t rfalNfcbTr2Table[] = { 1792, 3328, 5376, 9472 }; + /*******************************************************************************/ + + return rfalNfcbTr2Table[ (tr2Code & RFAL_NFCB_SENSB_RES_PROTO_TR2_MASK) ]; +} + +#endif /* RFAL_FEATURE_NFCB */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_nfcf.c b/Software/fab-reader2-c/components/rfal/Src/rfal_nfcf.c new file mode 100644 index 0000000..e3dd112 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_nfcf.c @@ -0,0 +1,546 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfcf.c + * + * \author Gustavo Patricio + * + * \brief Implementation of NFC-F Poller (FeliCa PCD) device + * + * The definitions and helpers methods provided by this module are + * aligned with NFC-F (FeliCa - JIS X6319-4) + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_nfcf.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_NFCF + #define RFAL_FEATURE_NFCF false /* NFC-F module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_NFCF + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ +#define RFAL_NFCF_SENSF_REQ_LEN_MIN 5U /*!< SENSF_RES minimum length */ + +#define RFAL_NFCF_READ_WO_ENCRYPTION_MIN_LEN 15U /*!< Minimum length for a Check Command T3T 5.4.1 */ +#define RFAL_NFCF_WRITE_WO_ENCRYPTION_MIN_LEN 31U /*!< Minimum length for an Update Command T3T 5.5.1 */ + +#define RFAL_NFCF_CHECK_RES_MIN_LEN 11U /*!< CHECK Response minimum length T3T 1.0 Table 8 */ +#define RFAL_NFCF_UPDATE_RES_MIN_LEN 11U /*!< UPDATE Response minimum length T3T 1.0 Table 8 */ + +#define RFAL_NFCF_CHECK_REQ_MAX_LEN 86U /*!< Max length of a Check request T3T 1.0 Table 7 */ +#define RFAL_NFCF_CHECK_REQ_MAX_SERV 15U /*!< Max Services number on Check request T3T 1.0 5.4.1.5 */ +#define RFAL_NFCF_CHECK_REQ_MAX_BLOCK 15U /*!< Max Blocks number on Check request T3T 1.0 5.4.1.10 */ +#define RFAL_NFCF_UPDATE_REQ_MAX_SERV 15U /*!< Max Services number Update request T3T 1.0 5.4.1.5 */ +#define RFAL_NFCF_UPDATE_REQ_MAX_BLOCK 13U /*!< Max Blocks number on Update request T3T 1.0 5.4.1.10 */ + + +/*! MRT Check | Uupdate = (Tt3t x ((A+1) + n (B+1)) x 4^E) + dRWTt3t T3T 5.8 + Max values used: A = 7 ; B = 7 ; E = 3 ; n = 15 (NFC Forum n = 15, JIS n = 32) +*/ +#define RFAL_NFCF_MRT_CHECK_UPDATE ((4096 * (8 + (15 * 8)) * 64 ) + 16) + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ +#define rfalNfcfSlots2CardNum( s ) ((uint8_t)(s)+1U) /*!< Converts Time Slot Number (TSN) into num of slots */ + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! Structure/Buffer to hold the SENSF_RES with LEN byte prepended */ +typedef struct{ + uint8_t LEN; /*!< NFC-F LEN byte */ + rfalNfcfSensfRes SENSF_RES; /*!< SENSF_RES */ +} rfalNfcfSensfResBuf; + + +/*! Greedy collection for NFCF GRE_POLL_F Activity 1.0 Table 10 */ +typedef struct{ + uint8_t pollFound; /*!< Number of devices found by the Poll */ + uint8_t pollCollision; /*!< Number of collisions detected */ + rfalFeliCaPollRes POLL_F[RFAL_NFCF_POLL_MAXCARDS]; /*!< GRE_POLL_F Activity 1.0 Table 10 */ +} rfalNfcfGreedyF; + + +/*! NFC-F SENSF_REQ format Digital 1.1 8.6.1 */ +typedef struct +{ + uint8_t CMD; /*!< Command code: 00h */ + uint8_t SC[RFAL_NFCF_SENSF_SC_LEN]; /*!< System Code */ + uint8_t RC; /*!< Request Code */ + uint8_t TSN; /*!< Time Slot Number */ +} rfalNfcfSensfReq; + + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ +static rfalNfcfGreedyF gRfalNfcfGreedyF; /*!< Activity's NFCF Greedy collection */ + + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +static void rfalNfcfComputeValidSENF( rfalNfcfListenDevice *outDevInfo, uint8_t *curDevIdx, uint8_t devLimit, bool overwrite, bool *nfcDepFound ); + + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ + +/*******************************************************************************/ +static void rfalNfcfComputeValidSENF( rfalNfcfListenDevice *outDevInfo, uint8_t *curDevIdx, uint8_t devLimit, bool overwrite, bool *nfcDepFound ) +{ + uint8_t tmpIdx; + bool duplicate; + rfalNfcfSensfResBuf *sensfBuf; + rfalNfcfSensfResBuf sensfCopy; + + + /*******************************************************************************/ + /* Go through all responses check if valid and duplicates */ + /*******************************************************************************/ + while( (gRfalNfcfGreedyF.pollFound > 0U) && ((*curDevIdx) < devLimit) ) + { + duplicate = false; + gRfalNfcfGreedyF.pollFound--; + + /* MISRA 11.3 - Cannot point directly into different object type, use local copy */ + ST_MEMCPY( (uint8_t*)&sensfCopy, (uint8_t*)&gRfalNfcfGreedyF.POLL_F[gRfalNfcfGreedyF.pollFound], sizeof(rfalNfcfSensfResBuf) ); + + + /* Point to received SENSF_RES */ + sensfBuf = &sensfCopy; + + + /* Check for devices that are already in device list */ + for( tmpIdx = 0; tmpIdx < (*curDevIdx); tmpIdx++ ) + { + if( ST_BYTECMP( sensfBuf->SENSF_RES.NFCID2, outDevInfo[tmpIdx].sensfRes.NFCID2, RFAL_NFCF_NFCID2_LEN ) == 0 ) + { + duplicate = true; + break; + } + } + + /* If is a duplicate skip this (and not to overwrite)*/ + if(duplicate && !overwrite) + { + continue; + } + + /* Check if response length is OK */ + if( (( sensfBuf->LEN - RFAL_NFCF_HEADER_LEN) < RFAL_NFCF_SENSF_RES_LEN_MIN) || ((sensfBuf->LEN - RFAL_NFCF_HEADER_LEN) > RFAL_NFCF_SENSF_RES_LEN_MAX) ) + { + continue; + } + + /* Check if the response is a SENSF_RES / Polling response */ + if( sensfBuf->SENSF_RES.CMD != (uint8_t)RFAL_NFCF_CMD_POLLING_RES ) + { + continue; + } + + /* Check if is an overwrite request or new device*/ + if(duplicate && overwrite) + { + /* overwrite deviceInfo/GRE_SENSF_RES with SENSF_RES */ + outDevInfo[tmpIdx].sensfResLen = (sensfBuf->LEN - RFAL_NFCF_LENGTH_LEN); + ST_MEMCPY( &outDevInfo[tmpIdx].sensfRes, &sensfBuf->SENSF_RES, outDevInfo[tmpIdx].sensfResLen ); + continue; + } + else + { + /* fill deviceInfo/GRE_SENSF_RES with new SENSF_RES */ + outDevInfo[(*curDevIdx)].sensfResLen = (sensfBuf->LEN - RFAL_NFCF_LENGTH_LEN); + ST_MEMCPY( &outDevInfo[(*curDevIdx)].sensfRes, &sensfBuf->SENSF_RES, outDevInfo[(*curDevIdx)].sensfResLen ); + } + + /* Check if this device supports NFC-DEP and signal it (ACTIVITY 1.1 9.3.6.63) */ + *nfcDepFound = rfalNfcfIsNfcDepSupported( &outDevInfo[(*curDevIdx)] ); + + (*curDevIdx)++; + } +} + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +ReturnCode rfalNfcfPollerInitialize( rfalBitRate bitRate ) +{ + ReturnCode ret; + + if( (bitRate != RFAL_BR_212) && (bitRate != RFAL_BR_424) ) + { + return ERR_PARAM; + } + + EXIT_ON_ERR( ret, rfalSetMode( RFAL_MODE_POLL_NFCF, bitRate, bitRate ) ); + rfalSetErrorHandling( RFAL_ERRORHANDLING_NFC ); + + rfalSetGT( RFAL_GT_NFCF ); + rfalSetFDTListen( RFAL_FDT_LISTEN_NFCF_POLLER ); + rfalSetFDTPoll( RFAL_FDT_POLL_NFCF_POLLER ); + + return ERR_NONE; +} + + + +/*******************************************************************************/ +ReturnCode rfalNfcfPollerPoll( rfalFeliCaPollSlots slots, uint16_t sysCode, uint8_t reqCode, rfalFeliCaPollRes *cardList, uint8_t *devCnt, uint8_t *collisions ) +{ + return rfalFeliCaPoll( slots, sysCode, reqCode, cardList, rfalNfcfSlots2CardNum(slots), devCnt, collisions ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcfPollerCheckPresence( void ) +{ + gRfalNfcfGreedyF.pollFound = 0; + gRfalNfcfGreedyF.pollCollision = 0; + + /* ACTIVITY 1.0 & 1.1 - 9.2.3.17 SENSF_REQ must be with number of slots equal to 4 + * SC must be 0xFFFF + * RC must be 0x00 (No system code info required) */ + return rfalFeliCaPoll( RFAL_FELICA_4_SLOTS, RFAL_NFCF_SYSTEMCODE, RFAL_FELICA_POLL_RC_NO_REQUEST, gRfalNfcfGreedyF.POLL_F, rfalNfcfSlots2CardNum(RFAL_FELICA_4_SLOTS), &gRfalNfcfGreedyF.pollFound, &gRfalNfcfGreedyF.pollCollision ); +} + + +/*******************************************************************************/ +ReturnCode rfalNfcfPollerCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcfListenDevice *nfcfDevList, uint8_t *devCnt ) +{ + ReturnCode ret; + bool nfcDepFound; + + if( (nfcfDevList == NULL) || (devCnt == NULL) ) + { + return ERR_PARAM; + } + + *devCnt = 0; + nfcDepFound = false; + + + /*******************************************************************************************/ + /* ACTIVITY 1.0 - 9.3.6.3 Copy valid SENSF_RES in GRE_POLL_F into GRE_SENSF_RES */ + /* ACTIVITY 1.0 - 9.3.6.6 The NFC Forum Device MUST remove all entries from GRE_SENSF_RES[]*/ + /* ACTIVITY 1.1 - 9.3.63.59 Populate GRE_SENSF_RES with data from GRE_POLL_F */ + /* */ + /* CON_DEVICES_LIMIT = 0 Just check if devices from Tech Detection exceeds -> always true */ + /* Allow the number of slots open on Technology Detection */ + /*******************************************************************************************/ + rfalNfcfComputeValidSENF( nfcfDevList, devCnt, ((devLimit == 0U) ? rfalNfcfSlots2CardNum( RFAL_FELICA_4_SLOTS ) : devLimit), false, &nfcDepFound ); + + + /*******************************************************************************/ + /* ACTIVITY 1.0 - 9.3.6.4 */ + /* ACTIVITY 1.1 - 9.3.63.60 Check if devices found are lower than the limit */ + /* and send a SENSF_REQ if so */ + /*******************************************************************************/ + if( *devCnt < devLimit ) + { + /* ACTIVITY 1.0 - 9.3.6.5 Copy valid SENSF_RES and then to remove it + * ACTIVITY 1.1 - 9.3.6.65 Copy and filter duplicates + * For now, due to some devices keep generating different nfcid2, we use 1.0 + * Phones detected: Samsung Galaxy Nexus,Samsung Galaxy S3,Samsung Nexus S */ + *devCnt = 0; + + ret = rfalNfcfPollerPoll( RFAL_FELICA_16_SLOTS, RFAL_NFCF_SYSTEMCODE, RFAL_FELICA_POLL_RC_NO_REQUEST, gRfalNfcfGreedyF.POLL_F, &gRfalNfcfGreedyF.pollFound, &gRfalNfcfGreedyF.pollCollision ); + if( ret == ERR_NONE ) + { + rfalNfcfComputeValidSENF( nfcfDevList, devCnt, devLimit, false, &nfcDepFound ); + } + + /*******************************************************************************/ + /* ACTIVITY 1.1 - 9.3.6.63 Check if any device supports NFC DEP */ + /*******************************************************************************/ + if( nfcDepFound && (compMode == RFAL_COMPLIANCE_MODE_NFC) ) + { + ret = rfalNfcfPollerPoll( RFAL_FELICA_16_SLOTS, RFAL_NFCF_SYSTEMCODE, RFAL_FELICA_POLL_RC_SYSTEM_CODE, gRfalNfcfGreedyF.POLL_F, &gRfalNfcfGreedyF.pollFound, &gRfalNfcfGreedyF.pollCollision ); + if( ret == ERR_NONE ) + { + rfalNfcfComputeValidSENF( nfcfDevList, devCnt, devLimit, true, &nfcDepFound ); + } + } + } + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcfPollerCheck( const uint8_t* nfcid2, const rfalNfcfServBlockListParam *servBlock, uint8_t *rxBuf, uint16_t rxBufLen, uint16_t *rcvdLen ) +{ + uint8_t txBuf[RFAL_NFCF_CHECK_REQ_MAX_LEN]; + uint8_t msgIt; + uint8_t i; + ReturnCode ret; + uint8_t *checkRes; + + /* Check parameters */ + if( (nfcid2 == NULL) || (rxBuf == NULL) || (servBlock == NULL) || + (servBlock->numBlock == 0U) || (servBlock->numBlock > RFAL_NFCF_CHECK_REQ_MAX_BLOCK) || + (servBlock->numServ == 0U) || (servBlock->numServ > RFAL_NFCF_CHECK_REQ_MAX_SERV) || + (rxBufLen < (RFAL_NFCF_LENGTH_LEN + RFAL_NFCF_CHECK_RES_MIN_LEN)) ) + { + return ERR_PARAM; + } + + msgIt = 0; + + /*******************************************************************************/ + /* Compose CHECK command/request */ + + txBuf[msgIt++] = RFAL_NFCF_CMD_READ_WITHOUT_ENCRYPTION; /* Command Code */ + + ST_MEMCPY( &txBuf[msgIt], nfcid2, RFAL_NFCF_NFCID2_LEN ); /* NFCID2 */ + msgIt += RFAL_NFCF_NFCID2_LEN; + + txBuf[msgIt++] = servBlock->numServ; /* NoS */ + for( i = 0; i < servBlock->numServ; i++) + { + txBuf[msgIt++] = (uint8_t)((servBlock->servList[i] >> 0U) & 0xFFU); /* Service Code */ + txBuf[msgIt++] = (uint8_t)((servBlock->servList[i] >> 8U) & 0xFFU); + } + + txBuf[msgIt++] = servBlock->numBlock; /* NoB */ + for( i = 0; i < servBlock->numBlock; i++) + { + txBuf[msgIt++] = servBlock->blockList[i].conf; /* Block list element conf (Flag|Access|Service) */ + if( (servBlock->blockList[i].conf & 0x80U) != 0U ) /* Check if 2 or 3 byte block list element */ + { + txBuf[msgIt++] = (uint8_t)(servBlock->blockList[i].blockNum & 0xFFU); /* 1byte Block Num */ + } + else + { + txBuf[msgIt++] = (uint8_t)((servBlock->blockList[i].blockNum >> 0U) & 0xFFU); /* 2byte Block Num */ + txBuf[msgIt++] = (uint8_t)((servBlock->blockList[i].blockNum >> 8U) & 0xFFU); + } + } + + /*******************************************************************************/ + /* Transceive CHECK command/request */ + ret = rfalTransceiveBlockingTxRx( txBuf, msgIt, rxBuf, rxBufLen, rcvdLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_NFCF_MRT_CHECK_UPDATE ); + + if( ret == ERR_NONE ) + { + /* Skip LEN byte */ + checkRes = (rxBuf + RFAL_NFCF_LENGTH_LEN); + + /* Check response length */ + if( *rcvdLen < (RFAL_NFCF_LENGTH_LEN + RFAL_NFCF_CHECKUPDATE_RES_ST2_POS) ) + { + ret = ERR_PROTO; + } + /* Check for a valid response */ + else if( (checkRes[RFAL_NFCF_CMD_POS] != (uint8_t)RFAL_NFCF_CMD_READ_WITHOUT_ENCRYPTION_RES) || + (checkRes[RFAL_NFCF_CHECKUPDATE_RES_ST1_POS] != RFAL_NFCF_STATUS_FLAG_SUCCESS) || + (checkRes[RFAL_NFCF_CHECKUPDATE_RES_ST2_POS] != RFAL_NFCF_STATUS_FLAG_SUCCESS) ) + { + ret = ERR_REQUEST; + } + /* CHECK succesfull, remove header */ + else + { + (*rcvdLen) -= (RFAL_NFCF_LENGTH_LEN + RFAL_NFCF_CHECKUPDATE_RES_NOB_POS); + + if( *rcvdLen > 0U ) + { + ST_MEMMOVE( rxBuf, &checkRes[RFAL_NFCF_CHECKUPDATE_RES_NOB_POS], (*rcvdLen) ); + } + } + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalNfcfPollerUpdate( const uint8_t* nfcid2, const rfalNfcfServBlockListParam *servBlock, uint8_t *txBuf, uint16_t txBufLen, const uint8_t *blockData, uint8_t *rxBuf, uint16_t rxBufLen ) +{ + uint8_t i; + uint16_t msgIt; + uint16_t rcvdLen; + uint16_t auxLen; + uint8_t *updateRes; + ReturnCode ret; + + /* Check parameters */ + if( (nfcid2 == NULL) || (rxBuf == NULL) || (servBlock == NULL) || (txBuf == NULL) || + (servBlock->numBlock == 0U) || (servBlock->numBlock > RFAL_NFCF_UPDATE_REQ_MAX_BLOCK) || + (servBlock->numServ == 0U) || (servBlock->numServ > RFAL_NFCF_UPDATE_REQ_MAX_SERV) || + (rxBufLen < (RFAL_NFCF_LENGTH_LEN + RFAL_NFCF_UPDATE_RES_MIN_LEN)) ) + { + return ERR_PARAM; + } + + /* Calculate required txBuffer lenth */ + auxLen = (uint16_t)( RFAL_NFCF_CMD_LEN + RFAL_NFCF_NFCID2_LEN + ( servBlock->numServ * sizeof(rfalNfcfServ) ) + + (servBlock->numBlock * sizeof(rfalNfcfBlockListElem)) + (uint16_t)((uint16_t)servBlock->numBlock * RFAL_NFCF_BLOCK_LEN) ); + + /* Check whether the provided buffer is sufficient for this request */ + if( txBufLen < auxLen ) + { + return ERR_PARAM; + } + + msgIt = 0; + + /*******************************************************************************/ + /* Compose UPDATE command/request */ + + txBuf[msgIt++] = RFAL_NFCF_CMD_WRITE_WITHOUT_ENCRYPTION; /* Command Code */ + + ST_MEMCPY( &txBuf[msgIt], nfcid2, RFAL_NFCF_NFCID2_LEN ); /* NFCID2 */ + msgIt += RFAL_NFCF_NFCID2_LEN; + + txBuf[msgIt++] = servBlock->numServ; /* NoS */ + for( i = 0; i < servBlock->numServ; i++) + { + txBuf[msgIt++] = (uint8_t)((servBlock->servList[i] >> 0U) & 0xFFU); /* Service Code */ + txBuf[msgIt++] = (uint8_t)((servBlock->servList[i] >> 8U) & 0xFFU); + } + + txBuf[msgIt++] = servBlock->numBlock; /* NoB */ + for( i = 0; i < servBlock->numBlock; i++) + { + txBuf[msgIt++] = servBlock->blockList[i].conf; /* Block list element conf (Flag|Access|Service) */ + if( (servBlock->blockList[i].conf & 0x80U) != 0U ) /* Check if 2 or 3 byte block list element */ + { + txBuf[msgIt++] = (uint8_t)(servBlock->blockList[i].blockNum & 0xFFU); /* 1byte Block Num */ + } + else + { + txBuf[msgIt++] = (uint8_t)((servBlock->blockList[i].blockNum >> 0U) & 0xFFU); /* 2byte Block Num */ + txBuf[msgIt++] = (uint8_t)((servBlock->blockList[i].blockNum >> 8U) & 0xFFU); + } + } + + auxLen = ((uint16_t)servBlock->numBlock * RFAL_NFCF_BLOCK_LEN); + ST_MEMCPY( &txBuf[msgIt], blockData, auxLen ); /* Block Data */ + msgIt += auxLen; + + + /*******************************************************************************/ + /* Transceive UPDATE command/request */ + ret = rfalTransceiveBlockingTxRx( txBuf, msgIt, rxBuf, rxBufLen, &rcvdLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_NFCF_MRT_CHECK_UPDATE ); + + if( ret == ERR_NONE ) + { + /* Skip LEN byte */ + updateRes = (rxBuf + RFAL_NFCF_LENGTH_LEN); + + /* Check response length */ + if( rcvdLen < (RFAL_NFCF_LENGTH_LEN + RFAL_NFCF_CHECKUPDATE_RES_ST2_POS) ) + { + ret = ERR_PROTO; + } + /* Check for a valid response */ + else if( (updateRes[RFAL_NFCF_CMD_POS] != (uint8_t)RFAL_NFCF_CMD_WRITE_WITHOUT_ENCRYPTION_RES) || + (updateRes[RFAL_NFCF_CHECKUPDATE_RES_ST1_POS] != RFAL_NFCF_STATUS_FLAG_SUCCESS) || + (updateRes[RFAL_NFCF_CHECKUPDATE_RES_ST2_POS] != RFAL_NFCF_STATUS_FLAG_SUCCESS) ) + { + ret = ERR_REQUEST; + } + else + { + /* MISRA 15.7 - Empty else */ + } + } + + return ret; +} + + + +/*******************************************************************************/ +bool rfalNfcfListenerIsT3TReq( const uint8_t* buf, uint16_t bufLen, uint8_t* nfcid2 ) +{ + /* Check cmd byte */ + switch( *buf ) + { + case RFAL_NFCF_CMD_READ_WITHOUT_ENCRYPTION: + if( bufLen < RFAL_NFCF_READ_WO_ENCRYPTION_MIN_LEN ) + { + return false; + } + break; + + case RFAL_NFCF_CMD_WRITE_WITHOUT_ENCRYPTION: + if( bufLen < RFAL_NFCF_WRITE_WO_ENCRYPTION_MIN_LEN ) + { + return false; + } + break; + + default: + return false; + } + + /* Output NFID2 if requested */ + if( nfcid2 != NULL ) + { + ST_MEMCPY( nfcid2, &buf[RFAL_NFCF_CMD_LEN], RFAL_NFCF_NFCID2_LEN ); + } + + return true; +} + +#endif /* RFAL_FEATURE_NFCF */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_nfcv.c b/Software/fab-reader2-c/components/rfal/Src/rfal_nfcv.c new file mode 100644 index 0000000..b38c6ba --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_nfcv.c @@ -0,0 +1,874 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_nfcv.c + * + * \author Gustavo Patricio + * + * \brief Implementation of NFC-V Poller (ISO15693) device + * + * The definitions and helpers methods provided by this module are + * aligned with NFC-V (ISO15693) + * + * The definitions and helpers methods provided by this module + * are aligned with NFC-V Digital 2.1 + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_nfcv.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_NFCV + #define RFAL_FEATURE_NFCV false /* NFC-V module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_NFCV + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_NFCV_INV_REQ_FLAG 0x06U /*!< INVENTORY_REQ INV_FLAG Digital 2.1 9.6.1 */ +#define RFAL_NFCV_MASKVAL_MAX_LEN 8U /*!< Mask value max length: 64 bits (UID length) */ +#define RFAL_NFCV_MASKVAL_MAX_1SLOT_LEN 64U /*!< Mask value max length in 1 Slot mode in bits Digital 2.1 9.6.1.6 */ +#define RFAL_NFCV_MASKVAL_MAX_16SLOT_LEN 60U /*!< Mask value max length in 16 Slot mode in bits Digital 2.1 9.6.1.6 */ +#define RFAL_NFCV_MAX_SLOTS 16U /*!< NFC-V max number of Slots */ +#define RFAL_NFCV_INV_REQ_HEADER_LEN 3U /*!< INVENTORY_REQ header length (INV_FLAG, CMD, MASK_LEN) */ +#define RFAL_NFCV_INV_RES_LEN 10U /*!< INVENTORY_RES length */ +#define RFAL_NFCV_WR_MUL_REQ_HEADER_LEN 4U /*!< Write Multiple header length (INV_FLAG, CMD, [UID], BNo, Bno) */ + + +#define RFAL_CMD_LEN 1U /*!< Commandbyte length */ +#define RFAL_NFCV_FLAG_POS 0U /*!< Flag byte position */ +#define RFAL_NFCV_FLAG_LEN 1U /*!< Flag byte length */ +#define RFAL_NFCV_DATASTART_POS 1U /*!< Position of start of data */ +#define RFAL_NFCV_DSFI_LEN 1U /*!< DSFID length */ +#define RFAL_NFCV_SLPREQ_REQ_FLAG 0x22U /*!< SLPV_REQ request flags Digital 2.0 (Candidate) 9.7.1.1 */ + +#define RFAL_NFCV_MAX_COLL_SUPPORTED 16U /*!< Maximum number of collisions supported by the Anticollision loop */ + +#define RFAL_FDT_POLL_MAX rfalConvMsTo1fc(20) /*!< Maximum Wait time FDTV,EOF 20 ms Digital 2.0 B.5 */ + + + +/*! Time from special frame to EOF + * ISO15693 2009 10.4.2 : 20ms + * NFC Forum defines Digital 2.0 9.7.4 : FDTV,EOF = [10 ; 20]ms + */ +#define RFAL_NFCV_FDT_EOF 20U + + + +/*! Time between slots - ISO 15693 defines t3min depending on modulation depth and data rate. + * With only high-bitrate supported, AM modulation and a length of 12 bytes (96bits) for INV_RES we get: + * - ISO t3min = 96/26 ms + 300us = 4 ms + * - NFC Forum defines FDTV,INVENT_NORES = (4394 + 2048)/fc. Digital 2.0 B.5*/ +#define RFAL_NFCV_FDT_V_INVENT_NORES 4U + + + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! NFC-V INVENTORY_REQ format Digital 2.0 9.6.1 */ +typedef struct +{ + uint8_t INV_FLAG; /*!< Inventory Flags */ + uint8_t CMD; /*!< Command code: 01h */ + uint8_t MASK_LEN; /*!< Mask Value Length */ + uint8_t MASK_VALUE[RFAL_NFCV_MASKVAL_MAX_LEN]; /*!< Mask Value */ +} rfalNfcvInventoryReq; + + +/*! NFC-V SLP_REQ format Digital 2.0 (Candidate) 9.7.1 */ +typedef struct +{ + uint8_t REQ_FLAG; /*!< Request Flags */ + uint8_t CMD; /*!< Command code: 02h */ + uint8_t UID[RFAL_NFCV_UID_LEN]; /*!< Mask Value */ +} rfalNfcvSlpvReq; + + +/*! Container for a collision found during Anticollision loop */ +typedef struct +{ + uint8_t maskLen; + uint8_t maskVal[RFAL_NFCV_MASKVAL_MAX_LEN]; +}rfalNfcvCollision; + + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +static ReturnCode rfalNfcvParseError( uint8_t err ); + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ + +/* +****************************************************************************** +* LOCAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +static ReturnCode rfalNfcvParseError( uint8_t err ) +{ + switch(err) + { + case RFAL_NFCV_ERROR_CMD_NOT_SUPPORTED: + case RFAL_NFCV_ERROR_OPTION_NOT_SUPPORTED: + return ERR_NOTSUPP; + + case RFAL_NFCV_ERROR_CMD_NOT_RECOGNIZED: + return ERR_PROTO; + + case RFAL_NFCV_ERROR_WRITE_FAILED: + return ERR_WRITE; + + default: + return ERR_REQUEST; + } +} + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerInitialize( void ) +{ + ReturnCode ret; + + EXIT_ON_ERR( ret, rfalSetMode( RFAL_MODE_POLL_NFCV, RFAL_BR_26p48, RFAL_BR_26p48 ) ); + rfalSetErrorHandling( RFAL_ERRORHANDLING_NFC ); + + rfalSetGT( RFAL_GT_NFCV ); + rfalSetFDTListen( RFAL_FDT_LISTEN_NFCV_POLLER ); + rfalSetFDTPoll( RFAL_FDT_POLL_NFCV_POLLER ); + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerCheckPresence( rfalNfcvInventoryRes *invRes ) +{ + ReturnCode ret; + + /* INVENTORY_REQ with 1 slot and no Mask Activity 2.0 (Candidate) 9.2.3.32 */ + ret = rfalNfcvPollerInventory( RFAL_NFCV_NUM_SLOTS_1, 0, NULL, invRes, NULL ); + + if( (ret == ERR_RF_COLLISION) || (ret == ERR_CRC) || + (ret == ERR_FRAMING) || (ret == ERR_PROTO) ) + { + ret = ERR_NONE; + } + + return ret; +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerInventory( rfalNfcvNumSlots nSlots, uint8_t maskLen, const uint8_t *maskVal, rfalNfcvInventoryRes *invRes, uint16_t* rcvdLen ) +{ + ReturnCode ret; + rfalNfcvInventoryReq invReq; + uint16_t rxLen; + + if( ((maskVal == NULL) && (maskLen != 0U)) || (invRes == NULL) ) + { + return ERR_PARAM; + } + + invReq.INV_FLAG = (RFAL_NFCV_INV_REQ_FLAG | (uint8_t)nSlots); + invReq.CMD = RFAL_NFCV_CMD_INVENTORY; + invReq.MASK_LEN = (uint8_t)MIN( maskLen, ((nSlots == RFAL_NFCV_NUM_SLOTS_1) ? RFAL_NFCV_MASKVAL_MAX_1SLOT_LEN : RFAL_NFCV_MASKVAL_MAX_16SLOT_LEN) ); /* Digital 2.0 9.6.1.6 */ + + if( rfalConvBitsToBytes(invReq.MASK_LEN) > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY( invReq.MASK_VALUE, maskVal, rfalConvBitsToBytes(invReq.MASK_LEN) ); + } + + ret = rfalISO15693TransceiveAnticollisionFrame( (uint8_t*)&invReq, (uint8_t)(RFAL_NFCV_INV_REQ_HEADER_LEN + rfalConvBitsToBytes(invReq.MASK_LEN)), (uint8_t*)invRes, sizeof(rfalNfcvInventoryRes), &rxLen ); + + /* Check for optional output parameter */ + if( rcvdLen != NULL ) + { + *rcvdLen = rxLen; + } + + if( ret == ERR_NONE ) + { + if( rxLen != rfalConvBytesToBits(RFAL_NFCV_INV_RES_LEN + RFAL_NFCV_CRC_LEN) ) + { + return ERR_PROTO; + } + } + + return ret; +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerCollisionResolution( rfalComplianceMode compMode, uint8_t devLimit, rfalNfcvListenDevice *nfcvDevList, uint8_t *devCnt ) +{ + ReturnCode ret; + uint8_t slotNum; + uint16_t rcvdLen; + uint8_t colIt; + uint8_t colCnt; + uint8_t colPos; + bool colPending; + rfalNfcvCollision colFound[RFAL_NFCV_MAX_COLL_SUPPORTED]; + + + if( (nfcvDevList == NULL) || (devCnt == NULL) ) + { + return ERR_PARAM; + } + + /* Initialize parameters */ + *devCnt = 0; + colIt = 0; + colCnt = 0; + colPending = false; + ST_MEMSET(colFound, 0x00, (sizeof(rfalNfcvCollision)*RFAL_NFCV_MAX_COLL_SUPPORTED) ); + + if( devLimit > 0U ) /* MISRA 21.18 */ + { + ST_MEMSET(nfcvDevList, 0x00, (sizeof(rfalNfcvListenDevice)*devLimit) ); + } + + NO_WARNING(colPending); /* colPending is not exposed externally, in future it might become exposed/ouput parameter */ + + if( compMode == RFAL_COMPLIANCE_MODE_NFC ) + { + /* Send INVENTORY_REQ with one slot Activity 2.0 9.3.7.1 (Symbol 0) */ + ret = rfalNfcvPollerInventory( RFAL_NFCV_NUM_SLOTS_1, 0, NULL, &nfcvDevList->InvRes, NULL ); + + if( ret == ERR_TIMEOUT ) /* Exit if no device found Activity 2.0 9.3.7.2 (Symbol 1) */ + { + return ERR_NONE; + } + if( ret == ERR_NONE ) /* Device found without transmission error/collision Activity 2.0 9.3.7.3 (Symbol 2) */ + { + (*devCnt)++; + return ERR_NONE; + } + + /* A Collision has been identified Activity 2.0 9.3.7.2 (Symbol 3) */ + colPending = true; + colCnt = 1; + + /* Check if the Collision Resolution is set to perform only Collision detection Activity 2.0 9.3.7.5 (Symbol 4)*/ + if( devLimit == 0U ) + { + return ERR_RF_COLLISION; + } + + platformDelay(RFAL_NFCV_FDT_V_INVENT_NORES); + + /*******************************************************************************/ + /* Collisions pending, Anticollision loop must be executed */ + /*******************************************************************************/ + } + else + { + /* Advance to 16 slots below without mask. Will give a good chance to identify multiple cards */ + colPending = true; + colCnt = 1; + } + + + /* Execute until all collisions are resolved Activity 2.0 9.3.7.16 (Symbol 17) */ + do + { + /* Activity 2.0 9.3.7.5 (Symbol 6) */ + colPending = false; + slotNum = 0; + + do + { + if( slotNum == 0U ) + { + /* Send INVENTORY_REQ with 16 slots Activity 2.0 9.3.7.7 (Symbol 8) */ + ret = rfalNfcvPollerInventory( RFAL_NFCV_NUM_SLOTS_16, colFound[colIt].maskLen, colFound[colIt].maskVal, &nfcvDevList[(*devCnt)].InvRes, &rcvdLen ); + } + else + { + ret = rfalISO15693TransceiveEOFAnticollision( (uint8_t*)&nfcvDevList[(*devCnt)].InvRes, sizeof(rfalNfcvInventoryRes), &rcvdLen ); + } + slotNum++; + + /*******************************************************************************/ + if( ret != ERR_TIMEOUT ) + { + if( rcvdLen < rfalConvBytesToBits(RFAL_NFCV_INV_RES_LEN + RFAL_NFCV_CRC_LEN) ) + { /* If only a partial frame was received make sure the FDT_V_INVENT_NORES is fulfilled */ + platformDelay(RFAL_NFCV_FDT_V_INVENT_NORES); + } + + if( ret == ERR_NONE ) + { + /* Check if the device found is already on the list and its response is a valid INVENTORY_RES */ + if( rcvdLen == rfalConvBytesToBits(RFAL_NFCV_INV_RES_LEN + RFAL_NFCV_CRC_LEN) ) + { + /* Activity 2.0 9.3.7.15 (Symbol 11) */ + (*devCnt)++; + } + } + else /* Treat everything else as collision */ + { + /* Activity 2.0 9.3.7.15 (Symbol 16) */ + colPending = true; + + + /*******************************************************************************/ + /* Ensure that this collision still fits on the container */ + if( colCnt < RFAL_NFCV_MAX_COLL_SUPPORTED ) + { + /* Store this collision on the container to be resolved later */ + /* Activity 2.0 9.3.7.15 (Symbol 16): add the collision information + * (MASK_VAL + SN) to the list containing the collision information */ + ST_MEMCPY(colFound[colCnt].maskVal, colFound[colIt].maskVal, RFAL_NFCV_UID_LEN); + colPos = colFound[colIt].maskLen; + colFound[colCnt].maskVal[(colPos/RFAL_BITS_IN_BYTE)] &= (uint8_t)((1U << (colPos % RFAL_BITS_IN_BYTE)) - 1U); + colFound[colCnt].maskVal[(colPos/RFAL_BITS_IN_BYTE)] |= (uint8_t)((slotNum-1U) << (colPos % RFAL_BITS_IN_BYTE)); + colFound[colCnt].maskVal[((colPos/RFAL_BITS_IN_BYTE)+1U)] = (uint8_t)((slotNum-1U) >> (RFAL_BITS_IN_BYTE - (colPos % RFAL_BITS_IN_BYTE))); + + colFound[colCnt].maskLen = (colFound[colIt].maskLen + 4U); + + colCnt++; + } + } + } + else + { + /* Timeout */ + platformDelay(RFAL_NFCV_FDT_V_INVENT_NORES); + } + + /* Check if devices found have reached device limit Activity 2.0 9.3.7.15 (Symbol 16) */ + if( *devCnt >= devLimit ) + { + return ERR_NONE; + } + } while( slotNum < RFAL_NFCV_MAX_SLOTS ); /* Slot loop */ + colIt++; + } while( colIt < colCnt ); /* Collisions found loop */ + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerSleepCollisionResolution( uint8_t devLimit, rfalNfcvListenDevice *nfcvDevList, uint8_t *devCnt ) +{ + uint8_t locDevCnt; + ReturnCode ret; + uint8_t i; + + if( (nfcvDevList == NULL) || (devCnt == NULL) ) + { + return ERR_PARAM; + } + + *devCnt = 0; + + do + { + locDevCnt = 0; + ret = rfalNfcvPollerCollisionResolution( RFAL_COMPLIANCE_MODE_ISO, (devLimit - *devCnt), &nfcvDevList[*devCnt], &locDevCnt ); + + for( i = *devCnt; i < (*devCnt + locDevCnt); i++ ) + { + rfalNfcvPollerSleep( 0x00, nfcvDevList[i].InvRes.UID ); + nfcvDevList[i].isSleep = true; + } + *devCnt += locDevCnt; + } + while( (locDevCnt > 0U) && (*devCnt < devLimit) ); + + return ret; +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerSleep( uint8_t flags, const uint8_t* uid ) +{ + ReturnCode ret; + rfalNfcvSlpvReq slpReq; + uint8_t rxBuf; /* dummy buffer, just to perform Rx */ + + if( uid == NULL ) + { + return ERR_PARAM; + } + + /* Compute SLPV_REQ */ + slpReq.REQ_FLAG = (flags | (uint8_t)RFAL_NFCV_REQ_FLAG_ADDRESS); /* Should be with UID according Digital 2.0 (Candidate) 9.7.1.1 */ + slpReq.CMD = RFAL_NFCV_CMD_SLPV; + ST_MEMCPY( slpReq.UID, uid, RFAL_NFCV_UID_LEN ); + + /* NFC Forum device SHALL wait at least FDTVpp to consider the SLPV acknowledged (FDTVpp = FDTVpoll) Digital 2.0 (Candidate) 9.7 9.8.2 */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&slpReq, sizeof(rfalNfcvSlpvReq), &rxBuf, sizeof(rxBuf), NULL, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_NFCV_POLLER ); + if( ret != ERR_TIMEOUT ) + { + return ret; + } + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerSelect( uint8_t flags, const uint8_t* uid ) +{ + uint16_t rcvLen; + rfalNfcvGenericRes res; + + if( uid == NULL ) + { + return ERR_PARAM; + } + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_SELECT, flags, RFAL_NFCV_PARAM_SKIP, uid, NULL, 0U, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerReadSingleBlock( uint8_t flags, const uint8_t* uid, uint8_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t bn; + + bn = blockNum; + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_READ_SINGLE_BLOCK, flags, RFAL_NFCV_PARAM_SKIP, uid, &bn, sizeof(uint8_t), rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerWriteSingleBlock( uint8_t flags, const uint8_t* uid, uint8_t blockNum, const uint8_t* wrData, uint8_t blockLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_LEN + RFAL_NFCV_MAX_BLOCK_LEN)]; + uint8_t dataLen; + uint16_t rcvLen; + rfalNfcvGenericRes res; + + /* Check for valid parameters */ + if( (blockLen == 0U) || (blockLen > (uint8_t)RFAL_NFCV_MAX_BLOCK_LEN) || (wrData == NULL) ) + { + return ERR_PARAM; + } + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = blockNum; /* Set Block Number (8 bits) */ + ST_MEMCPY( &data[dataLen], wrData, blockLen ); /* Append Block data to write */ + dataLen += blockLen; + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_WRITE_SINGLE_BLOCK, flags, RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerLockBlock( uint8_t flags, const uint8_t* uid, uint8_t blockNum ) +{ + uint16_t rcvLen; + rfalNfcvGenericRes res; + uint8_t bn; + + bn = blockNum; + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_LOCK_BLOCK, flags, RFAL_NFCV_PARAM_SKIP, uid, &bn, sizeof(uint8_t), (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint8_t firstBlockNum, uint8_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_LEN + RFAL_NFCV_BLOCKNUM_LEN)]; + uint8_t dataLen; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = firstBlockNum; /* Set first Block Number */ + data[dataLen++] = numOfBlocks; /* Set number of blocks to read */ + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_READ_MULTIPLE_BLOCKS, flags, RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerWriteMultipleBlocks( uint8_t flags, const uint8_t* uid, uint8_t firstBlockNum, uint8_t numOfBlocks, uint8_t *txBuf, uint16_t txBufLen, uint8_t blockLen, const uint8_t* wrData, uint16_t wrDataLen ) +{ + ReturnCode ret; + uint16_t rcvLen; + uint16_t reqLen; + rfalNfcvGenericRes res; + uint16_t msgIt; + + /* Calculate required buffer length */ + reqLen = (uint16_t)((uid != NULL) ? (RFAL_NFCV_WR_MUL_REQ_HEADER_LEN + RFAL_NFCV_UID_LEN + wrDataLen) : (RFAL_NFCV_WR_MUL_REQ_HEADER_LEN + wrDataLen)); + + if( (reqLen > txBufLen) || (blockLen > (uint8_t)RFAL_NFCV_MAX_BLOCK_LEN) || ((((uint16_t)numOfBlocks) * (uint16_t)blockLen) != wrDataLen) || (numOfBlocks == 0U) || (wrData == NULL) ) + { + return ERR_PARAM; + } + + msgIt = 0; + + /* Compute Request Command */ + txBuf[msgIt++] = (uint8_t)(flags & (~((uint32_t)RFAL_NFCV_REQ_FLAG_ADDRESS) & ~((uint32_t)RFAL_NFCV_REQ_FLAG_SELECT))); + txBuf[msgIt++] = RFAL_NFCV_CMD_WRITE_MULTIPLE_BLOCKS; + + /* Check if Request is to be sent in Addressed or Selected mode */ + if( uid != NULL ) + { + txBuf[RFAL_NFCV_FLAG_POS] |= (uint8_t)RFAL_NFCV_REQ_FLAG_ADDRESS; + ST_MEMCPY( &txBuf[msgIt], uid, RFAL_NFCV_UID_LEN ); + msgIt += (uint8_t)RFAL_NFCV_UID_LEN; + } + else + { + txBuf[RFAL_NFCV_FLAG_POS] |= (uint8_t)RFAL_NFCV_REQ_FLAG_SELECT; + } + + txBuf[msgIt++] = firstBlockNum; + txBuf[msgIt++] = (numOfBlocks - 1U); + + if( wrDataLen > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY( &txBuf[msgIt], wrData, wrDataLen ); + msgIt += wrDataLen; + } + + /* Transceive Command */ + ret = rfalTransceiveBlockingTxRx( txBuf, msgIt, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_MAX ); + + if( ret != ERR_NONE ) + { + return ret; + } + + /* Check if the response minimum length has been received */ + if( rcvLen < (uint8_t)RFAL_NFCV_FLAG_LEN ) + { + return ERR_PROTO; + } + + /* Check if an error has been signalled */ + if( (res.RES_FLAG & (uint8_t)RFAL_NFCV_RES_FLAG_ERROR) != 0U ) + { + return rfalNfcvParseError( *res.data ); + } + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerExtendedReadSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[RFAL_NFCV_BLOCKNUM_EXTENDED_LEN]; + uint8_t dataLen; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)blockNum; /* TS T5T 1.0 BNo is considered as a multi-byte field. TS T5T 1.0 5.1.1.13 multi-byte field follows [DIGITAL]. [DIGITAL] 9.3.1 A multiple byte field is transmitted LSB first. */ + data[dataLen++] = (uint8_t)((blockNum >> 8U) & 0xFFU); + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_EXTENDED_READ_SINGLE_BLOCK, flags, RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerExtendedWriteSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, const uint8_t* wrData, uint8_t blockLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_EXTENDED_LEN + RFAL_NFCV_MAX_BLOCK_LEN)]; + uint8_t dataLen; + uint16_t rcvLen; + rfalNfcvGenericRes res; + + /* Check for valid parameters */ + if( (blockLen == 0U) || (blockLen > (uint8_t)RFAL_NFCV_MAX_BLOCK_LEN) ) + { + return ERR_PARAM; + } + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)blockNum; /* TS T5T 1.0 BNo is considered as a multi-byte field. TS T5T 1.0 5.1.1.13 multi-byte field follows [DIGITAL]. [DIGITAL] 9.3.1 A multiple byte field is transmitted LSB first. */ + data[dataLen++] = (uint8_t)((blockNum >> 8U) & 0xFFU); + ST_MEMCPY( &data[dataLen], wrData, blockLen ); /* Append Block data to write */ + dataLen += blockLen; + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_EXTENDED_WRITE_SINGLE_BLOCK, flags, RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerExtendedLockSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum ) +{ + uint8_t data[RFAL_NFCV_BLOCKNUM_EXTENDED_LEN]; + uint8_t dataLen; + uint16_t rcvLen; + rfalNfcvGenericRes res; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)blockNum; /* TS T5T 1.0 BNo is considered as a multi-byte field. TS T5T 1.0 5.1.1.13 multi-byte field follows [DIGITAL]. [DIGITAL] 9.3.1 A multiple byte field is transmitted LSB first. */ + data[dataLen++] = (uint8_t)((blockNum >> 8U) & 0xFFU); + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_EXTENDED_LOCK_SINGLE_BLOCK, flags, RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerExtendedReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint16_t firstBlockNum, uint16_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_EXTENDED_LEN + RFAL_NFCV_BLOCKNUM_EXTENDED_LEN)]; + uint8_t dataLen; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)((firstBlockNum >> 0U) & 0xFFU); + data[dataLen++] = (uint8_t)((firstBlockNum >> 8U) & 0xFFU); + data[dataLen++] = (uint8_t)((numOfBlocks >> 0U) & 0xFFU); + data[dataLen++] = (uint8_t)((numOfBlocks >> 8U) & 0xFFU); + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_EXTENDED_READ_MULTIPLE_BLOCK, flags, RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerExtendedWriteMultipleBlocks( uint8_t flags, const uint8_t* uid, uint16_t firstBlockNum, uint16_t numOfBlocks, uint8_t *txBuf, uint16_t txBufLen, uint8_t blockLen, const uint8_t* wrData, uint16_t wrDataLen ) +{ + ReturnCode ret; + uint16_t rcvLen; + uint16_t reqLen; + rfalNfcvGenericRes res; + uint16_t msgIt; + uint16_t nBlocks; + + /* Calculate required buffer length */ + reqLen = ((uid != NULL) ? (RFAL_NFCV_WR_MUL_REQ_HEADER_LEN + RFAL_NFCV_UID_LEN + wrDataLen) : (RFAL_NFCV_WR_MUL_REQ_HEADER_LEN + wrDataLen) ); + + if( (reqLen > txBufLen) || (blockLen > (uint8_t)RFAL_NFCV_MAX_BLOCK_LEN) || (( (uint16_t)numOfBlocks * (uint16_t)blockLen) != wrDataLen) || (numOfBlocks == 0U) ) + { + return ERR_PARAM; + } + + msgIt = 0; + nBlocks = (numOfBlocks - 1U); + + /* Compute Request Command */ + txBuf[msgIt++] = (uint8_t)(flags & (~((uint32_t)RFAL_NFCV_REQ_FLAG_ADDRESS) & ~((uint32_t)RFAL_NFCV_REQ_FLAG_SELECT))); + txBuf[msgIt++] = RFAL_NFCV_CMD_EXTENDED_WRITE_MULTIPLE_BLOCK; + + /* Check if Request is to be sent in Addressed or Selected mode */ + if( uid != NULL ) + { + txBuf[RFAL_NFCV_FLAG_POS] |= (uint8_t)RFAL_NFCV_REQ_FLAG_ADDRESS; + ST_MEMCPY( &txBuf[msgIt], uid, RFAL_NFCV_UID_LEN ); + msgIt += (uint8_t)RFAL_NFCV_UID_LEN; + } + else + { + txBuf[RFAL_NFCV_FLAG_POS] |= (uint8_t)RFAL_NFCV_REQ_FLAG_SELECT; + } + + txBuf[msgIt++] = (uint8_t)((firstBlockNum >> 0) & 0xFFU); + txBuf[msgIt++] = (uint8_t)((firstBlockNum >> 8) & 0xFFU); + txBuf[msgIt++] = (uint8_t)((nBlocks >> 0) & 0xFFU); + txBuf[msgIt++] = (uint8_t)((nBlocks >> 8) & 0xFFU); + + if( wrDataLen > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY( &txBuf[msgIt], wrData, wrDataLen ); + msgIt += wrDataLen; + } + + /* Transceive Command */ + ret = rfalTransceiveBlockingTxRx( txBuf, msgIt, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_MAX ); + + if( ret != ERR_NONE ) + { + return ret; + } + + /* Check if the response minimum length has been received */ + if( rcvLen < (uint8_t)RFAL_NFCV_FLAG_LEN ) + { + return ERR_PROTO; + } + + /* Check if an error has been signalled */ + if( (res.RES_FLAG & (uint8_t)RFAL_NFCV_RES_FLAG_ERROR) != 0U ) + { + return rfalNfcvParseError( *res.data ); + } + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerGetSystemInformation( uint8_t flags, const uint8_t* uid, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_GET_SYS_INFO, flags, RFAL_NFCV_PARAM_SKIP, uid, NULL, 0U, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerExtendedGetSystemInformation( uint8_t flags, const uint8_t* uid, uint8_t requestField, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_EXTENDED_GET_SYS_INFO, flags, requestField, uid, NULL, 0U, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalNfcvPollerTransceiveReq( uint8_t cmd, uint8_t flags, uint8_t param, const uint8_t* uid, const uint8_t *data, uint16_t dataLen, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + ReturnCode ret; + rfalNfcvGenericReq req; + uint8_t msgIt; + rfalBitRate rxBR; + bool fastMode; + + msgIt = 0; + fastMode = false; + + /* Check for valid parameters */ + if( (rxBuf == NULL) || (rcvLen == NULL) || ((dataLen > 0U) && (data == NULL)) || + (dataLen > ((uid != NULL) ? RFAL_NFCV_MAX_GEN_DATA_LEN : (RFAL_NFCV_MAX_GEN_DATA_LEN - RFAL_NFCV_UID_LEN))) ) + { + return ERR_PARAM; + } + + + /* Check if the command is an ST's Fast command */ + if( (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_READ_SINGLE_BLOCK) || (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_EXTENDED_READ_SINGLE_BLOCK) || + (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_READ_MULTIPLE_BLOCKS) || (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_EXTENDED_READ_MULTIPLE_BLOCKS) || + (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_WRITE_MESSAGE) || (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_READ_MESSAGE_LENGTH) || + (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_READ_MESSAGE) || (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_READ_DYN_CONFIGURATION) || + (cmd == (uint8_t)RFAL_NFCV_CMD_FAST_WRITE_DYN_CONFIGURATION) ) + { + /* Store current Rx bit rate and move to fast mode */ + rfalGetBitRate( NULL, &rxBR ); + rfalSetBitRate( RFAL_BR_KEEP, RFAL_BR_52p97 ); + + fastMode = true; + } + + + /* Compute Request Command */ + req.REQ_FLAG = (uint8_t)(flags & (~((uint32_t)RFAL_NFCV_REQ_FLAG_ADDRESS) & ~((uint32_t)RFAL_NFCV_REQ_FLAG_SELECT))); + req.CMD = cmd; + + /* Prepend parameter on ceratin proprietary requests: IC Manuf, Parameters */ + if( param != RFAL_NFCV_PARAM_SKIP ) + { + req.payload.data[msgIt++] = param; + } + + /* Check if request is to be sent in Addressed or Selected mode */ + if( uid != NULL ) + { + req.REQ_FLAG |= (uint8_t)RFAL_NFCV_REQ_FLAG_ADDRESS; + ST_MEMCPY( &req.payload.data[msgIt], uid, RFAL_NFCV_UID_LEN ); + msgIt += RFAL_NFCV_UID_LEN; + } + else + { + req.REQ_FLAG |= (uint8_t)RFAL_NFCV_REQ_FLAG_SELECT; + } + + if( dataLen > 0U ) + { + ST_MEMCPY( &req.payload.data[msgIt], data, dataLen); + msgIt += (uint8_t)dataLen; + } + + /* Transceive Command */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&req, (RFAL_CMD_LEN + RFAL_NFCV_FLAG_LEN +(uint16_t)msgIt), rxBuf, rxBufLen, rcvLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_MAX ); + + /* If the Option Flag is set in certain commands an EOF needs to be sent after 20ms to retrieve the VICC response ISO15693-3 2009 10.4.2 & 10.4.3 & 10.4.5 */ + if( ((flags & (uint8_t)RFAL_NFCV_REQ_FLAG_OPTION) != 0U) && ((cmd == (uint8_t)RFAL_NFCV_CMD_WRITE_SINGLE_BLOCK) || (cmd == (uint8_t)RFAL_NFCV_CMD_WRITE_MULTIPLE_BLOCKS) || + (cmd == (uint8_t)RFAL_NFCV_CMD_LOCK_BLOCK) || (cmd == (uint8_t)RFAL_NFCV_CMD_EXTENDED_WRITE_SINGLE_BLOCK) || + (cmd == (uint8_t)RFAL_NFCV_CMD_EXTENDED_LOCK_SINGLE_BLOCK) || (cmd == (uint8_t)RFAL_NFCV_CMD_EXTENDED_WRITE_MULTIPLE_BLOCK)) ) + { + ret = rfalISO15693TransceiveEOF( rxBuf, (uint8_t)rxBufLen, rcvLen ); + } + + /* Restore Rx BitRate */ + if( fastMode ) + { + rfalSetBitRate( RFAL_BR_KEEP, rxBR ); + } + + if( ret != ERR_NONE ) + { + return ret; + } + + /* Check if the response minimum length has been received */ + if( (*rcvLen) < (uint8_t)RFAL_NFCV_FLAG_LEN ) + { + return ERR_PROTO; + } + + /* Check if an error has been signalled */ + if( (rxBuf[RFAL_NFCV_FLAG_POS] & (uint8_t)RFAL_NFCV_RES_FLAG_ERROR) != 0U ) + { + return rfalNfcvParseError( rxBuf[RFAL_NFCV_DATASTART_POS] ); + } + + return ERR_NONE; +} + +#endif /* RFAL_FEATURE_NFCV */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_rfst25r3911.c b/Software/fab-reader2-c/components/rfal/Src/rfal_rfst25r3911.c new file mode 100644 index 0000000..c9f9979 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_rfst25r3911.c @@ -0,0 +1,3733 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R3911 firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Gustavo Patricio + * + * \brief RF Abstraction Layer (RFAL) + * + * RFAL implementation for ST25R3911 + */ + + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ + +#include "rfal_chip.h" +#include "utils.h" +#include "st25r3911.h" +#include "st25r3911_com.h" +#include "st25r3911_interrupt.h" +#include "rfal_analogConfig.h" +#include "rfal_iso15693_2.h" + +/* + ****************************************************************************** + * ENABLE SWITCHS + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_LISTEN_MODE + #error " RFAL: Module configuration missing. Please enable/disable support for Listen Mode: RFAL_FEATURE_LISTEN_MODE " +#endif + +#ifndef RFAL_FEATURE_WAKEUP_MODE + #error " RFAL: Module configuration missing. Please enable/disable support for Wake-Up Mode: RFAL_FEATURE_WAKEUP_MODE " +#endif + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! Struct that holds all involved on a Transceive including the context passed by the caller */ +typedef struct{ + rfalTransceiveState state; /*!< Current transceive state */ + rfalTransceiveState lastState; /*!< Last transceive state (debug purposes) */ + ReturnCode status; /*!< Current status/error of the transceive */ + bool rxse; /*!< Flag indicating if RXE was received with RXS */ + + rfalTransceiveContext ctx; /*!< The transceive context given by the caller */ +} rfalTxRx; + + +/*! Struct that holds all context for the Listen Mode */ +typedef struct{ + rfalLmState state; /*!< Current Listen Mode state */ + rfalBitRate brDetected; /*!< Last bit rate detected */ + + uint8_t* rxBuf; /*!< Location to store incoming data in Listen Mode */ + uint16_t rxBufLen; /*!< Length of rxBuf */ + uint16_t* rxLen; /*!< Pointer to write the data length placed into rxBuf */ + bool dataFlag; /*!< Listen Mode current Data Flag */ +} rfalLm; + + +/*! Struct that holds all context for the Wake-Up Mode */ +typedef struct{ + rfalWumState state; /*!< Current Wake-Up Mode state */ + rfalWakeUpConfig cfg; /*!< Current Wake-Up Mode context */ +} rfalWum; + + +/*! Struct that holds the timings GT and FDTs */ +typedef struct{ + uint32_t GT; /*!< GT in 1/fc */ + uint32_t FDTListen; /*!< FDTListen in 1/fc */ + uint32_t FDTPoll; /*!< FDTPoll in 1/fc */ +} rfalTimings; + + +/*! Struct that holds the software timers */ +typedef struct{ + uint32_t GT; /*!< RFAL's GT timer */ + uint32_t FWT; /*!< FWT/RWT timer for Active P2P*/ + uint32_t RXE; /*!< Timer between RXS and RXE */ +} rfalTimers; + + +/*! Struct that holds the RFAL's callbacks */ +typedef struct{ + rfalPreTxRxCallback preTxRx; /*!< RFAL's Pre TxRx callback */ + rfalPostTxRxCallback postTxRx; /*!< RFAL's Post TxRx callback */ +} rfalCallbacks; + + +/*! Struct that holds counters to control the FIFO on Tx and Rx */ +typedef struct{ + uint16_t expWL; /*!< The amount of bytes expected to be Tx when a WL interrupt occours */ + uint16_t bytesTotal; /*!< Total bytes to be transmitted OR the total bytes received */ + uint16_t bytesWritten;/*!< Amount of bytes already written on FIFO (Tx) OR read (RX) from FIFO and written on rxBuffer*/ + uint8_t status[ST25R3911_FIFO_STATUS_LEN]; /*!< FIFO Status Registers */ +} rfalFIFO; + + +/*! Struct that holds RFAL's configuration settings */ +typedef struct{ + uint8_t obsvModeTx; /*!< RFAL's config of the ST25R3911's observation mode while Tx */ + uint8_t obsvModeRx; /*!< RFAL's config of the ST25R3911's observation mode while Rx */ + rfalEHandling eHandling; /*!< RFAL's error handling config/mode */ +} rfalConfigs; + + +/*! Struct that holds NFC-F data - Used only inside rfalFelicaPoll() (static to avoid adding it into stack) */ +typedef struct{ + rfalFeliCaPollRes pollResponses[RFAL_FELICA_POLL_MAX_SLOTS]; /* FeliCa Poll response container for 16 slots */ +} rfalNfcfWorkingData; + + +/*! Struct that holds NFC-V current context + * + * 96 bytes is FIFO size of ST25R3911, codingBuffer has to be big enough for coping with maximum response size (Manchester coded) + * - current implementation expects it be written in one bulk into FIFO + * - needs to be above FIFO water level of ST25R3911 (64) + * - 65 is actually 1 byte too much, but ~75us in 1of256 another byte is already gone + * + * - inventory requests responses: 14 bytes + * - Max read single block responses: 32 bytes + * - Read multiple block responses: variable + * + * ISO15693 frame: SOF + Flags + Data + CRC + EOF + */ +typedef struct{ + uint8_t codingBuffer[((2 + 255 + 3)*2)];/*!< Coding buffer, length MUST be above 64: [65; ...] */ + uint16_t nfcvOffset; /*!< Offset needed for ISO15693 coding function */ + rfalTransceiveContext origCtx; /*!< Context provided by user */ + uint16_t ignoreBits; /*!< Number of bits at the beginning of a frame to be ignored when decoding*/ +} rfalNfcvWorkingData; + + +/*! RFAL instance */ +typedef struct{ + rfalState state; /*!< RFAL's current state */ + rfalMode mode; /*!< RFAL's current mode */ + rfalBitRate txBR; /*!< RFAL's current Tx Bit Rate */ + rfalBitRate rxBR; /*!< RFAL's current Rx Bit Rate */ + bool field; /*!< Current field state (On / Off) */ + + rfalConfigs conf; /*!< RFAL's configuration settings */ + rfalTimings timings; /*!< RFAL's timing setting */ + rfalTxRx TxRx; /*!< RFAL's transceive management */ + rfalFIFO fifo; /*!< RFAL's FIFO management */ + rfalTimers tmr; /*!< RFAL's Software timers */ + rfalCallbacks callbacks; /*!< RFAL's callbacks */ + +#if RFAL_FEATURE_LISTEN_MODE + rfalLm Lm; /*!< RFAL's listen mode management */ +#endif /* RFAL_FEATURE_LISTEN_MODE */ + +#if RFAL_FEATURE_WAKEUP_MODE + rfalWum wum; /*!< RFAL's Wake-up mode management */ +#endif /* RFAL_FEATURE_WAKEUP_MODE */ + +#if RFAL_FEATURE_NFCF + rfalNfcfWorkingData nfcfData; /*!< RFAL's working data when supporting NFC-F */ +#endif /* RFAL_FEATURE_NFCF */ + +#if RFAL_FEATURE_NFCV + rfalNfcvWorkingData nfcvData; /*!< RFAL's working data when supporting NFC-V */ +#endif /* RFAL_FEATURE_NFCV */ + +} rfal; + + + +/*! Felica's command set */ +typedef enum +{ + FELICA_CMD_POLLING = 0x00, /*!< Felica Poll/REQC command (aka SENSF_REQ) to identify a card */ + FELICA_CMD_POLLING_RES = 0x01, /*!< Felica Poll/REQC command (aka SENSF_RES) response */ + FELICA_CMD_REQUEST_SERVICE = 0x02, /*!< verify the existence of Area and Service */ + FELICA_CMD_REQUEST_RESPONSE = 0x04, /*!< verify the existence of a card */ + FELICA_CMD_READ_WITHOUT_ENCRYPTION = 0x06, /*!< read Block Data from a Service that requires no authentication */ + FELICA_CMD_WRITE_WITHOUT_ENCRYPTION = 0x08, /*!< write Block Data to a Service that requires no authentication */ + FELICA_CMD_REQUEST_SYSTEM_CODE = 0x0c, /*!< acquire the System Code registered to a card */ + FELICA_CMD_AUTHENTICATION1 = 0x10, /*!< authenticate a card */ + FELICA_CMD_AUTHENTICATION2 = 0x12, /*!< allow a card to authenticate a Reader/Writer */ + FELICA_CMD_READ = 0x14, /*!< read Block Data from a Service that requires authentication */ + FELICA_CMD_WRITE = 0x16, /*!< write Block Data to a Service that requires authentication */ +}t_rfalFeliCaCmd; + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ + +#define RFAL_FIFO_IN_LT_32 32U /*!< Number of bytes in the FIFO when WL interrupt occurs while Tx ( fifo_lt: 0 ) */ +#define RFAL_FIFO_IN_LT_16 16U /*!< Number of bytes in the FIFO when WL interrupt occurs while Tx ( fifo_lt: 1 ) */ + +#define RFAL_FIFO_OUT_LT_32 (ST25R3911_FIFO_DEPTH - RFAL_FIFO_IN_LT_32) /*!< Number of bytes sent/out of the FIFO when WL interrupt occurs while Tx ( fifo_lt: 0 ) */ +#define RFAL_FIFO_OUT_LT_16 (ST25R3911_FIFO_DEPTH - RFAL_FIFO_IN_LT_16) /*!< Number of bytes sent/out of the FIFO when WL interrupt occurs while Tx ( fifo_lt: 1 ) */ + +#define RFAL_FIFO_STATUS_REG1 0U /*!< Location of FIFO status register 1 in local copy */ +#define RFAL_FIFO_STATUS_REG2 1U /*!< Location of FIFO status register 2 in local copy */ +#define RFAL_FIFO_STATUS_INVALID 0xFFU /*!< Value indicating that the local FIFO status in invalid|cleared */ + +#define RFAL_ST25R3911_GPT_MAX_1FC rfalConv8fcTo1fc( 0xFFFFU ) /*!< Max GPT steps in 1fc (0xFFFF steps of 8/fc => 0xFFFF * 590ns = 38,7ms) */ +#define RFAL_ST25R3911_NRT_MAX_1FC rfalConv4096fcTo1fc( 0xFFFFU ) /*!< Max NRT steps in 1fc (0xFFFF steps of 4096/fc => 0xFFFF * 302us = 19.8s ) */ +#define RFAL_ST25R3911_NRT_DISABLED 0U /*!< NRT Disabled: All 0 No-response timer is not started, wait forever */ +#define RFAL_ST25R3911_MRT_MAX_1FC rfalConv64fcTo1fc( 0x00FFU ) /*!< Max MRT steps in 1fc (0x00FF steps of 64/fc => 0x00FF * 4.72us = 1.2ms ) */ +#define RFAL_ST25R3911_MRT_MIN_1FC rfalConv64fcTo1fc( 0x0004U ) /*!< Min MRT steps in 1fc ( 0<=mrt<=4 ; 4 (64/fc) => 0x0004 * 4.72us = 18.88us ) */ +#define RFAL_ST25R3911_GT_MAX_1FC rfalConvMsTo1fc( 5000U ) /*!< Max GT value allowed in 1/fc */ +#define RFAL_ST25R3911_GT_MIN_1FC rfalConvMsTo1fc(RFAL_ST25R3911_SW_TMR_MIN_1MS) /*!< Min GT value allowed in 1/fc */ +#define RFAL_ST25R3911_SW_TMR_MIN_1MS 1U /*!< Min value of a SW timer in ms */ + +#define RFAL_OBSMODE_DISABLE 0x00U /*!< Observation Mode disabled */ + +#define RFAL_NFC_RX_INCOMPLETE_LEN (uint8_t)1U /*!< Threshold value where incoming rx may be considered as incomplete in NFC */ +#define RFAL_EMVCO_RX_MAXLEN (uint8_t)4U /*!< Maximum value where EMVCo to apply special error handling */ +#define RFAL_EMVCO_RX_MINLEN (uint8_t)2U /*!< Minimum value where EMVCo to apply special error handling */ + +#define RFAL_NORXE_TOUT 10U /*!< Timeout to be used on a potential missing RXE - Silicon ST25R3911B Errata #1.1 */ + +#define RFAL_ISO14443A_SDD_RES_LEN 5U /*!< SDD_RES | Anticollision (UID CLn) length - rfalNfcaSddRes */ + +#define RFAL_FELICA_POLL_DELAY_TIME 512U /*!< FeliCa Poll Processing time is 2.417 ms ~512*64/fc Digital 1.1 A4 */ +#define RFAL_FELICA_POLL_SLOT_TIME 256U /*!< FeliCa Poll Time Slot duration is 1.208 ms ~256*64/fc Digital 1.1 A4 */ + +#define RFAL_ISO15693_IGNORE_BITS rfalConvBytesToBits(2U) /*!< Ignore collisions before the UID (RES_FLAG + DSFID) */ + + +/*******************************************************************************/ + +#define RFAL_LM_GT rfalConvUsTo1fc(100U) /*!< Listen Mode Guard Time enforced (GT - Passive; TIRFG - Active) */ +#define RFAL_FDT_POLL_ADJUSTMENT rfalConvUsTo1fc(80U) /*!< FDT Poll adjustment: Time between the expiration of GPT to the actual Tx */ +#define RFAL_FDT_LISTEN_MRT_ADJUSTMENT 64U /*!< MRT jitter adjustment: timeout will be between [ tout ; tout + 64 cycles ] */ +#define RFAL_AP2P_FIELDOFF_TRFW rfalConv8fcTo1fc(64U) /*!< Time after TXE and Field Off in AP2P Trfw: 37.76us -> 64 (8/fc) */ + + +/*! FWT adjustment: + * 64 : NRT jitter between TXE and NRT start */ +#define RFAL_FWT_ADJUSTMENT 64U + +/*! FWT ISO14443A adjustment: + * 512 : Initial 4bit length */ +#define RFAL_FWT_A_ADJUSTMENT 512U + +/*! FWT ISO14443B adjustment: + * 2784 : Adjustment for the SOF and initial byte */ +#define RFAL_FWT_B_ADJUSTMENT 2784U + + +/*! FWT FeliCa 212 adjustment: + * 1024 : Length of the two Sync bytes at 212kbps */ +#define RFAL_FWT_F_212_ADJUSTMENT 1024U + +/*! FWT FeliCa 424 adjustment: + * 512 : Length of the two Sync bytes at 424kbps */ +#define RFAL_FWT_F_424_ADJUSTMENT 512U + + +/*! Time between our field Off and other peer field On : Tadt + (n x Trfw) + * Ecma 340 11.1.2 - Tadt: [56.64 , 188.72] us ; n: [0 , 3] ; Trfw = 37.76 us + * Should be: 189 + (3*38) = 303us ; we'll use a more relaxed setting: 605 us */ +#define RFAL_AP2P_FIELDON_TADTTRFW rfalConvUsTo1fc(605U) + + +/*! FDT Listen adjustment for ISO14443A EMVCo 2.6 4.8.1.3 ; Digital 1.1 6.10 + * + * 276: Time from the rising pulse of the pause of the logic '1' (i.e. the time point to measure the deaftime from), + * to the actual end of the EOF sequence (the point where the MRT starts). Please note that the ST25R391x uses the + * ISO14443-2 definition where the EOF consists of logic '0' followed by sequence Y. + */ +#define RFAL_FDT_LISTEN_A_ADJUSTMENT 276U + + +/*! FDT Listen adjustment for ISO14443B EMVCo 2.6 4.8.1.6 ; Digital 1.1 7.9 + * + * 340: Time from the rising edge of the EoS to the starting point of the MRT timer (sometime after the final high + * part of the EoS is completed). + * + * -64: Adjustment for the TR1PUTMIN. + * The TR1PUTMIN of the ST25R3911 is 1152/fc (72/fs). The EMVCo test case TB0000 measures the TR1PUTMIN. + * It takes the default value of TR1PUTMIN (79/fs) and reduces it by 128/fc in every iteration. + * This results in a TR1PUTMIN of 1136/fc (71/fs) for the second iteration. The ST25R3911 sends a NAK because + * the TR1PUTMIN of the ST25R3911 (72/fs) is higher than 71/fs. + * Therefore the test suite assumes TR1PUTMIN of 1264/fc (79/fs). + * The test cases TB340.0 and TB435.0 uses the TR1PUTMIN to send frames too early. In order to correctly + * recognise these frames as being sent too early (starting inside reader deaf time), the MRT has to be + * increased by at least 64/fc (8/fs). + */ +#define RFAL_FDT_LISTEN_B_ADJUSTMENT (340U - 64U) + + +/*! FDT Listen adjustment for ISO15693 + * ISO15693 2000 8.4 t1 MIN = 4192/fc + * ISO15693 2009 9.1 t1 MIN = 4320/fc + * Digital 2.1 B.5 FDTV,LISTEN,MIN = 4310/fc + * Set FDT Listen one step earlier than on the more recent spec versions for greater interoprability + */ +#define RFAL_FDT_LISTEN_V_ADJUSTMENT 128U + + + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ + +#define rfalCalcNumBytes( nBits ) (((uint32_t)(nBits) + 7U) / 8U) /*!< Returns the number of bytes required to fit given the number of bits */ + +#define rfalTimerStart( timer, time_ms ) (timer) = platformTimerCreate((uint16_t)(time_ms)) /*!< Configures and starts the RTOX timer */ +#define rfalTimerisExpired( timer ) platformTimerIsExpired( timer ) /*!< Checks if timer has expired */ + +#define rfalST25R3911ObsModeDisable() st25r3911WriteTestRegister(0x01U, 0x00U) /*!< Disable ST25R3911 Observation mode */ +#define rfalST25R3911ObsModeTx() st25r3911WriteTestRegister(0x01U, gRFAL.conf.obsvModeTx) /*!< Enable Observation mode 0x0A CSI: Digital TX modulation signal CSO: none */ +#define rfalST25R3911ObsModeRx() st25r3911WriteTestRegister(0x01U, gRFAL.conf.obsvModeRx) /*!< Enable Observation mode 0x04 CSI: Digital output of AM channel CSO: Digital output of PM channel */ + + +#define rfalCheckDisableObsMode() if(gRFAL.conf.obsvModeRx != 0U){ rfalST25R3911ObsModeDisable(); } /*!< Checks if the observation mode is enabled, and applies on ST25R3911 */ +#define rfalCheckEnableObsModeTx() if(gRFAL.conf.obsvModeTx != 0U){ rfalST25R3911ObsModeTx(); } /*!< Checks if the observation mode is enabled, and applies on ST25R3911 */ +#define rfalCheckEnableObsModeRx() if(gRFAL.conf.obsvModeRx != 0U){ rfalST25R3911ObsModeRx(); } /*!< Checks if the observation mode is enabled, and applies on ST25R3911 */ + + +#define rfalGetIncmplBits( FIFOStatus2 ) (( (FIFOStatus2) >> 1) & 0x07U) /*!< Returns the number of bits from fifo status */ +#define rfalIsIncompleteByteError( error ) (((error) >= ERR_INCOMPLETE_BYTE) && ((error) <= ERR_INCOMPLETE_BYTE_07)) /*!< Checks if given error is a Incomplete error */ + +#define rfalAdjACBR( b ) (((uint16_t)(b) >= (uint16_t)RFAL_BR_52p97) ? (uint16_t)(b) : ((uint16_t)(b)+1U)) /*!< Adjusts ST25R391x Bit rate to Analog Configuration */ +#define rfalConvBR2ACBR( b ) (((rfalAdjACBR((b)))<din; + streamConf.dout = isoStreamConfig->dout; + streamConf.report_period_length = isoStreamConfig->report_period_length; + streamConf.useBPSK = isoStreamConfig->useBPSK; + st25r3911StreamConfigure(&streamConf); + } + + /* Set Analog configurations for this bit rate */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_POLL_COMMON) ); + rfalSetAnalogConfig( (rfalAnalogConfigId)(RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCV | rfalConvBR2ACBR(gRFAL.txBR) | RFAL_ANALOG_CONFIG_TX ) ); + rfalSetAnalogConfig( (rfalAnalogConfigId)(RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCV | rfalConvBR2ACBR(gRFAL.rxBR) | RFAL_ANALOG_CONFIG_RX ) ); + break; + + #endif /* RFAL_FEATURE_NFCV */ + + + /*******************************************************************************/ + case RFAL_MODE_POLL_ACTIVE_P2P: + + /* Set Analog configurations for this bit rate */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_POLL_COMMON) ); + rfalSetAnalogConfig( (rfalAnalogConfigId)(RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | rfalConvBR2ACBR(gRFAL.txBR) | RFAL_ANALOG_CONFIG_TX ) ); + rfalSetAnalogConfig( (rfalAnalogConfigId)(RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_AP2P | rfalConvBR2ACBR(gRFAL.rxBR) | RFAL_ANALOG_CONFIG_RX ) ); + break; + + /*******************************************************************************/ + case RFAL_MODE_LISTEN_ACTIVE_P2P: + + /* Set Analog configurations for this bit rate */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_LISTEN_COMMON) ); + rfalSetAnalogConfig( (rfalAnalogConfigId)(RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | rfalConvBR2ACBR(gRFAL.txBR) | RFAL_ANALOG_CONFIG_TX ) ); + rfalSetAnalogConfig( (rfalAnalogConfigId)(RFAL_ANALOG_CONFIG_LISTEN | RFAL_ANALOG_CONFIG_TECH_AP2P | rfalConvBR2ACBR(gRFAL.rxBR) | RFAL_ANALOG_CONFIG_RX ) ); + break; + + /*******************************************************************************/ + case RFAL_MODE_LISTEN_NFCA: + case RFAL_MODE_LISTEN_NFCB: + case RFAL_MODE_LISTEN_NFCF: + case RFAL_MODE_NONE: + return ERR_WRONG_STATE; + + /*******************************************************************************/ + default: + return ERR_NOT_IMPLEMENTED; + } + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalGetBitRate( rfalBitRate *txBR, rfalBitRate *rxBR ) +{ + if( (gRFAL.state == RFAL_STATE_IDLE) || (gRFAL.mode == RFAL_MODE_NONE) ) + { + return ERR_WRONG_STATE; + } + + if( txBR != NULL ) + { + *txBR = gRFAL.txBR; + } + + if( rxBR != NULL ) + { + *rxBR = gRFAL.rxBR; + } + + return ERR_NONE; +} + + +/*******************************************************************************/ +void rfalSetErrorHandling( rfalEHandling eHandling ) +{ + gRFAL.conf.eHandling = eHandling; +} + + +/*******************************************************************************/ +rfalEHandling rfalGetErrorHandling( void ) +{ + return gRFAL.conf.eHandling; +} + + +/*******************************************************************************/ +void rfalSetFDTPoll( uint32_t FDTPoll ) +{ + gRFAL.timings.FDTPoll = MIN( FDTPoll, RFAL_ST25R3911_GPT_MAX_1FC ); +} + + +/*******************************************************************************/ +uint32_t rfalGetFDTPoll( void ) +{ + return gRFAL.timings.FDTPoll; +} + + +/*******************************************************************************/ +void rfalSetFDTListen( uint32_t FDTListen ) +{ + gRFAL.timings.FDTListen = MIN( FDTListen, RFAL_ST25R3911_MRT_MAX_1FC); +} + +/*******************************************************************************/ +uint32_t rfalGetFDTListen( void ) +{ + return gRFAL.timings.FDTListen; +} + +void rfalSetGT( uint32_t GT ) +{ + gRFAL.timings.GT = MIN( GT, RFAL_ST25R3911_GT_MAX_1FC ); +} + +/*******************************************************************************/ +uint32_t rfalGetGT( void ) +{ + return gRFAL.timings.GT; +} + +/*******************************************************************************/ +bool rfalIsGTExpired( void ) +{ + if( gRFAL.tmr.GT != RFAL_TIMING_NONE ) + { + if( !rfalTimerisExpired( gRFAL.tmr.GT ) ) + { + return false; + } + } + return true; +} + +/*******************************************************************************/ +ReturnCode rfalFieldOnAndStartGT( void ) +{ + ReturnCode ret; + + /* Check if RFAL has been initialized (Oscillator should be running) and also + * if a direct register access has been performed and left the Oscillator Off */ + if( !st25r3911IsOscOn() || (gRFAL.state < RFAL_STATE_INIT) ) + { + return ERR_WRONG_STATE; + } + + ret = ERR_NONE; + + /* Set Analog configurations for Field On event */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_FIELD_ON) ); + + /*******************************************************************************/ + /* Perform collision avoidance and turn field On if not already On */ + if( !st25r3911IsTxEnabled() || !gRFAL.field ) + { + /* Use Thresholds set by AnalogConfig */ + ret = st25r3911PerformCollisionAvoidance( ST25R3911_CMD_RESPONSE_RF_COLLISION_0, ST25R3911_THRESHOLD_DO_NOT_SET, ST25R3911_THRESHOLD_DO_NOT_SET, 0 ); + + gRFAL.field = st25r3911IsTxEnabled(); + + /* Only turn on Receiver and Transmitter if field was successfully turned On */ + if(gRFAL.field) + { + st25r3911TxRxOn(); /* Enable Tx and Rx (Tx is already On) */ + } + } + + /*******************************************************************************/ + /* Start GT timer in case the GT value is set */ + if( (gRFAL.timings.GT != RFAL_TIMING_NONE) ) + { + /* Ensure that a SW timer doesn't have a lower value then the minimum */ + rfalTimerStart( gRFAL.tmr.GT, rfalConv1fcToMs( MAX( (gRFAL.timings.GT), RFAL_ST25R3911_GT_MIN_1FC) ) ); + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalFieldOff( void ) +{ + /* Check whether a TxRx is not yet finished */ + if( gRFAL.TxRx.state != RFAL_TXRX_STATE_IDLE ) + { + rfalCleanupTransceive(); + } + + /* Disable Tx and Rx */ + st25r3911TxRxOff(); + + /* Set Analog configurations for Field Off event */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_FIELD_OFF) ); + gRFAL.field = false; + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalStartTransceive( const rfalTransceiveContext *ctx ) +{ + uint32_t FxTAdj; /* FWT or FDT adjustment calculation */ + + /* Check for valid parameters */ + if( ctx == NULL ) + { + return ERR_PARAM; + } + + /* Ensure that RFAL is already Initialized and the mode has been set */ + if( (gRFAL.state >= RFAL_STATE_MODE_SET) /*&& (gRFAL.TxRx.state == RFAL_TXRX_STATE_INIT )*/ ) + { + /*******************************************************************************/ + /* Check whether the field is already On, otherwise no TXE will be received */ + if( !st25r3911IsTxEnabled() && (!rfalIsModePassiveListen( gRFAL.mode ) && (ctx->txBuf != NULL)) ) + { + return ERR_WRONG_STATE; + } + + gRFAL.TxRx.ctx = *ctx; + + /*******************************************************************************/ + if( gRFAL.timings.FDTListen != RFAL_TIMING_NONE ) + { + /* Calculate MRT adjustment accordingly to the current mode */ + FxTAdj = RFAL_FDT_LISTEN_MRT_ADJUSTMENT; + if(gRFAL.mode == RFAL_MODE_POLL_NFCA) { FxTAdj += (uint32_t)RFAL_FDT_LISTEN_A_ADJUSTMENT; } + if(gRFAL.mode == RFAL_MODE_POLL_NFCA_T1T) { FxTAdj += (uint32_t)RFAL_FDT_LISTEN_A_ADJUSTMENT; } + if(gRFAL.mode == RFAL_MODE_POLL_NFCB) { FxTAdj += (uint32_t)RFAL_FDT_LISTEN_B_ADJUSTMENT; } + if(gRFAL.mode == RFAL_MODE_POLL_NFCV) { FxTAdj += (uint32_t)RFAL_FDT_LISTEN_V_ADJUSTMENT; } + + + /* Set Minimum FDT(Listen) in which PICC is not allowed to send a response */ + st25r3911WriteRegister( ST25R3911_REG_MASK_RX_TIMER, (uint8_t)rfalConv1fcTo64fc( (FxTAdj > gRFAL.timings.FDTListen) ? RFAL_ST25R3911_MRT_MIN_1FC : (gRFAL.timings.FDTListen - FxTAdj) ) ); + } + + /*******************************************************************************/ + /* FDT Poll will be loaded in rfalPrepareTransceive() once the previous was expired */ + + /*******************************************************************************/ + if( rfalIsModePassiveComm( gRFAL.mode ) ) /* Passive Comms */ + { + if( (gRFAL.TxRx.ctx.fwt != RFAL_FWT_NONE) && (gRFAL.TxRx.ctx.fwt != 0U) ) + { + /* Ensure proper timing configuration */ + if( gRFAL.timings.FDTListen >= gRFAL.TxRx.ctx.fwt ) + { + return ERR_PARAM; + } + + FxTAdj = RFAL_FWT_ADJUSTMENT; + if(gRFAL.mode == RFAL_MODE_POLL_NFCA) { FxTAdj += (uint32_t)RFAL_FWT_A_ADJUSTMENT; } + if(gRFAL.mode == RFAL_MODE_POLL_NFCA_T1T) { FxTAdj += (uint32_t)RFAL_FWT_A_ADJUSTMENT; } + if(gRFAL.mode == RFAL_MODE_POLL_NFCB) { FxTAdj += (uint32_t)RFAL_FWT_B_ADJUSTMENT; } + if(gRFAL.mode == RFAL_MODE_POLL_NFCF) + { + FxTAdj += (uint32_t)((gRFAL.txBR == RFAL_BR_212) ? RFAL_FWT_F_212_ADJUSTMENT : RFAL_FWT_F_424_ADJUSTMENT ); + } + + /* Ensure that the given FWT doesn't exceed NRT maximum */ + gRFAL.TxRx.ctx.fwt = MIN( (gRFAL.TxRx.ctx.fwt + FxTAdj), RFAL_ST25R3911_NRT_MAX_1FC ); + + /* Set FWT in the NRT */ + st25r3911SetNoResponseTime_64fcs( rfalConv1fcTo64fc( gRFAL.TxRx.ctx.fwt ) ); + } + else + { + /* Disable NRT, no NRE will be triggered, therefore wait endlessly for Rx */ + st25r3911SetNoResponseTime_64fcs( RFAL_ST25R3911_NRT_DISABLED ); + } + } + else /* Active Comms */ + { + /* Setup NRT timer for rf response RF collision timeout. */ + st25r3911SetNoResponseTime_64fcs( rfalConv1fcTo64fc(RFAL_AP2P_FIELDON_TADTTRFW) ); + + /* In Active Mode No Response Timer cannot be used to measure FWT a SW timer is used instead */ + } + + gRFAL.state = RFAL_STATE_TXRX; + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_IDLE; + gRFAL.TxRx.status = ERR_BUSY; + gRFAL.TxRx.rxse = false; + + #if RFAL_FEATURE_NFCV + /*******************************************************************************/ + if( (RFAL_MODE_POLL_NFCV == gRFAL.mode) || (RFAL_MODE_POLL_PICOPASS == gRFAL.mode) ) + { /* Exchange receive buffer with internal buffer */ + gRFAL.nfcvData.origCtx = gRFAL.TxRx.ctx; + + gRFAL.TxRx.ctx.rxBuf = ((gRFAL.nfcvData.origCtx.rxBuf != NULL) ? gRFAL.nfcvData.codingBuffer : NULL); + gRFAL.TxRx.ctx.rxBufLen = (uint16_t)rfalConvBytesToBits(sizeof(gRFAL.nfcvData.codingBuffer)); + gRFAL.TxRx.ctx.flags = (uint32_t)RFAL_TXRX_FLAGS_CRC_TX_MANUAL + | (uint32_t)RFAL_TXRX_FLAGS_CRC_RX_KEEP + | (uint32_t)RFAL_TXRX_FLAGS_NFCIP1_OFF + | (uint32_t)(gRFAL.nfcvData.origCtx.flags & (uint32_t)RFAL_TXRX_FLAGS_AGC_OFF) + | (uint32_t)RFAL_TXRX_FLAGS_PAR_RX_KEEP + | (uint32_t)RFAL_TXRX_FLAGS_PAR_TX_NONE; + + /* In NFCV a TxRx with a valid txBuf and txBufSize==0 indicates to send an EOF */ + /* Skip logic below that would go directly into receive */ + if ( gRFAL.TxRx.ctx.txBuf != NULL ) + { + return ERR_NONE; + } + } + #endif /* RFAL_FEATURE_NFCV */ + + + /*******************************************************************************/ + /* Check if the Transceive start performing Tx or goes directly to Rx */ + if( (gRFAL.TxRx.ctx.txBuf == NULL) || (gRFAL.TxRx.ctx.txBufLen == 0U) ) + { + /* Clear FIFO, Clear and Enable the Interrupts */ + rfalPrepareTransceive( ); + + /* Disable our field upon a Rx reEnable on AP2P */ + if( rfalIsModeActiveComm(gRFAL.mode) ) + { + st25r3911TxOff(); + } + + /* No Tx done, enable the Receiver */ + st25r3911ExecuteCommand( ST25R3911_CMD_UNMASK_RECEIVE_DATA ); + + /* Start NRT manually, if FWT = 0 (wait endlessly for Rx) chip will ignore anyhow */ + st25r3911ExecuteCommand( ST25R3911_CMD_START_NO_RESPONSE_TIMER ); + + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_IDLE; + } + + return ERR_NONE; + } + + return ERR_WRONG_STATE; +} + + +/*******************************************************************************/ +bool rfalIsTransceiveInTx( void ) +{ + return ( (gRFAL.TxRx.state >= RFAL_TXRX_STATE_TX_IDLE) && (gRFAL.TxRx.state < RFAL_TXRX_STATE_RX_IDLE) ); +} + + +/*******************************************************************************/ +bool rfalIsTransceiveInRx( void ) +{ + return (gRFAL.TxRx.state >= RFAL_TXRX_STATE_RX_IDLE); +} + + +/*******************************************************************************/ +ReturnCode rfalTransceiveBlockingTx( uint8_t* txBuf, uint16_t txBufLen, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t* actLen, uint32_t flags, uint32_t fwt ) +{ + ReturnCode ret; + rfalTransceiveContext ctx; + + rfalCreateByteFlagsTxRxContext( ctx, txBuf, txBufLen, rxBuf, rxBufLen, actLen, flags, fwt ); + EXIT_ON_ERR( ret, rfalStartTransceive( &ctx ) ); + + return rfalTransceiveRunBlockingTx(); +} + + +/*******************************************************************************/ +static ReturnCode rfalTransceiveRunBlockingTx( void ) +{ + ReturnCode ret; + + do{ + rfalWorker(); + ret = rfalGetTransceiveStatus(); + } + while( rfalIsTransceiveInTx() && (ret == ERR_BUSY) ); + + if( rfalIsTransceiveInRx() ) + { + return ERR_NONE; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalTransceiveBlockingRx( void ) +{ + ReturnCode ret; + + do{ + rfalWorker(); + ret = rfalGetTransceiveStatus(); + } + while( rfalIsTransceiveInRx() && (ret == ERR_BUSY) ); + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalTransceiveBlockingTxRx( uint8_t* txBuf, uint16_t txBufLen, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t* actLen, uint32_t flags, uint32_t fwt ) +{ + ReturnCode ret; + + EXIT_ON_ERR( ret, rfalTransceiveBlockingTx( txBuf, txBufLen, rxBuf, rxBufLen, actLen, flags, fwt ) ); + ret = rfalTransceiveBlockingRx(); + + /* Convert received bits to bytes */ + if( actLen != NULL ) + { + *actLen = rfalConvBitsToBytes(*actLen); + } + + return ret; +} + + +/*******************************************************************************/ +static ReturnCode rfalRunTransceiveWorker( void ) +{ + if( gRFAL.state == RFAL_STATE_TXRX ) + { + /* Run Tx or Rx state machines */ + if( rfalIsTransceiveInTx() ) + { + rfalTransceiveTx(); + return rfalGetTransceiveStatus(); + } + + if( rfalIsTransceiveInRx() ) + { + rfalTransceiveRx(); + return rfalGetTransceiveStatus(); + } + } + return ERR_WRONG_STATE; +} + +/*******************************************************************************/ +rfalTransceiveState rfalGetTransceiveState( void ) +{ + return gRFAL.TxRx.state; +} + +ReturnCode rfalGetTransceiveStatus( void ) +{ + return ((gRFAL.TxRx.state == RFAL_TXRX_STATE_IDLE) ? gRFAL.TxRx.status : ERR_BUSY); +} + + +/*******************************************************************************/ +ReturnCode rfalGetTransceiveRSSI( uint16_t *rssi ) +{ + uint16_t amRSSI; + uint16_t pmRSSI; + + if( rssi == NULL ) + { + return ERR_PARAM; + } + + /* Check if Manual channel is enabled */ + if( st25r3911CheckReg( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_rx_man, ST25R3911_REG_OP_CONTROL_rx_man ) ) + { + st25r3911GetRSSI( &amRSSI, &pmRSSI ); + + /* Check which channel is selected */ + *rssi = ( st25r3911CheckReg( ST25R3911_REG_RX_CONF1, ST25R3911_REG_RX_CONF1_ch_sel, ST25R3911_REG_RX_CONF1_ch_sel ) ? pmRSSI : amRSSI ); + return ERR_NONE; + } + + *rssi = 0; + return ERR_NOTSUPP; +} + + +/*******************************************************************************/ +void rfalWorker( void ) +{ + platformProtectWorker(); /* Protect RFAL Worker/Task/Process */ + + switch( gRFAL.state ) + { + case RFAL_STATE_TXRX: + rfalRunTransceiveWorker(); + break; + + #if RFAL_FEATURE_LISTEN_MODE + case RFAL_STATE_LM: + rfalRunListenModeWorker(); + break; + #endif /* RFAL_FEATURE_LISTEN_MODE */ + + #if RFAL_FEATURE_WAKEUP_MODE + case RFAL_STATE_WUM: + rfalRunWakeUpModeWorker(); + break; + #endif /* RFAL_FEATURE_WAKEUP_MODE */ + + /* Nothing to be done */ + default: + /* MISRA 16.4: no empty default statement (a comment being enough) */ + break; + } + + platformUnprotectWorker(); /* Unprotect RFAL Worker/Task/Process */ +} + + +/*******************************************************************************/ +static void rfalErrorHandling( void ) +{ + bool rxHasIncParError; + uint8_t fifoBytesToRead; + uint8_t reEnRx[] = { ST25R3911_CMD_CLEAR_FIFO, ST25R3911_CMD_UNMASK_RECEIVE_DATA }; + + + fifoBytesToRead = rfalFIFOStatusGetNumBytes(); + + + /*******************************************************************************/ + /* EMVCo */ + /*******************************************************************************/ + if( gRFAL.conf.eHandling == RFAL_ERRORHANDLING_EMVCO ) + { + /*******************************************************************************/ + /* EMD Handling - NFC Forum Digital 1.1 4.1.1.1 ; EMVCo 2.6 4.9.2 */ + /* ReEnable the receiver on frames with a length < 4 bytes, upon: */ + /* - Collision or Framing error detected */ + /* - Residual bits are detected (hard framing error) */ + /* - Parity error */ + /* - CRC error */ + /*******************************************************************************/ + + /* Check if reception has incompete bytes or parity error */ + rxHasIncParError = ( rfalFIFOStatusIsIncompleteByte() ? true : rfalFIFOStatusIsMissingPar() ); /* MISRA 13.5 */ + + /* In case there are residual bits decrement FIFO bytes */ + if( (fifoBytesToRead > 0U) && rxHasIncParError) + { + fifoBytesToRead--; + } + + if( ( (gRFAL.fifo.bytesTotal + fifoBytesToRead) < RFAL_EMVCO_RX_MAXLEN ) && + ( (gRFAL.TxRx.status == ERR_RF_COLLISION) || (gRFAL.TxRx.status == ERR_FRAMING) || + (gRFAL.TxRx.status == ERR_PAR) || (gRFAL.TxRx.status == ERR_CRC) || + rxHasIncParError ) ) + { + /* Ignore this reception, ReEnable receiver */ + st25r3911ExecuteCommands( reEnRx, sizeof(reEnRx) ); + + rfalFIFOStatusClear(); + gRFAL.fifo.bytesTotal = 0; + gRFAL.TxRx.status = ERR_BUSY; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_RXS; + } + return; + } + + /*******************************************************************************/ + /* ISO14443A Mode */ + /*******************************************************************************/ + if( gRFAL.mode == RFAL_MODE_POLL_NFCA ) + { + + /*******************************************************************************/ + /* If we received one incomplete byte (not a block and a incomplete byte at * + * the end) we will raise a specific error ( support for T2T 4 bit ACK / NAK ) * + * Otherwise just leave it as an CRC/FRAMING/PAR error */ + /*******************************************************************************/ + if( (gRFAL.TxRx.status == ERR_PAR) || (gRFAL.TxRx.status == ERR_CRC) ) + { + if( rfalFIFOStatusIsIncompleteByte() && (fifoBytesToRead == RFAL_NFC_RX_INCOMPLETE_LEN) ) + { + st25r3911ReadFifo( (uint8_t*)(gRFAL.TxRx.ctx.rxBuf), fifoBytesToRead ); + if( (gRFAL.TxRx.ctx.rxRcvdLen) != NULL ) + { + *gRFAL.TxRx.ctx.rxRcvdLen = rfalFIFOGetNumIncompleteBits(); + } + + gRFAL.TxRx.status = ERR_INCOMPLETE_BYTE; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + } + } + } + +} + + +/*******************************************************************************/ +static void rfalCleanupTransceive( void ) +{ + /*******************************************************************************/ + /* Transceive flags */ + /*******************************************************************************/ + + /* Restore default settings on NFCIP1 mode, Receiving parity + CRC bits and manual Tx Parity*/ + st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, (ST25R3911_REG_ISO14443A_NFC_no_tx_par | ST25R3911_REG_ISO14443A_NFC_no_rx_par | ST25R3911_REG_ISO14443A_NFC_nfc_f0) ); + + /* Restore AGC enabled */ + st25r3911SetRegisterBits( ST25R3911_REG_RX_CONF2, ST25R3911_REG_RX_CONF2_agc_en ); + + /*******************************************************************************/ + + + + /*******************************************************************************/ + /* Execute Post Transceive Callback */ + /*******************************************************************************/ + if( gRFAL.callbacks.postTxRx != NULL ) + { + gRFAL.callbacks.postTxRx(); + } + /*******************************************************************************/ + +} + + +/*******************************************************************************/ +static void rfalPrepareTransceive( void ) +{ + uint32_t maskInterrupts; + uint8_t reg; + + /*******************************************************************************/ + /* In the EMVCo mode the NRT will continue to run. * + * For the clear to stop it, the EMV mode has to be disabled before */ + st25r3911ClrRegisterBits( ST25R3911_REG_GPT_CONTROL, ST25R3911_REG_GPT_CONTROL_nrt_emv ); + + /* Reset receive logic */ + st25r3911ExecuteCommand( ST25R3911_CMD_CLEAR_FIFO ); + + /* Reset Rx Gain */ + st25r3911ExecuteCommand( ST25R3911_CMD_CLEAR_SQUELCH ); + + + /*******************************************************************************/ + /* FDT Poll */ + /*******************************************************************************/ + if( rfalIsModePassiveComm( gRFAL.mode ) ) /* Passive Comms */ + { + /* In Passive communications General Purpose Timer is used to measure FDT Poll */ + if( gRFAL.timings.FDTPoll != RFAL_TIMING_NONE ) + { + /* Configure GPT to start at RX end */ + st25r3911StartGPTimer_8fcs( (uint16_t)rfalConv1fcTo8fc( MIN( gRFAL.timings.FDTPoll, (gRFAL.timings.FDTPoll - RFAL_FDT_POLL_ADJUSTMENT) ) ), ST25R3911_REG_GPT_CONTROL_gptc_erx ); + } + } + + + /*******************************************************************************/ + /* Execute Pre Transceive Callback */ + /*******************************************************************************/ + if( gRFAL.callbacks.preTxRx != NULL ) + { + gRFAL.callbacks.preTxRx(); + } + /*******************************************************************************/ + + maskInterrupts = ( ST25R3911_IRQ_MASK_FWL | ST25R3911_IRQ_MASK_TXE | + ST25R3911_IRQ_MASK_RXS | ST25R3911_IRQ_MASK_RXE | + ST25R3911_IRQ_MASK_FWL | ST25R3911_IRQ_MASK_NRE | + ST25R3911_IRQ_MASK_PAR | ST25R3911_IRQ_MASK_CRC | + ST25R3911_IRQ_MASK_ERR1 | ST25R3911_IRQ_MASK_ERR2 ); + + + /*******************************************************************************/ + /* Transceive flags */ + /*******************************************************************************/ + + reg = (ST25R3911_REG_ISO14443A_NFC_no_tx_par_off | ST25R3911_REG_ISO14443A_NFC_no_rx_par_off | ST25R3911_REG_ISO14443A_NFC_nfc_f0_off); + + /* Check if NFCIP1 mode is to be enabled */ + if( (gRFAL.TxRx.ctx.flags & (uint8_t)RFAL_TXRX_FLAGS_NFCIP1_ON) != 0U ) + { + reg |= ST25R3911_REG_ISO14443A_NFC_nfc_f0; + } + + /* Check if Parity check is to be skipped and to keep the parity + CRC bits in FIFO */ + if( (gRFAL.TxRx.ctx.flags & (uint8_t)RFAL_TXRX_FLAGS_PAR_RX_KEEP) != 0U ) + { + reg |= ST25R3911_REG_ISO14443A_NFC_no_rx_par; + } + + /* Check if automatic Parity bits is to be disabled */ + if( (gRFAL.TxRx.ctx.flags & (uint8_t)RFAL_TXRX_FLAGS_PAR_TX_NONE) != 0U ) + { + reg |= ST25R3911_REG_ISO14443A_NFC_no_tx_par; + } + + /* Apply current TxRx flags on ISO14443A and NFC 106kb/s Settings Register */ + st25r3911ChangeRegisterBits( ST25R3911_REG_ISO14443A_NFC, (ST25R3911_REG_ISO14443A_NFC_no_tx_par | ST25R3911_REG_ISO14443A_NFC_no_rx_par | ST25R3911_REG_ISO14443A_NFC_nfc_f0), reg ); + + + /* Check if AGC is to be disabled */ + if( (gRFAL.TxRx.ctx.flags & (uint8_t)RFAL_TXRX_FLAGS_AGC_OFF) != 0U ) + { + st25r3911ClrRegisterBits( ST25R3911_REG_RX_CONF2, ST25R3911_REG_RX_CONF2_agc_en ); + } + else + { + st25r3911SetRegisterBits( ST25R3911_REG_RX_CONF2, ST25R3911_REG_RX_CONF2_agc_en ); + } + /*******************************************************************************/ + + + + /*******************************************************************************/ + /* EMVCo NRT mode */ + /*******************************************************************************/ + if( gRFAL.conf.eHandling == RFAL_ERRORHANDLING_EMVCO ) + { + st25r3911SetRegisterBits( ST25R3911_REG_GPT_CONTROL, ST25R3911_REG_GPT_CONTROL_nrt_emv ); + } + else + { + st25r3911ClrRegisterBits( ST25R3911_REG_GPT_CONTROL, ST25R3911_REG_GPT_CONTROL_nrt_emv ); + } + /*******************************************************************************/ + + + + /* In Active comms enable also External Field interrupts */ + if( rfalIsModeActiveComm( gRFAL.mode ) ) + { + maskInterrupts |= ( ST25R3911_IRQ_MASK_EOF | ST25R3911_IRQ_MASK_EON | ST25R3911_IRQ_MASK_CAT | ST25R3911_IRQ_MASK_CAC ); + } + + + /*******************************************************************************/ + /* clear and enable these interrupts */ + st25r3911GetInterrupt( maskInterrupts ); + st25r3911EnableInterrupts( maskInterrupts ); + + /* Clear FIFO status local copy */ + rfalFIFOStatusClear(); +} + +/*******************************************************************************/ +static void rfalTransceiveTx( void ) +{ + volatile uint32_t irqs; + uint16_t tmp; + ReturnCode ret; + + /* Supress warning in case NFC-V feature is disabled */ + ret = ERR_NONE; + NO_WARNING(ret); + + + irqs = ST25R3911_IRQ_MASK_NONE; + + if( gRFAL.TxRx.state != gRFAL.TxRx.lastState ) + { + /* rfalLogD( "RFAL: lastSt: %d curSt: %d \r\n", gRFAL.TxRx.lastState, gRFAL.TxRx.state ); */ + gRFAL.TxRx.lastState = gRFAL.TxRx.state; + } + + switch( gRFAL.TxRx.state ) + { + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_IDLE: + + /* Nothing to do */ + + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_WAIT_GT ; + /* fall through */ + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_WAIT_GT: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + if( !rfalIsGTExpired() ) + { + break; + } + + gRFAL.tmr.GT = RFAL_TIMING_NONE; + + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_WAIT_FDT; + /* fall through */ + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_WAIT_FDT: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + /* Only in Passive communications GPT is used to measure FDT Poll */ + if( rfalIsModePassiveComm( gRFAL.mode ) ) + { + if( st25r3911IsGPTRunning() ) + { + break; + } + } + + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_TRANSMIT; + /* fall through */ + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_TRANSMIT: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + /* Clear FIFO, Clear and Enable the Interrupts */ + rfalPrepareTransceive( ); + + /* Calculate when Water Level Interrupt will be triggered */ + gRFAL.fifo.expWL = (uint16_t)( st25r3911CheckReg( ST25R3911_REG_IO_CONF1, ST25R3911_REG_IO_CONF1_fifo_lt, ST25R3911_REG_IO_CONF1_fifo_lt_16bytes) ? RFAL_FIFO_OUT_LT_16 : RFAL_FIFO_OUT_LT_32 ); + + #if RFAL_FEATURE_NFCV + /*******************************************************************************/ + /* In NFC-V streaming mode, the FIFO needs to be loaded with the coded bits */ + if( (RFAL_MODE_POLL_NFCV == gRFAL.mode) || (RFAL_MODE_POLL_PICOPASS == gRFAL.mode) ) + { + #if 0 + /* Debugging code: output the payload bits by writing into the FIFO and subsequent clearing */ + st25r3911WriteFifo(gRFAL.TxRx.ctx.txBuf, rfalConvBitsToBytes(gRFAL.TxRx.ctx.txBufLen)); + st25r3911ExecuteCommand( ST25R3911_CMD_CLEAR_FIFO ); + #endif + /* Calculate the bytes needed to be Written into FIFO (a incomplete byte will be added as 1byte) */ + gRFAL.nfcvData.nfcvOffset = 0; + ret = iso15693VCDCode(gRFAL.TxRx.ctx.txBuf, rfalConvBitsToBytes(gRFAL.TxRx.ctx.txBufLen), (((gRFAL.nfcvData.origCtx.flags & (uint32_t)RFAL_TXRX_FLAGS_CRC_TX_MANUAL) != 0U)?false:true),(((gRFAL.nfcvData.origCtx.flags & (uint32_t)RFAL_TXRX_FLAGS_NFCV_FLAG_MANUAL) != 0U)?false:true), (RFAL_MODE_POLL_PICOPASS == gRFAL.mode), + &gRFAL.fifo.bytesTotal, &gRFAL.nfcvData.nfcvOffset, gRFAL.nfcvData.codingBuffer, MIN( (uint16_t)ST25R3911_FIFO_DEPTH, (uint16_t)sizeof(gRFAL.nfcvData.codingBuffer) ), &gRFAL.fifo.bytesWritten); + + if( (ret != ERR_NONE) && (ret != ERR_AGAIN) ) + { + gRFAL.TxRx.status = ret; + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL; + break; + } + /* Set the number of full bytes and bits to be transmitted */ + st25r3911SetNumTxBits( rfalConvBytesToBits(gRFAL.fifo.bytesTotal) ); + + /* Load FIFO with coded bytes */ + /* TODO: check bytesWritten does not exceed 255 */ + st25r3911WriteFifo( gRFAL.nfcvData.codingBuffer, (uint8_t)gRFAL.fifo.bytesWritten ); + + } + /*******************************************************************************/ + else + #endif /* RFAL_FEATURE_NFCV */ + { + /* Calculate the bytes needed to be Written into FIFO (a incomplete byte will be added as 1byte) */ + gRFAL.fifo.bytesTotal = (uint16_t)rfalCalcNumBytes(gRFAL.TxRx.ctx.txBufLen); + + /* Set the number of full bytes and bits to be transmitted */ + st25r3911SetNumTxBits( gRFAL.TxRx.ctx.txBufLen ); + + /* Load FIFO with total length or FIFO's maximum */ + gRFAL.fifo.bytesWritten = MIN( gRFAL.fifo.bytesTotal, ST25R3911_FIFO_DEPTH ); + st25r3911WriteFifo( gRFAL.TxRx.ctx.txBuf, (uint8_t)gRFAL.fifo.bytesWritten ); + } + + /*Check if Observation Mode is enabled and set it on ST25R391x */ + rfalCheckEnableObsModeTx(); + + /*******************************************************************************/ + /* Trigger/Start transmission */ + if( (gRFAL.TxRx.ctx.flags & (uint32_t)RFAL_TXRX_FLAGS_CRC_TX_MANUAL) != 0U ) + { + st25r3911ExecuteCommand( ST25R3911_CMD_TRANSMIT_WITHOUT_CRC ); + } + else + { + st25r3911ExecuteCommand( ST25R3911_CMD_TRANSMIT_WITH_CRC ); + } + + /* Check if a WL level is expected or TXE should come */ + gRFAL.TxRx.state = (( gRFAL.fifo.bytesWritten < gRFAL.fifo.bytesTotal ) ? RFAL_TXRX_STATE_TX_WAIT_WL : RFAL_TXRX_STATE_TX_WAIT_TXE); + break; + + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_WAIT_WL: + + irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_FWL | ST25R3911_IRQ_MASK_TXE) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + break; /* No interrupt to process */ + } + + if( ((irqs & ST25R3911_IRQ_MASK_FWL) != 0U) && ((irqs & ST25R3911_IRQ_MASK_TXE) == 0U) ) + { + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_RELOAD_FIFO; + } + else + { + gRFAL.TxRx.status = ERR_IO; + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL; + break; + } + + /* fall through */ + + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_RELOAD_FIFO: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + #if RFAL_FEATURE_NFCV + /*******************************************************************************/ + /* In NFC-V streaming mode, the FIFO needs to be loaded with the coded bits */ + if( (RFAL_MODE_POLL_NFCV == gRFAL.mode) || (RFAL_MODE_POLL_PICOPASS == gRFAL.mode) ) + { + uint16_t maxLen; + + /* Load FIFO with the remaining length or maximum available (which fit on the coding buffer) */ + maxLen = (uint16_t)MIN( (gRFAL.fifo.bytesTotal - gRFAL.fifo.bytesWritten), gRFAL.fifo.expWL); + maxLen = (uint16_t)MIN( maxLen, sizeof(gRFAL.nfcvData.codingBuffer) ); + tmp = 0; + + /* Calculate the bytes needed to be Written into FIFO (a incomplete byte will be added as 1byte) */ + ret = iso15693VCDCode(gRFAL.TxRx.ctx.txBuf, rfalConvBitsToBytes(gRFAL.TxRx.ctx.txBufLen), (((gRFAL.nfcvData.origCtx.flags & (uint32_t)RFAL_TXRX_FLAGS_CRC_TX_MANUAL) != 0U)?false:true), (((gRFAL.nfcvData.origCtx.flags & (uint32_t)RFAL_TXRX_FLAGS_NFCV_FLAG_MANUAL) != 0U)?false:true), (RFAL_MODE_POLL_PICOPASS == gRFAL.mode), + &gRFAL.fifo.bytesTotal, &gRFAL.nfcvData.nfcvOffset, gRFAL.nfcvData.codingBuffer, maxLen, &tmp); + + if( (ret != ERR_NONE) && (ret != ERR_AGAIN) ) + { + gRFAL.TxRx.status = ret; + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL; + break; + } + + /* Load FIFO with coded bytes */ + /* TODO: check tmp does not exceed 255 */ + st25r3911WriteFifo( gRFAL.nfcvData.codingBuffer, (uint8_t)tmp ); + } + /*******************************************************************************/ + else + #endif /* RFAL_FEATURE_NFCV */ + { + /* Load FIFO with the remaining length or maximum available */ + tmp = MIN( (gRFAL.fifo.bytesTotal - gRFAL.fifo.bytesWritten), gRFAL.fifo.expWL); /* tmp holds the number of bytes written on this iteration */ + /* TODO: check tmp does not exceed 255 */ + st25r3911WriteFifo( &gRFAL.TxRx.ctx.txBuf[gRFAL.fifo.bytesWritten], (uint8_t)tmp ); + } + + /* Update total written bytes to FIFO */ + gRFAL.fifo.bytesWritten += tmp; + + /* Check if a WL level is expected or TXE should come */ + gRFAL.TxRx.state = (( gRFAL.fifo.bytesWritten < gRFAL.fifo.bytesTotal ) ? RFAL_TXRX_STATE_TX_WAIT_WL : RFAL_TXRX_STATE_TX_WAIT_TXE); + break; + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_WAIT_TXE: + + irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_FWL | ST25R3911_IRQ_MASK_TXE) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + break; /* No interrupt to process */ + } + + + if( (irqs & ST25R3911_IRQ_MASK_TXE) != 0U ) + { + /* In Active comm start SW timer to measure FWT */ + if( rfalIsModeActiveComm( gRFAL.mode) && (gRFAL.TxRx.ctx.fwt != RFAL_FWT_NONE) && (gRFAL.TxRx.ctx.fwt != 0U) ) + { + rfalTimerStart( gRFAL.tmr.FWT, rfalConv1fcToMs( gRFAL.TxRx.ctx.fwt ) ); + } + + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_DONE; + } + else if( (irqs & ST25R3911_IRQ_MASK_FWL) != 0U ) + { + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911 Errata #TBD */ + /* ST25R3911 may send a WL even when all bytes have been written to FIFO */ + /*******************************************************************************/ + break; /* Ignore ST25R3911 FIFO WL if total TxLen is already on the FIFO */ + } + else + { + gRFAL.TxRx.status = ERR_IO; + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL; + break; + } + + /* fall through */ + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_DONE: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + /* If no rxBuf is provided do not wait/expect Rx */ + if( gRFAL.TxRx.ctx.rxBuf == NULL ) + { + /*Check if Observation Mode was enabled and disable it on ST25R391x */ + rfalCheckDisableObsMode(); + + /* Clean up Transceive */ + rfalCleanupTransceive(); + + gRFAL.TxRx.status = ERR_NONE; + gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE; + break; + } + + rfalCheckEnableObsModeRx(); + + /* Goto Rx */ + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_IDLE; + break; + + /*******************************************************************************/ + case RFAL_TXRX_STATE_TX_FAIL: + + /* Error should be assigned by previous state */ + if( gRFAL.TxRx.status == ERR_BUSY ) + { + gRFAL.TxRx.status = ERR_SYSTEM; + } + + /*Check if Observation Mode was enabled and disable it on ST25R391x */ + rfalCheckDisableObsMode(); + + /* Clean up Transceive */ + rfalCleanupTransceive(); + + gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE; + break; + + /*******************************************************************************/ + default: + gRFAL.TxRx.status = ERR_SYSTEM; + gRFAL.TxRx.state = RFAL_TXRX_STATE_TX_FAIL; + break; + } +} + + +/*******************************************************************************/ +static void rfalTransceiveRx( void ) +{ + volatile uint32_t irqs; + uint8_t tmp; + uint8_t aux; + + irqs = ST25R3911_IRQ_MASK_NONE; + + if( gRFAL.TxRx.state != gRFAL.TxRx.lastState ) + { + /* rfalLogD( "RFAL: lastSt: %d curSt: %d \r\n", gRFAL.TxRx.lastState, gRFAL.TxRx.state ); */ + gRFAL.TxRx.lastState = gRFAL.TxRx.state; + } + + switch( gRFAL.TxRx.state ) + { + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_IDLE: + + /* Clear rx counters */ + gRFAL.fifo.bytesWritten = 0; // Total bytes written on RxBuffer + gRFAL.fifo.bytesTotal = 0; // Total bytes in FIFO will now be from Rx + if( gRFAL.TxRx.ctx.rxRcvdLen != NULL ) + { + *gRFAL.TxRx.ctx.rxRcvdLen = 0; + } + + gRFAL.TxRx.state = ( rfalIsModeActiveComm( gRFAL.mode ) ? RFAL_TXRX_STATE_RX_WAIT_EON : RFAL_TXRX_STATE_RX_WAIT_RXS ); + break; + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_WAIT_RXS: + + /*******************************************************************************/ + /* If in Active comm, Check if FWT SW timer has expired */ + if( rfalIsModeActiveComm( gRFAL.mode ) && (gRFAL.TxRx.ctx.fwt != RFAL_FWT_NONE) && (gRFAL.TxRx.ctx.fwt != 0U) ) + { + if( rfalTimerisExpired( gRFAL.tmr.FWT ) ) + { + gRFAL.TxRx.status = ERR_TIMEOUT; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + break; + } + } + + /*******************************************************************************/ + irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_RXS | ST25R3911_IRQ_MASK_NRE | ST25R3911_IRQ_MASK_EOF | ST25R3911_IRQ_MASK_RXE) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + break; /* No interrupt to process */ + } + + + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911 Errata #1.7 */ + /* NRE interrupt may be triggered twice */ + /* Ignore NRE if is detected together with no Rx Start */ + /*******************************************************************************/ + + /* Only raise Timeout if NRE is detected with no Rx Start (NRT EMV mode) */ + if( ((irqs & ST25R3911_IRQ_MASK_NRE) != 0U) && ((irqs & ST25R3911_IRQ_MASK_RXS) == 0U) ) + { + gRFAL.TxRx.status = ERR_TIMEOUT; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + break; + } + + /* Only raise Link Loss if EOF is detected with no Rx Start */ + if( ((irqs & ST25R3911_IRQ_MASK_EOF) != 0U) && ((irqs & ST25R3911_IRQ_MASK_RXS) == 0U) ) + { + /* In AP2P a Field On has already occurred - treat this as timeout | mute */ + gRFAL.TxRx.status = ( rfalIsModeActiveComm( gRFAL.mode ) ? ERR_TIMEOUT : ERR_LINK_LOSS ); + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + break; + } + + if( (irqs & ST25R3911_IRQ_MASK_RXS) != 0U ) + { + /* If we got RXS + RXE together, jump directly into RFAL_TXRX_STATE_RX_ERR_CHECK */ + if( (irqs & ST25R3911_IRQ_MASK_RXE) != 0U ) + { + gRFAL.TxRx.rxse = true; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_ERR_CHECK; + break; + } + else + { + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911 Errata #1.1 */ + /* Rarely on corrupted frames I_rxs gets signaled but I_rxe is not signaled */ + /* Use a SW timer to handle an eventual missing RXE */ + rfalTimerStart( gRFAL.tmr.RXE, RFAL_NORXE_TOUT ); + /*******************************************************************************/ + + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_RXE; + } + } + else if( (irqs & ST25R3911_IRQ_MASK_RXE) != 0U ) + { + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911 Errata #1.9 */ + /* ST25R3911 may indicate RXE without RXS previously, this happens upon some */ + /* noise or incomplete byte frames with less than 4 bits */ + /*******************************************************************************/ + + gRFAL.TxRx.status = ERR_IO; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + + rfalErrorHandling(); + break; + } + else + { + gRFAL.TxRx.status = ERR_IO; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + break; + } + + /* fall through */ + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_WAIT_RXE: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_RXE | ST25R3911_IRQ_MASK_FWL | ST25R3911_IRQ_MASK_EOF) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911B Errata #1.1 */ + /* ST25R3911 may indicate RXS without RXE afterwards, this happens rarely on */ + /* corrupted frames. */ + /* SW timer is used to timeout upon a missing RXE */ + if( rfalTimerisExpired( gRFAL.tmr.RXE ) ) + { + gRFAL.TxRx.status = ERR_FRAMING; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + } + /*******************************************************************************/ + + break; /* No interrupt to process */ + } + + if( ((irqs & ST25R3911_IRQ_MASK_FWL) != 0U) && ((irqs & ST25R3911_IRQ_MASK_RXE) == 0U) ) + { + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_FIFO; + break; + } + + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_ERR_CHECK; + /* fall through */ + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_ERR_CHECK: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + /* Retrieve and check for any error irqs */ + irqs |= st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_CRC | ST25R3911_IRQ_MASK_PAR | ST25R3911_IRQ_MASK_ERR1 | ST25R3911_IRQ_MASK_ERR2 | ST25R3911_IRQ_MASK_COL) ); + + if( (irqs & ST25R3911_IRQ_MASK_ERR1) != 0U ) + { + gRFAL.TxRx.status = ERR_FRAMING; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA; + + /* Check if there's a specific error handling for this */ + rfalErrorHandling(); + break; + } + /* Discard Soft Framing errors if not in EMVCo error handling */ + else if( ((irqs & ST25R3911_IRQ_MASK_ERR2) != 0U) && (gRFAL.conf.eHandling == RFAL_ERRORHANDLING_EMVCO) ) + { + gRFAL.TxRx.status = ERR_FRAMING; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA; + + /* Check if there's a specific error handling for this */ + rfalErrorHandling(); + break; + } + else if( (irqs & ST25R3911_IRQ_MASK_PAR) != 0U ) + { + gRFAL.TxRx.status = ERR_PAR; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA; + + /* Check if there's a specific error handling for this */ + rfalErrorHandling(); + break; + } + else if( (irqs & ST25R3911_IRQ_MASK_CRC) != 0U ) + { + gRFAL.TxRx.status = ERR_CRC; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA; + + /* Check if there's a specific error handling for this */ + rfalErrorHandling(); + break; + } + else if( (irqs & ST25R3911_IRQ_MASK_COL) != 0U ) + { + gRFAL.TxRx.status = ERR_RF_COLLISION; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA; + + /* Check if there's a specific error handling for this */ + rfalErrorHandling(); + break; + } + else if( ((irqs & ST25R3911_IRQ_MASK_EOF) != 0U) && ((irqs & ST25R3911_IRQ_MASK_RXE) == 0U) ) + { + gRFAL.TxRx.status = ERR_LINK_LOSS; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + break; + } + else if( ((irqs & ST25R3911_IRQ_MASK_RXE) != 0U) || (gRFAL.TxRx.rxse) ) + { + /* Reception ended without any error indication, * + * check FIFO status for malformed or incomplete frames */ + + /* Check if the reception ends with an incomplete byte (residual bits) */ + if( rfalFIFOStatusIsIncompleteByte() ) + { + gRFAL.TxRx.status = ERR_INCOMPLETE_BYTE; + } + /* Check if the reception ends with missing parity bit */ + else if( rfalFIFOStatusIsMissingPar() ) + { + gRFAL.TxRx.status = ERR_FRAMING; + } + else + { + /* MISRA 15.7 - Empty else */ + } + + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_READ_DATA; + } + else + { + gRFAL.TxRx.status = ERR_IO; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + break; + } + + /* fall through */ + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_READ_DATA: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + tmp = rfalFIFOStatusGetNumBytes(); + + /*******************************************************************************/ + /* Check if CRC should not be placed in rxBuf */ + if( ((gRFAL.TxRx.ctx.flags & (uint32_t)RFAL_TXRX_FLAGS_CRC_RX_KEEP) == 0U) ) + { + /* Check if CRC is being placed into the FIFO and if received frame was bigger than CRC */ + if( st25r3911IsCRCinFIFO() && ((gRFAL.fifo.bytesTotal + tmp) > 0U) ) + { + /* By default CRC will not be placed into the rxBuffer */ + if( ( tmp > (uint8_t)RFAL_CRC_LEN) ) + { + tmp -= (uint8_t)RFAL_CRC_LEN; + } + /* If the CRC was already placed into rxBuffer (due to WL interrupt where CRC was already in FIFO Read) + * cannot remove it from rxBuf. Can only remove it from rxBufLen not indicate the presence of CRC */ + else if(gRFAL.fifo.bytesTotal > (uint16_t)RFAL_CRC_LEN) + { + gRFAL.fifo.bytesTotal -= (uint16_t)RFAL_CRC_LEN; + } + else + { + /* MISRA 15.7 - Empty else */ + } + } + } + + gRFAL.fifo.bytesTotal += tmp; /* add to total bytes counter */ + + /*******************************************************************************/ + /* Check if remaining bytes fit on the rxBuf available */ + if( gRFAL.fifo.bytesTotal > rfalConvBitsToBytes(gRFAL.TxRx.ctx.rxBufLen) ) + { + tmp = (uint8_t)( rfalConvBitsToBytes(gRFAL.TxRx.ctx.rxBufLen) - gRFAL.fifo.bytesWritten); + + gRFAL.TxRx.status = ERR_NOMEM; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + } + + /*******************************************************************************/ + /* Retrieve remaining bytes from FIFO to rxBuf, and assign total length rcvd */ + st25r3911ReadFifo( &gRFAL.TxRx.ctx.rxBuf[gRFAL.fifo.bytesWritten], tmp); + if( (gRFAL.TxRx.ctx.rxRcvdLen != NULL) ) + { + (*gRFAL.TxRx.ctx.rxRcvdLen) = (uint16_t)rfalConvBytesToBits( gRFAL.fifo.bytesTotal ); + if( rfalFIFOStatusIsIncompleteByte() ) + { + (*gRFAL.TxRx.ctx.rxRcvdLen) -= (RFAL_BITS_IN_BYTE - rfalFIFOGetNumIncompleteBits()); + } + } + + #if RFAL_FEATURE_NFCV + /*******************************************************************************/ + /* Decode sub bit stream into payload bits for NFCV, if no error found so far */ + if( ((RFAL_MODE_POLL_NFCV == gRFAL.mode) || (RFAL_MODE_POLL_PICOPASS == gRFAL.mode)) && (gRFAL.TxRx.status == ERR_BUSY) ) + { + ReturnCode ret; + uint16_t offset = 0; + + ret = iso15693VICCDecode(gRFAL.TxRx.ctx.rxBuf, gRFAL.fifo.bytesTotal, + gRFAL.nfcvData.origCtx.rxBuf, rfalConvBitsToBytes(gRFAL.nfcvData.origCtx.rxBufLen), &offset, gRFAL.nfcvData.origCtx.rxRcvdLen, gRFAL.nfcvData.ignoreBits, (RFAL_MODE_POLL_PICOPASS == gRFAL.mode) ); + + if( ((ERR_NONE == ret) || (ERR_CRC == ret)) + && (((uint32_t)RFAL_TXRX_FLAGS_CRC_RX_KEEP & gRFAL.nfcvData.origCtx.flags) == 0U) + && ((*gRFAL.nfcvData.origCtx.rxRcvdLen % RFAL_BITS_IN_BYTE) == 0U) + && (*gRFAL.nfcvData.origCtx.rxRcvdLen >= rfalConvBytesToBits(RFAL_CRC_LEN) ) + ) + { + *gRFAL.nfcvData.origCtx.rxRcvdLen -= (uint16_t)rfalConvBytesToBits(RFAL_CRC_LEN); /* Remove CRC */ + } + + /* Restore original ctx */ + gRFAL.TxRx.ctx = gRFAL.nfcvData.origCtx; + gRFAL.TxRx.status = ((ret != ERR_NONE) ? ret : ERR_BUSY); + } + #endif /* RFAL_FEATURE_NFCV */ + + /*******************************************************************************/ + /* If an error as been marked/detected don't fall into to RX_DONE */ + if( gRFAL.TxRx.status != ERR_BUSY ) + { + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + break; + } + + if( rfalIsModeActiveComm( gRFAL.mode ) ) + { + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_EOF; + break; + } + + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_DONE; + /* fall through */ + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_DONE: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + /*Check if Observation Mode was enabled and disable it on ST25R391x */ + rfalCheckDisableObsMode(); + + /* Clean up Transceive */ + rfalCleanupTransceive(); + + + gRFAL.TxRx.status = ERR_NONE; + gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE; + break; + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_READ_FIFO: + + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911B Errata #1.1 */ + /* ST25R3911 may indicate RXS without RXE afterwards, this happens rarely on */ + /* corrupted frames. */ + /* Re-Start SW timer to handle an eventual missing RXE */ + rfalTimerStart( gRFAL.tmr.RXE, RFAL_NORXE_TOUT ); + /*******************************************************************************/ + + + tmp = rfalFIFOStatusGetNumBytes(); + gRFAL.fifo.bytesTotal += tmp; + + /*******************************************************************************/ + /* Calculate the amount of bytes that still fits in rxBuf */ + aux = (uint8_t)(( gRFAL.fifo.bytesTotal > rfalConvBitsToBytes(gRFAL.TxRx.ctx.rxBufLen) ) ? (rfalConvBitsToBytes(gRFAL.TxRx.ctx.rxBufLen) - gRFAL.fifo.bytesWritten) : tmp); + + /*******************************************************************************/ + /* Retrieve incoming bytes from FIFO to rxBuf, and store already read amount */ + st25r3911ReadFifo( &gRFAL.TxRx.ctx.rxBuf[gRFAL.fifo.bytesWritten], aux); + gRFAL.fifo.bytesWritten += aux; + + /*******************************************************************************/ + /* If the bytes already read were not the full FIFO WL, dump the remaining * + * FIFO so that ST25R391x can continue with reception */ + if( aux < tmp ) + { + st25r3911ReadFifo( NULL, (tmp - aux) ); + } + + rfalFIFOStatusClear(); + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_RXE; + break; + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_FAIL: + + /*Check if Observation Mode was enabled and disable it on ST25R391x */ + rfalCheckDisableObsMode(); + + /* Clean up Transceive */ + rfalCleanupTransceive(); + + /* Error should be assigned by previous state */ + if( gRFAL.TxRx.status == ERR_BUSY ) + { + gRFAL.TxRx.status = ERR_SYSTEM; + } + + /*rfalLogD( "RFAL: curSt: %d Error: %d \r\n", gRFAL.TxRx.state, gRFAL.TxRx.status );*/ + gRFAL.TxRx.state = RFAL_TXRX_STATE_IDLE; + break; + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_WAIT_EON: + + irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_EON | ST25R3911_IRQ_MASK_NRE) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + break; /* No interrupt to process */ + } + + if( (irqs & ST25R3911_IRQ_MASK_EON) != 0U ) + { + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_WAIT_RXS; + } + + if( (irqs & ST25R3911_IRQ_MASK_NRE) != 0U ) + { + /* ST25R3911 uses the NRT to measure other device's Field On max time: Tadt + (n x Trfw) */ + gRFAL.TxRx.status = ERR_LINK_LOSS; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + } + break; + + + /*******************************************************************************/ + case RFAL_TXRX_STATE_RX_WAIT_EOF: + + irqs = st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_CAT | ST25R3911_IRQ_MASK_CAC) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + break; /* No interrupt to process */ + } + + if( (irqs & ST25R3911_IRQ_MASK_CAT) != 0U ) + { + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_DONE; + } + else if( (irqs & ST25R3911_IRQ_MASK_CAC) != 0U ) + { + gRFAL.TxRx.status = ERR_RF_COLLISION; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + } + else + { + gRFAL.TxRx.status = ERR_IO; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + } + break; + + + /*******************************************************************************/ + default: + gRFAL.TxRx.status = ERR_SYSTEM; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_FAIL; + break; + } +} + +/*******************************************************************************/ +static void rfalFIFOStatusUpdate( void ) +{ + if(gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] == RFAL_FIFO_STATUS_INVALID) + { + st25r3911ReadMultipleRegisters( ST25R3911_REG_FIFO_RX_STATUS1, gRFAL.fifo.status, ST25R3911_FIFO_STATUS_LEN ); + } +} + + +/*******************************************************************************/ +static void rfalFIFOStatusClear( void ) +{ + gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] = RFAL_FIFO_STATUS_INVALID; +} + + +/*******************************************************************************/ +static uint8_t rfalFIFOStatusGetNumBytes( void ) +{ + rfalFIFOStatusUpdate(); + + return gRFAL.fifo.status[RFAL_FIFO_STATUS_REG1]; + +} + + +/*******************************************************************************/ +static bool rfalFIFOStatusIsIncompleteByte( void ) +{ + rfalFIFOStatusUpdate(); + return ((gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] & (ST25R3911_REG_FIFO_RX_STATUS2_mask_fifo_lb | ST25R3911_REG_FIFO_RX_STATUS2_fifo_ncp)) != 0U); +} + + +/*******************************************************************************/ +static bool rfalFIFOStatusIsMissingPar( void ) +{ + rfalFIFOStatusUpdate(); + return ((gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] & ST25R3911_REG_FIFO_RX_STATUS2_np_lb) != 0U); +} + + +/*******************************************************************************/ +static uint8_t rfalFIFOGetNumIncompleteBits( void ) +{ + rfalFIFOStatusUpdate(); + return ((gRFAL.fifo.status[RFAL_FIFO_STATUS_REG2] & ST25R3911_REG_FIFO_RX_STATUS2_mask_fifo_lb) >> ST25R3911_REG_FIFO_RX_STATUS2_shift_fifo_lb); +} + + +#if RFAL_FEATURE_NFCA + +/*******************************************************************************/ +ReturnCode rfalISO14443ATransceiveShortFrame( rfal14443AShortFrameCmd txCmd, uint8_t* rxBuf, uint8_t rxBufLen, uint16_t* rxRcvdLen, uint32_t fwt ) +{ + ReturnCode ret; + uint8_t directCmd; + + /* Check if RFAL is properly initialized */ + if( !st25r3911IsTxEnabled() || (gRFAL.state < RFAL_STATE_MODE_SET) || (( gRFAL.mode != RFAL_MODE_POLL_NFCA ) && ( gRFAL.mode != RFAL_MODE_POLL_NFCA_T1T )) ) + { + return ERR_WRONG_STATE; + } + + /* Check for valid parameters */ + if( (rxBuf == NULL) || (rxRcvdLen == NULL) || (fwt == RFAL_FWT_NONE) ) + { + return ERR_PARAM; + } + + /*******************************************************************************/ + /* Select the Direct Command to be performed */ + switch (txCmd) + { + case RFAL_14443A_SHORTFRAME_CMD_WUPA: + directCmd = ST25R3911_CMD_TRANSMIT_WUPA; + break; + + case RFAL_14443A_SHORTFRAME_CMD_REQA: + directCmd = ST25R3911_CMD_TRANSMIT_REQA; + break; + + default: + return ERR_PARAM; + } + + + /*******************************************************************************/ + /* Enable anti collision to recognise collision in first byte of SENS_REQ */ + st25r3911SetRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_antcl); + + /* Disable CRC while receiving since ATQA has no CRC included */ + st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_no_crc_rx ); + + + /*******************************************************************************/ + /* Wait for GT and FDT */ + while( !rfalIsGTExpired() ) { /* MISRA 15.6: mandatory brackets */ }; + while( st25r3911IsGPTRunning() ) { /* MISRA 15.6: mandatory brackets */ }; + + gRFAL.tmr.GT = RFAL_TIMING_NONE; + + + /*******************************************************************************/ + /* Prepare for Transceive, Receive only (bypass Tx states) */ + gRFAL.TxRx.ctx.flags = ((uint32_t) RFAL_TXRX_FLAGS_CRC_TX_MANUAL | (uint32_t)RFAL_TXRX_FLAGS_CRC_RX_KEEP ); + gRFAL.TxRx.ctx.rxBuf = rxBuf; + gRFAL.TxRx.ctx.rxBufLen = rxBufLen; + gRFAL.TxRx.ctx.rxRcvdLen = rxRcvdLen; + + /*******************************************************************************/ + /* Load NRT with FWT */ + st25r3911SetNoResponseTime_64fcs( rfalConv1fcTo64fc( MIN( (fwt + RFAL_FWT_ADJUSTMENT + RFAL_FWT_A_ADJUSTMENT), RFAL_ST25R3911_NRT_MAX_1FC ) ) ); + + if( gRFAL.timings.FDTListen != RFAL_TIMING_NONE ) + { + /* Set Minimum FDT(Listen) in which PICC is not allowed to send a response */ + st25r3911WriteRegister( ST25R3911_REG_MASK_RX_TIMER, (uint8_t)rfalConv1fcTo64fc( ((RFAL_FDT_LISTEN_MRT_ADJUSTMENT + RFAL_FDT_LISTEN_A_ADJUSTMENT) > gRFAL.timings.FDTListen) ? RFAL_ST25R3911_MRT_MIN_1FC : (gRFAL.timings.FDTListen - (RFAL_FDT_LISTEN_MRT_ADJUSTMENT + RFAL_FDT_LISTEN_A_ADJUSTMENT)) ) ); + } + + /* In Passive communications General Purpose Timer is used to measure FDT Poll */ + if( gRFAL.timings.FDTPoll != RFAL_TIMING_NONE ) + { + /* Configure GPT to start at RX end */ + st25r3911StartGPTimer_8fcs( (uint16_t)rfalConv1fcTo8fc( MIN( gRFAL.timings.FDTPoll, (gRFAL.timings.FDTPoll - RFAL_FDT_POLL_ADJUSTMENT) ) ), ST25R3911_REG_GPT_CONTROL_gptc_erx ); + } + + /*******************************************************************************/ + rfalPrepareTransceive(); + + /* Also enable bit collision interrupt */ + st25r3911GetInterrupt( ST25R3911_IRQ_MASK_COL ); + st25r3911EnableInterrupts( ST25R3911_IRQ_MASK_COL ); + + /*Check if Observation Mode is enabled and set it on ST25R391x */ + rfalCheckEnableObsModeTx(); + + /*******************************************************************************/ + /* Chip bug: Clear nbtx bits before sending WUPA/REQA - otherwise ST25R3911 will report parity error */ + st25r3911WriteRegister( ST25R3911_REG_NUM_TX_BYTES2, 0); + + /* Send either WUPA or REQA. All affected tags will backscatter ATQA and change to READY state */ + st25r3911ExecuteCommand( directCmd ); + + /* Wait for TXE */ + if( st25r3911WaitForInterruptsTimed( ST25R3911_IRQ_MASK_TXE, (uint16_t)MAX( rfalConv1fcToMs( fwt ), RFAL_ST25R3911_SW_TMR_MIN_1MS ) ) == 0U) + { + ret = ERR_IO; + } + else + { + /*Check if Observation Mode is enabled and set it on ST25R391x */ + rfalCheckEnableObsModeRx(); + + /* Jump into a transceive Rx state for reception (bypass Tx states) */ + gRFAL.state = RFAL_STATE_TXRX; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_IDLE; + gRFAL.TxRx.status = ERR_BUSY; + + /* Execute Transceive Rx blocking */ + ret = rfalTransceiveBlockingRx(); + } + + + /* Disable Collision interrupt */ + st25r3911DisableInterrupts( (ST25R3911_IRQ_MASK_COL) ); + + /* Disable anti collision again */ + st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_antcl ); + + /* ReEnable CRC on Rx */ + st25r3911ClrRegisterBits(ST25R3911_REG_AUX, ST25R3911_REG_AUX_no_crc_rx ); + + return ret; +} + +/*******************************************************************************/ +ReturnCode rfalISO14443ATransceiveAnticollisionFrame( uint8_t *buf, uint8_t *bytesToSend, uint8_t *bitsToSend, uint16_t *rxLength, uint32_t fwt ) +{ + ReturnCode ret; + rfalTransceiveContext ctx; + uint8_t collByte; + uint8_t collData; + + /* Check if RFAL is properly initialized */ + if( (gRFAL.state < RFAL_STATE_MODE_SET) || ( gRFAL.mode != RFAL_MODE_POLL_NFCA ) ) + { + return ERR_WRONG_STATE; + } + + /* Check for valid parameters */ + if( (buf == NULL) || (bytesToSend == NULL) || (bitsToSend == NULL) || (rxLength == NULL) ) + { + return ERR_PARAM; + } + + /*******************************************************************************/ + /* Set speficic Analog Config for Anticolission if needed */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_ANTICOL) ); + + + /*******************************************************************************/ + /* Enable anti collision to recognise collision in first byte of SENS_REQ */ + st25r3911SetRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_antcl ); + + /* Disable CRC while receiving */ + st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_no_crc_rx ); + + + + /*******************************************************************************/ + /* Prepare for Transceive */ + ctx.flags = ( (uint32_t)RFAL_TXRX_FLAGS_CRC_TX_MANUAL | (uint32_t)RFAL_TXRX_FLAGS_CRC_RX_KEEP | (uint32_t)RFAL_TXRX_FLAGS_AGC_OFF ); /* Disable Automatic Gain Control (AGC) for better detection of collision */ + ctx.txBuf = buf; + ctx.txBufLen = (uint16_t)(rfalConvBytesToBits( *bytesToSend ) + *bitsToSend ); + ctx.rxBuf = &buf[*bytesToSend]; + ctx.rxBufLen = (uint16_t)rfalConvBytesToBits( RFAL_ISO14443A_SDD_RES_LEN ); + ctx.rxRcvdLen = rxLength; + ctx.fwt = fwt; + + rfalStartTransceive( &ctx ); + + /* Additionally enable bit collision interrupt */ + st25r3911GetInterrupt( ST25R3911_IRQ_MASK_COL ); + st25r3911EnableInterrupts( ST25R3911_IRQ_MASK_COL ); + + /*******************************************************************************/ + collByte = 0; + + /* save the collision byte */ + if ((*bitsToSend) > 0U) + { + buf[(*bytesToSend)] <<= (RFAL_BITS_IN_BYTE - (*bitsToSend)); + buf[(*bytesToSend)] >>= (RFAL_BITS_IN_BYTE - (*bitsToSend)); + collByte = buf[(*bytesToSend)]; + } + + + /*******************************************************************************/ + /* Run Transceive blocking */ + ret = rfalTransceiveRunBlockingTx(); + if( ret == ERR_NONE) + { + ret = rfalTransceiveBlockingRx(); + + /*******************************************************************************/ + if ((*bitsToSend) > 0U) + { + buf[(*bytesToSend)] >>= (*bitsToSend); + buf[(*bytesToSend)] <<= (*bitsToSend); + buf[(*bytesToSend)] |= collByte; + } + + if( (ERR_RF_COLLISION == ret) ) + { + /* read out collision register */ + st25r3911ReadRegister( ST25R3911_REG_COLLISION_STATUS, &collData); + + (*bytesToSend) = ((collData >> ST25R3911_REG_COLLISION_STATUS_shift_c_byte) & 0x0FU); // 4-bits Byte information + (*bitsToSend) = ((collData >> ST25R3911_REG_COLLISION_STATUS_shift_c_bit) & 0x07U); // 3-bits bit information + + } + } + + + /*******************************************************************************/ + /* Disable Collision interrupt */ + st25r3911DisableInterrupts( (ST25R3911_IRQ_MASK_COL) ); + + /* Disable anti collision again */ + st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_antcl ); + + /* ReEnable CRC on Rx */ + st25r3911ClrRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_no_crc_rx ); + /*******************************************************************************/ + + + /* Restore common Analog configurations for this mode */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_TX) ); + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCA | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_RX) ); + + return ret; +} + +#endif /* RFAL_FEATURE_NFCA */ + +#if RFAL_FEATURE_NFCV + +/*******************************************************************************/ +ReturnCode rfalISO15693TransceiveAnticollisionFrame( uint8_t *txBuf, uint8_t txBufLen, uint8_t *rxBuf, uint8_t rxBufLen, uint16_t *actLen ) +{ + ReturnCode ret; + rfalTransceiveContext ctx; + + /* Check if RFAL is properly initialized */ + if( (gRFAL.state < RFAL_STATE_MODE_SET) || ( gRFAL.mode != RFAL_MODE_POLL_NFCV ) ) + { + return ERR_WRONG_STATE; + } + + /*******************************************************************************/ + /* Set speficic Analog Config for Anticolission if needed */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCV | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_ANTICOL) ); + + + /* Ignoring collisions before the UID (RES_FLAG + DSFID) */ + gRFAL.nfcvData.ignoreBits = (uint16_t)RFAL_ISO15693_IGNORE_BITS; + + /*******************************************************************************/ + /* Prepare for Transceive */ + ctx.flags = ((txBufLen==0U)?(uint32_t)RFAL_TXRX_FLAGS_CRC_TX_MANUAL:(uint32_t)RFAL_TXRX_FLAGS_CRC_TX_AUTO) | (uint32_t)RFAL_TXRX_FLAGS_CRC_RX_KEEP | (uint32_t)RFAL_TXRX_FLAGS_AGC_OFF | ((txBufLen==0U)?(uint32_t)RFAL_TXRX_FLAGS_NFCV_FLAG_MANUAL:(uint32_t)RFAL_TXRX_FLAGS_NFCV_FLAG_AUTO); /* Disable Automatic Gain Control (AGC) for better detection of collision */ + ctx.txBuf = txBuf; + ctx.txBufLen = (uint16_t)rfalConvBytesToBits(txBufLen); + ctx.rxBuf = rxBuf; + ctx.rxBufLen = (uint16_t)rfalConvBytesToBits(rxBufLen); + ctx.rxRcvdLen = actLen; + ctx.fwt = rfalConv64fcTo1fc(ISO15693_FWT); + + rfalStartTransceive( &ctx ); + + /*******************************************************************************/ + /* Run Transceive blocking */ + ret = rfalTransceiveRunBlockingTx(); + if( ret == ERR_NONE) + { + ret = rfalTransceiveBlockingRx(); + } + + /* Restore common Analog configurations for this mode */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCV | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_TX) ); + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_POLL | RFAL_ANALOG_CONFIG_TECH_NFCV | RFAL_ANALOG_CONFIG_BITRATE_COMMON | RFAL_ANALOG_CONFIG_RX) ); + + gRFAL.nfcvData.ignoreBits = 0; + return ret; +} + +/*******************************************************************************/ +ReturnCode rfalISO15693TransceiveEOFAnticollision( uint8_t *rxBuf, uint8_t rxBufLen, uint16_t *actLen ) +{ + uint8_t dummy; + + return rfalISO15693TransceiveAnticollisionFrame( &dummy, 0, rxBuf, rxBufLen, actLen ); +} + +/*******************************************************************************/ +ReturnCode rfalISO15693TransceiveEOF( uint8_t *rxBuf, uint8_t rxBufLen, uint16_t *actLen ) +{ + ReturnCode ret; + uint8_t dummy; + + /* Check if RFAL is properly initialized */ + if( ( gRFAL.state < RFAL_STATE_MODE_SET ) || ( gRFAL.mode != RFAL_MODE_POLL_NFCV ) ) + { + return ERR_WRONG_STATE; + } + + /*******************************************************************************/ + /* Run Transceive blocking */ + ret = rfalTransceiveBlockingTxRx( &dummy, + 0, + rxBuf, + rxBufLen, + actLen, + ( (uint32_t)RFAL_TXRX_FLAGS_CRC_TX_MANUAL | (uint32_t)RFAL_TXRX_FLAGS_CRC_RX_KEEP |(uint32_t)RFAL_TXRX_FLAGS_AGC_ON ), + rfalConv64fcTo1fc(ISO15693_FWT) ); + return ret; +} + +#endif /* RFAL_FEATURE_NFCV */ + +#if RFAL_FEATURE_NFCF + +/*******************************************************************************/ +ReturnCode rfalFeliCaPoll( rfalFeliCaPollSlots slots, uint16_t sysCode, uint8_t reqCode, rfalFeliCaPollRes* pollResList, uint8_t pollResListSize, uint8_t *devicesDetected, uint8_t *collisionsDetected ) +{ + ReturnCode ret; + uint8_t frame[RFAL_FELICA_POLL_REQ_LEN - RFAL_FELICA_LEN_LEN]; // LEN is added by ST25R3911 automatically + uint16_t actLen; + uint8_t frameIdx; + uint8_t devDetected; + uint8_t colDetected; + rfalEHandling curHandling; + uint8_t nbSlots; + + /* Check if RFAL is properly initialized */ + if( (gRFAL.state < RFAL_STATE_MODE_SET) || ( gRFAL.mode != RFAL_MODE_POLL_NFCF ) ) + { + return ERR_WRONG_STATE; + } + + frameIdx = 0; + colDetected = 0; + devDetected = 0; + nbSlots = (uint8_t)slots; + + /*******************************************************************************/ + /* Compute SENSF_REQ frame */ + frame[frameIdx++] = (uint8_t)FELICA_CMD_POLLING; /* CMD: SENF_REQ */ + frame[frameIdx++] = (uint8_t)(sysCode >> 8); /* System Code (SC) */ + frame[frameIdx++] = (uint8_t)(sysCode & 0xFFU); /* System Code (SC) */ + frame[frameIdx++] = reqCode; /* Communication Parameter Request (RC)*/ + frame[frameIdx++] = nbSlots; /* TimeSlot (TSN) */ + + + /*******************************************************************************/ + /* NRT should not stop on reception - Use EMVCo mode to run NRT in nrt_emv * + * ERRORHANDLING_EMVCO has no special handling for NFC-F mode */ + curHandling = gRFAL.conf.eHandling; + rfalSetErrorHandling( RFAL_ERRORHANDLING_EMVCO ); + + /*******************************************************************************/ + /* Run transceive blocking, + * Calculate Total Response Time in(64/fc): + * 512 PICC process time + (n * 256 Time Slot duration) */ + ret = rfalTransceiveBlockingTx( frame, + (uint16_t)frameIdx, + (uint8_t*)gRFAL.nfcfData.pollResponses, + RFAL_FELICA_POLL_RES_LEN, + &actLen, + (RFAL_TXRX_FLAGS_DEFAULT), + rfalConv64fcTo1fc( RFAL_FELICA_POLL_DELAY_TIME + (RFAL_FELICA_POLL_SLOT_TIME * ((uint32_t)nbSlots + 1U)) ) ); + + /*******************************************************************************/ + /* If Tx OK, Wait for all responses, store them as soon as they appear */ + if( ret == ERR_NONE ) + { + bool timeout; + + do + { + ret = rfalTransceiveBlockingRx(); + if( ret == ERR_TIMEOUT ) + { + /* Upon timeout the full Poll Delay + (Slot time)*(nbSlots) has expired */ + timeout = true; + } + else + { + /* Reception done, reEnabled Rx for following Slot */ + st25r3911ExecuteCommand( ST25R3911_CMD_UNMASK_RECEIVE_DATA ); + st25r3911ExecuteCommand( ST25R3911_CMD_CLEAR_SQUELCH ); + + /* If the reception was OK, new device found */ + if( ret == ERR_NONE ) + { + devDetected++; + + /* Overwrite the Transceive context for the next reception */ + gRFAL.TxRx.ctx.rxBuf = (uint8_t*)gRFAL.nfcfData.pollResponses[devDetected]; + } + /* If the reception was not OK, mark as collision */ + else + { + colDetected++; + } + + /* Check whether NRT has expired meanwhile */ + timeout = st25r3911CheckReg( ST25R3911_REG_REGULATOR_RESULT, ST25R3911_REG_REGULATOR_RESULT_nrt_on, 0x00 ); + if( !timeout ) + { + /* Jump again into transceive Rx state for the following reception */ + gRFAL.TxRx.status = ERR_BUSY; + gRFAL.state = RFAL_STATE_TXRX; + gRFAL.TxRx.state = RFAL_TXRX_STATE_RX_IDLE; + } + } + }while( ((nbSlots--) != 0U) && !timeout ); + } + + /*******************************************************************************/ + /* Restore NRT to normal mode - back to previous error handling */ + rfalSetErrorHandling( curHandling ); + + /*******************************************************************************/ + /* Assign output parameters if requested */ + + if( (pollResList != NULL) && (pollResListSize > 0U) && (devDetected > 0U) ) + { + ST_MEMCPY( pollResList, gRFAL.nfcfData.pollResponses, (RFAL_FELICA_POLL_RES_LEN * (uint32_t)MIN(pollResListSize, devDetected) ) ); + } + + if( devicesDetected != NULL ) + { + *devicesDetected = devDetected; + } + + if( collisionsDetected != NULL ) + { + *collisionsDetected = colDetected; + } + + return (( (colDetected != 0U) || (devDetected != 0U)) ? ERR_NONE : ret); +} + +#endif /* RFAL_FEATURE_NFCF */ + + +/***************************************************************************** + * Listen Mode * + *****************************************************************************/ + + + +/*******************************************************************************/ +bool rfalIsExtFieldOn( void ) +{ + return st25r3911IsExtFieldOn(); +} + +#if RFAL_FEATURE_LISTEN_MODE + +/*******************************************************************************/ +ReturnCode rfalListenStart( uint32_t lmMask, const rfalLmConfPA *confA, const rfalLmConfPB *confB, const rfalLmConfPF *confF, uint8_t *rxBuf, uint16_t rxBufLen, uint16_t *rxLen ) +{ + NO_WARNING(confA); + NO_WARNING(confB); + NO_WARNING(confF); + + + gRFAL.Lm.state = RFAL_LM_STATE_NOT_INIT; + + + /*******************************************************************************/ + if( ((lmMask & RFAL_LM_MASK_NFCA) != 0U) || ((lmMask & RFAL_LM_MASK_NFCB) != 0U) || ((lmMask & RFAL_LM_MASK_NFCF) != 0U) ) + { + return ERR_NOTSUPP; + } + + + /*******************************************************************************/ + if( (lmMask & RFAL_LM_MASK_ACTIVE_P2P) != 0U ) + { + gRFAL.state = RFAL_STATE_LM; + + gRFAL.Lm.rxBuf = rxBuf; + gRFAL.Lm.rxBufLen = rxBufLen; + gRFAL.Lm.rxLen = rxLen; + *gRFAL.Lm.rxLen = 0; + gRFAL.Lm.dataFlag = false; + + /* Disable GPT trigger source */ + st25r3911ChangeRegisterBits( ST25R3911_REG_GPT_CONTROL, ST25R3911_REG_GPT_CONTROL_gptc_mask, ST25R3911_REG_GPT_CONTROL_gptc_no_trigger ); + + /* On Bit Rate Detection Mode ST25R391x will filter incoming frames during MRT time starting on External Field On event, use 512/fc steps */ + st25r3911WriteRegister( ST25R3911_REG_MASK_RX_TIMER, (uint8_t)rfalConv1fcTo512fc( RFAL_LM_GT ) ); + + /* Restore default settings on NFCIP1 mode, Receiving parity + CRC bits and manual Tx Parity*/ + st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, (ST25R3911_REG_ISO14443A_NFC_no_tx_par | ST25R3911_REG_ISO14443A_NFC_no_rx_par | ST25R3911_REG_ISO14443A_NFC_nfc_f0) ); + + /* Enable External Field Detector */ + st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd ); + + /* Enable Receiver */ + st25r3911ChangeRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_rx_en, ST25R3911_REG_OP_CONTROL_rx_en ); + + /* Set Analog configurations for generic Listen mode */ + /* Not on SetState(POWER OFF) as otherwise would be applied on every Field Event */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_LISTEN_ON) ); + + /* Initialize as POWER_OFF and set proper mode in RF Chip */ + rfalListenSetState( RFAL_LM_STATE_POWER_OFF ); + } + else + { + return ERR_REQUEST; /* Listen Start called but no mode was enabled */ + } + + return ERR_NONE; +} + + + +/*******************************************************************************/ +static ReturnCode rfalRunListenModeWorker( void ) +{ + volatile uint32_t irqs; + uint8_t tmp; + + if( gRFAL.state != RFAL_STATE_LM ) + { + return ERR_WRONG_STATE; + } + + switch( gRFAL.Lm.state ) + { + /*******************************************************************************/ + case RFAL_LM_STATE_POWER_OFF: + + irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_EON ) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + break; /* No interrupt to process */ + } + + if( (irqs & ST25R3911_IRQ_MASK_EON) != 0U ) + { + rfalListenSetState( RFAL_LM_STATE_IDLE ); + } + else + { + break; + } + /* fall through */ + + + /*******************************************************************************/ + case RFAL_LM_STATE_IDLE: /* PRQA S 2003 # MISRA 16.3 - Intentional fall through */ + + irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_NFCT | ST25R3911_IRQ_MASK_RXE | ST25R3911_IRQ_MASK_EOF ) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + break; /* No interrupt to process */ + } + + if( (irqs & ST25R3911_IRQ_MASK_NFCT) != 0U ) + { + /* Retrieve detected bitrate */ + uint8_t newBr; + st25r3911ReadRegister( ST25R3911_REG_NFCIP1_BIT_RATE, &newBr ); + newBr >>= ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_shift; + + if (newBr > ST25R3911_REG_BIT_RATE_rxrate_424) + { + newBr = ST25R3911_REG_BIT_RATE_rxrate_424; + } + + gRFAL.Lm.brDetected = (rfalBitRate)(newBr); /* PRQA S 4342 # MISRA 10.5 - Guaranteed that no invalid enum values may be created. See also equalityGuard_RFAL_BR_106 ff.*/ + } + if( ((irqs & ST25R3911_IRQ_MASK_RXE) != 0U) && (gRFAL.Lm.brDetected != RFAL_BR_KEEP) ) + { + irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_RXE | ST25R3911_IRQ_MASK_EOF | ST25R3911_IRQ_MASK_CRC | ST25R3911_IRQ_MASK_PAR | ST25R3911_IRQ_MASK_ERR2 | ST25R3911_IRQ_MASK_ERR1 ) ); + + if( ((irqs & ST25R3911_IRQ_MASK_CRC) != 0U) || ((irqs & ST25R3911_IRQ_MASK_PAR) != 0U) || ((irqs & ST25R3911_IRQ_MASK_ERR1) != 0U) ) + { + /* nfc_ar may have triggered RF Collision Avoidance, disable it before executing Clear (Stop All activities) */ + st25r3911ClrRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar ); + st25r3911ExecuteCommand( ST25R3911_CMD_CLEAR_FIFO ); + st25r3911ExecuteCommand( ST25R3911_CMD_UNMASK_RECEIVE_DATA ); + st25r3911SetRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar ); + st25r3911TxOff(); + break; /* A bad reception occurred, remain in same state */ + } + + /* Retrieve received data */ + st25r3911ReadRegister(ST25R3911_REG_FIFO_RX_STATUS1, &tmp); + *gRFAL.Lm.rxLen = tmp; + + st25r3911ReadFifo( gRFAL.Lm.rxBuf, (uint8_t)MIN( *gRFAL.Lm.rxLen, rfalConvBitsToBytes(gRFAL.Lm.rxBufLen) ) ); + + /* Check if the data we got has at least the CRC and remove it, otherwise leave at 0 */ + *gRFAL.Lm.rxLen -= ((*gRFAL.Lm.rxLen > RFAL_CRC_LEN) ? RFAL_CRC_LEN : *gRFAL.Lm.rxLen); + *gRFAL.Lm.rxLen = (uint16_t)rfalConvBytesToBits( *gRFAL.Lm.rxLen ); + gRFAL.Lm.dataFlag = true; + + /*Check if Observation Mode was enabled and disable it on ST25R391x */ + rfalCheckDisableObsMode(); + } + else if( ((irqs & ST25R3911_IRQ_MASK_EOF) != 0U) && (!gRFAL.Lm.dataFlag) ) + { + rfalListenSetState( RFAL_LM_STATE_POWER_OFF ); + } + else + { + /* MISRA 15.7 - Empty else */ + } + break; + + /*******************************************************************************/ + case RFAL_LM_STATE_READY_F: + case RFAL_LM_STATE_READY_A: + case RFAL_LM_STATE_ACTIVE_A: + case RFAL_LM_STATE_ACTIVE_Ax: + case RFAL_LM_STATE_SLEEP_A: + case RFAL_LM_STATE_SLEEP_B: + case RFAL_LM_STATE_SLEEP_AF: + case RFAL_LM_STATE_READY_Ax: + case RFAL_LM_STATE_CARDEMU_4A: + case RFAL_LM_STATE_CARDEMU_4B: + case RFAL_LM_STATE_CARDEMU_3: + return ERR_INTERNAL; + + case RFAL_LM_STATE_TARGET_F: + case RFAL_LM_STATE_TARGET_A: + break; + + /*******************************************************************************/ + default: + return ERR_WRONG_STATE; + } + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalListenStop( void ) +{ + gRFAL.Lm.state = RFAL_LM_STATE_NOT_INIT; + + /*Check if Observation Mode was enabled and disable it on ST25R391x */ + rfalCheckDisableObsMode(); + + /* Disable Receiver and Transmitter */ + rfalFieldOff(); + + /* As there's no Off mode, set default value: ISO14443A with automatic RF Collision Avoidance Off */ + st25r3911WriteRegister( ST25R3911_REG_MODE, (ST25R3911_REG_MODE_om_iso14443a | ST25R3911_REG_MODE_nfc_ar_off) ); + + /* Set Analog configurations for Listen Off event */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_LISTEN_OFF) ); + + return ERR_NONE; +} + + +/*******************************************************************************/ +/* PRQA S 3673 1 # MISRA 8.13 - ST25R3911B does not support Listen mode. Implementation for other chips will modify rxBuf and rxLen */ +ReturnCode rfalListenSleepStart( rfalLmState sleepSt, uint8_t *rxBuf, uint16_t rxBufLen, uint16_t *rxLen ) +{ + NO_WARNING(sleepSt); + NO_WARNING(rxBuf); + NO_WARNING(rxBufLen); + NO_WARNING(rxLen); + + return ERR_NOTSUPP; +} + + +/*******************************************************************************/ +rfalLmState rfalListenGetState( bool *dataFlag, rfalBitRate *lastBR ) +{ + /* Allow state retrieval even if gRFAL.state != RFAL_STATE_LM so * + * that this Lm state can be used by caller after activation */ + + if( lastBR != NULL ) + { + *lastBR = gRFAL.Lm.brDetected; + } + + if( dataFlag != NULL ) + { + *dataFlag = gRFAL.Lm.dataFlag; + } + + return gRFAL.Lm.state; +} + + +/*******************************************************************************/ +ReturnCode rfalListenSetState( rfalLmState newSt ) +{ + ReturnCode ret; + uint8_t tmp; + rfalLmState newState; + bool reSetState; + + /*rfalLogD( "RFAL: curState: %02X newState: %02X \r\n", gRFAL.Lm.state, newSt );*/ + + /* SetState clears the Data flag */ + gRFAL.Lm.dataFlag = false; + newState = newSt; + ret = ERR_NONE; + + do{ + reSetState = false; + + /*******************************************************************************/ + switch( newState ) + { + /*******************************************************************************/ + case RFAL_LM_STATE_POWER_OFF: + + /*******************************************************************************/ + /* Disable nfc_ar as RF Collision Avoidance timer may have already started */ + st25r3911ClrRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar ); + + st25r3911ExecuteCommand( ST25R3911_CMD_CLEAR_FIFO ); + + /* Ensure that our field is Off, as automatic response RF Collision Avoidance may have been triggered */ + st25r3911TxOff(); + + /*******************************************************************************/ + /* Ensure that the NFCIP1 mode is disabled */ + st25r3911ClrRegisterBits( ST25R3911_REG_ISO14443A_NFC, ST25R3911_REG_ISO14443A_NFC_nfc_f0 ); + + + /*******************************************************************************/ + /* Clear and enable required IRQs */ + st25r3911DisableInterrupts( ST25R3911_IRQ_MASK_ALL ); + + + st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_NFCT | ST25R3911_IRQ_MASK_RXS | ST25R3911_IRQ_MASK_CRC | ST25R3911_IRQ_MASK_ERR1 | + ST25R3911_IRQ_MASK_ERR2 | ST25R3911_IRQ_MASK_PAR | ST25R3911_IRQ_MASK_EON | ST25R3911_IRQ_MASK_EOF | ST25R3911_IRQ_MASK_RXE ) ); + + + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911 Errata TDB */ + /* RXS and NFCT are triggered very close (specially in higher bitrates). * + * If the interrupt status register is being read when NFCT is trigerred, the * + * IRQ line might go low and NFCT is not signalled on the status register. * + * For initial bitrate detection, mask RXS, only wait for NFCT and RXE. */ + /*******************************************************************************/ + + st25r3911EnableInterrupts( (ST25R3911_IRQ_MASK_NFCT | ST25R3911_IRQ_MASK_CRC | ST25R3911_IRQ_MASK_ERR1 | + ST25R3911_IRQ_MASK_ERR2 | ST25R3911_IRQ_MASK_PAR | ST25R3911_IRQ_MASK_EON | ST25R3911_IRQ_MASK_EOF | ST25R3911_IRQ_MASK_RXE ) ); + + /*******************************************************************************/ + /* Clear the bitRate previously detected */ + gRFAL.Lm.brDetected = RFAL_BR_KEEP; + + + /*******************************************************************************/ + /* Apply the BitRate detection mode mode */ + st25r3911WriteRegister( ST25R3911_REG_MODE, (ST25R3911_REG_MODE_targ_targ | ST25R3911_REG_MODE_om_bit_rate_detection | ST25R3911_REG_MODE_nfc_ar_on) ); + + + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911 Errata #1.3 */ + /* Even though bitrate is going to be detected the bitrate must be set to * + * 106kbps to get correct 106kbps parity */ + st25r3911WriteRegister( ST25R3911_REG_BIT_RATE, (ST25R3911_REG_BIT_RATE_txrate_106 | ST25R3911_REG_BIT_RATE_rxrate_106) ); + /*******************************************************************************/ + + + /*******************************************************************************/ + /* Check if external Field is already On */ + if( rfalIsExtFieldOn() ) + { + reSetState = true; + newState = RFAL_LM_STATE_IDLE; /* Set IDLE state */ + } + break; + + /*******************************************************************************/ + case RFAL_LM_STATE_IDLE: + + /*******************************************************************************/ + /* In Active P2P the Initiator may: Turn its field On; LM goes into IDLE state; + * Initiator sends an unexpected frame raising a Protocol error; Initiator + * turns its field Off and ST25R3911 performs the automatic RF Collision + * Avoidance keeping our field On; upon a Protocol error upper layer sets + * again the state to IDLE to clear dataFlag and wait for next data. + * + * Ensure that when upper layer calls SetState(IDLE), it restores initial + * configuration and that check whether an external Field is still present */ + + /* nfc_ar may have triggered RF Collision Avoidance, disable it before executing Clear (Stop All activities) */ + st25r3911ClrRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar ); + st25r3911ExecuteCommand( ST25R3911_CMD_CLEAR_FIFO ); + st25r3911SetRegisterBits( ST25R3911_REG_MODE, ST25R3911_REG_MODE_nfc_ar ); + + /* Ensure that our field is Off, as automatic response RF Collision Avoidance may have been triggered */ + st25r3911TxOff(); + + + /* Load 2nd/3rd stage gain setting from registers into the receiver */ + st25r3911ExecuteCommand( ST25R3911_CMD_CLEAR_SQUELCH ); + + /*******************************************************************************/ + /* REMARK: Silicon workaround ST25R3911 Errata #1.4 */ + /* Enable; disable; enable mixer to make sure the digital decoder is in * + * high state. This also switches the demodulator to mixer mode. */ + st25r3911ReadRegister( ST25R3911_REG_RX_CONF1, &tmp ); + st25r3911WriteRegister( ST25R3911_REG_RX_CONF1, (tmp | ST25R3911_REG_RX_CONF1_amd_sel) ); + st25r3911WriteRegister( ST25R3911_REG_RX_CONF1, (uint8_t)(tmp & ~ST25R3911_REG_RX_CONF1_amd_sel) ); + st25r3911WriteRegister( ST25R3911_REG_RX_CONF1, (tmp | ST25R3911_REG_RX_CONF1_amd_sel) ); + /*******************************************************************************/ + + /* ReEnable the receiver */ + st25r3911ExecuteCommand( ST25R3911_CMD_UNMASK_RECEIVE_DATA ); + + + /* If external Field is no longer detected go back to POWER_OFF */ + if( !st25r3911IsExtFieldOn() ) + { + reSetState = true; + newState = RFAL_LM_STATE_POWER_OFF; /* Set POWER_OFF state */ + } + + /*******************************************************************************/ + /*Check if Observation Mode is enabled and set it on ST25R391x */ + rfalCheckEnableObsModeRx(); + break; + + /*******************************************************************************/ + case RFAL_LM_STATE_TARGET_A: + case RFAL_LM_STATE_TARGET_F: + /* States not handled by the LM, just keep state context */ + break; + + /*******************************************************************************/ + case RFAL_LM_STATE_READY_F: + case RFAL_LM_STATE_CARDEMU_3: + case RFAL_LM_STATE_READY_Ax: + case RFAL_LM_STATE_READY_A: + case RFAL_LM_STATE_ACTIVE_Ax: + case RFAL_LM_STATE_ACTIVE_A: + case RFAL_LM_STATE_SLEEP_A: + case RFAL_LM_STATE_SLEEP_B: + case RFAL_LM_STATE_SLEEP_AF: + case RFAL_LM_STATE_CARDEMU_4A: + case RFAL_LM_STATE_CARDEMU_4B: + return ERR_NOTSUPP; + + /*******************************************************************************/ + default: + return ERR_WRONG_STATE; + } + } + while( reSetState ); + + gRFAL.Lm.state = newState; + + return ret; +} + +#endif /* RFAL_FEATURE_LISTEN_MODE */ + + +/******************************************************************************* + * Wake-Up Mode * + *******************************************************************************/ + +#if RFAL_FEATURE_WAKEUP_MODE + +/*******************************************************************************/ +ReturnCode rfalWakeUpModeStart( const rfalWakeUpConfig *config ) +{ + uint8_t aux; + uint8_t reg; + uint32_t irqs; + + /* The Wake-Up procedure is explained in detail in Application Note: AN4985 */ + + if( config == NULL ) + { + gRFAL.wum.cfg.period = RFAL_WUM_PERIOD_500MS; + gRFAL.wum.cfg.irqTout = false; + gRFAL.wum.cfg.swTagDetect = false; + + gRFAL.wum.cfg.indAmp.enabled = true; + gRFAL.wum.cfg.indPha.enabled = true; + gRFAL.wum.cfg.cap.enabled = false; + gRFAL.wum.cfg.indAmp.delta = 2U; + gRFAL.wum.cfg.indAmp.reference = RFAL_WUM_REFERENCE_AUTO; + gRFAL.wum.cfg.indAmp.autoAvg = false; + gRFAL.wum.cfg.indPha.delta = 2U; + gRFAL.wum.cfg.indPha.reference = RFAL_WUM_REFERENCE_AUTO; + gRFAL.wum.cfg.indPha.autoAvg = false; + } + else + { + gRFAL.wum.cfg = *config; + } + + + /* Check for valid configuration */ + if( (gRFAL.wum.cfg.cap.enabled && (gRFAL.wum.cfg.indAmp.enabled || gRFAL.wum.cfg.indPha.enabled)) || + (!gRFAL.wum.cfg.cap.enabled && !gRFAL.wum.cfg.indAmp.enabled && !gRFAL.wum.cfg.indPha.enabled) || + gRFAL.wum.cfg.swTagDetect ) + { + return ERR_PARAM; + } + + irqs = ST25R3911_IRQ_MASK_NONE; + + + /* Disable Tx, Rx, External Field Detector and set default ISO14443A mode */ + st25r3911TxRxOff(); + st25r3911ClrRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd ); + st25r3911ChangeRegisterBits(ST25R3911_REG_MODE, (ST25R3911_REG_MODE_targ | ST25R3911_REG_MODE_mask_om), (ST25R3911_REG_MODE_targ_init | ST25R3911_REG_MODE_om_iso14443a) ); + + /* Set Analog configurations for Wake-up On event */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_WAKEUP_ON) ); + + /*******************************************************************************/ + /* Prepare Wake-Up Timer Control Register */ + reg = (uint8_t)(((uint8_t)gRFAL.wum.cfg.period & 0x0FU) << ST25R3911_REG_WUP_TIMER_CONTROL_shift_wut); + reg |= (uint8_t)(((uint8_t)gRFAL.wum.cfg.period < (uint8_t)RFAL_WUM_PERIOD_100MS) ? ST25R3911_REG_WUP_TIMER_CONTROL_wur : 0x00U); + + if(gRFAL.wum.cfg.irqTout) + { + reg |= ST25R3911_REG_WUP_TIMER_CONTROL_wto; + irqs |= ST25R3911_IRQ_MASK_WT; + } + + /*******************************************************************************/ + /* Check if Inductive Amplitude is to be performed */ + if( gRFAL.wum.cfg.indAmp.enabled ) + { + aux = (uint8_t)((gRFAL.wum.cfg.indAmp.delta) << ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_d); + aux |= (uint8_t)(gRFAL.wum.cfg.indAmp.aaInclMeas ? ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aam : 0x00U); + aux |= (uint8_t)(((uint8_t)gRFAL.wum.cfg.indAmp.aaWeight << ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_aew) & ST25R3911_REG_AMPLITUDE_MEASURE_CONF_mask_am_aew); + aux |= (uint8_t)(gRFAL.wum.cfg.indAmp.autoAvg ? ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_ae : 0x00U); + + st25r3911WriteRegister( ST25R3911_REG_AMPLITUDE_MEASURE_CONF, aux ); + + /* Only need to set the reference if not using Auto Average */ + if( !gRFAL.wum.cfg.indAmp.autoAvg ) + { + if( gRFAL.wum.cfg.indAmp.reference == RFAL_WUM_REFERENCE_AUTO ) + { + st25r3911MeasureAmplitude( &gRFAL.wum.cfg.indAmp.reference ); + } + st25r3911WriteRegister( ST25R3911_REG_AMPLITUDE_MEASURE_REF, gRFAL.wum.cfg.indAmp.reference ); + } + + reg |= ST25R3911_REG_WUP_TIMER_CONTROL_wam; + irqs |= ST25R3911_IRQ_MASK_WAM; + } + + /*******************************************************************************/ + /* Check if Inductive Phase is to be performed */ + if( gRFAL.wum.cfg.indPha.enabled ) + { + aux = (uint8_t)((gRFAL.wum.cfg.indPha.delta) << ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_d); + aux |= (uint8_t)(gRFAL.wum.cfg.indPha.aaInclMeas ? ST25R3911_REG_PHASE_MEASURE_CONF_pm_aam : 0x00U); + aux |= (uint8_t)(((uint8_t)gRFAL.wum.cfg.indPha.aaWeight << ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_aew) & ST25R3911_REG_PHASE_MEASURE_CONF_mask_pm_aew); + aux |= (uint8_t)(gRFAL.wum.cfg.indPha.autoAvg ? ST25R3911_REG_PHASE_MEASURE_CONF_pm_ae : 0x00U); + + st25r3911WriteRegister( ST25R3911_REG_PHASE_MEASURE_CONF, aux ); + + /* Only need to set the reference if not using Auto Average */ + if( !gRFAL.wum.cfg.indPha.autoAvg ) + { + if( gRFAL.wum.cfg.indPha.reference == RFAL_WUM_REFERENCE_AUTO ) + { + st25r3911MeasurePhase( &gRFAL.wum.cfg.indPha.reference ); + } + st25r3911WriteRegister( ST25R3911_REG_PHASE_MEASURE_REF, gRFAL.wum.cfg.indPha.reference ); + } + + reg |= ST25R3911_REG_WUP_TIMER_CONTROL_wph; + irqs |= ST25R3911_IRQ_MASK_WPH; + } + + /*******************************************************************************/ + /* Check if Capacitive is to be performed */ + if( gRFAL.wum.cfg.cap.enabled ) + { + /*******************************************************************************/ + /* Perform Capacitive sensor calibration */ + + /* Disable Oscillator and Field */ + st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, (ST25R3911_REG_OP_CONTROL_en | ST25R3911_REG_OP_CONTROL_tx_en) ); + + /* Sensor gain should be configured on Analog Config */ + + /* Perform calibration procedure */ + st25r3911CalibrateCapacitiveSensor( NULL ); + + + /*******************************************************************************/ + aux = (uint8_t)((gRFAL.wum.cfg.cap.delta) << ST25R3911_REG_CAPACITANCE_MEASURE_CONF_shift_cm_d); + aux |= (uint8_t)(gRFAL.wum.cfg.cap.aaInclMeas ? ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aam : 0x00U); + aux |= (uint8_t)(((uint8_t)gRFAL.wum.cfg.cap.aaWeight << ST25R3911_REG_CAPACITANCE_MEASURE_CONF_shift_cm_aew) & ST25R3911_REG_CAPACITANCE_MEASURE_CONF_mask_cm_aew); + aux |= (uint8_t)(gRFAL.wum.cfg.cap.autoAvg ? ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_ae : 0x00U); + + st25r3911WriteRegister( ST25R3911_REG_CAPACITANCE_MEASURE_CONF, aux ); + + /* Only need to set the reference if not using Auto Average */ + if( !gRFAL.wum.cfg.cap.autoAvg ) + { + if( gRFAL.wum.cfg.indPha.reference == RFAL_WUM_REFERENCE_AUTO ) + { + st25r3911MeasureCapacitance( &gRFAL.wum.cfg.cap.reference ); + } + st25r3911WriteRegister( ST25R3911_REG_CAPACITANCE_MEASURE_REF, gRFAL.wum.cfg.cap.reference ); + } + + reg |= ST25R3911_REG_WUP_TIMER_CONTROL_wcap; + irqs |= ST25R3911_IRQ_MASK_WCAP; + } + + /* Disable and clear all interrupts except Wake-Up IRQs */ + st25r3911DisableInterrupts( ST25R3911_IRQ_MASK_ALL ); + st25r3911GetInterrupt( irqs ); + st25r3911EnableInterrupts( irqs ); + + /* Enable Low Power Wake-Up Mode */ + st25r3911WriteRegister( ST25R3911_REG_WUP_TIMER_CONTROL, reg ); + st25r3911ChangeRegisterBits( ST25R3911_REG_OP_CONTROL, (ST25R3911_REG_OP_CONTROL_en | ST25R3911_REG_OP_CONTROL_wu), ST25R3911_REG_OP_CONTROL_wu ); + + gRFAL.wum.state = RFAL_WUM_STATE_ENABLED; + gRFAL.state = RFAL_STATE_WUM; + + return ERR_NONE; +} + + +/*******************************************************************************/ +bool rfalWakeUpModeHasWoke( void ) +{ + return (gRFAL.wum.state >= RFAL_WUM_STATE_ENABLED_WOKE); +} + + +/*******************************************************************************/ +static void rfalRunWakeUpModeWorker( void ) +{ + uint32_t irqs; + + if( gRFAL.state != RFAL_STATE_WUM ) + { + return; + } + + switch( gRFAL.wum.state ) + { + case RFAL_WUM_STATE_ENABLED: + case RFAL_WUM_STATE_ENABLED_WOKE: + + irqs = st25r3911GetInterrupt( ( ST25R3911_IRQ_MASK_WT | ST25R3911_IRQ_MASK_WAM | ST25R3911_IRQ_MASK_WPH | ST25R3911_IRQ_MASK_WCAP ) ); + if( irqs == ST25R3911_IRQ_MASK_NONE ) + { + break; /* No interrupt to process */ + } + + /*******************************************************************************/ + /* Check and mark which measurement(s) cause interrupt */ + if((irqs & ST25R3911_IRQ_MASK_WAM) != 0U) + { + gRFAL.wum.state = RFAL_WUM_STATE_ENABLED_WOKE; + } + + if((irqs & ST25R3911_IRQ_MASK_WPH) != 0U) + { + gRFAL.wum.state = RFAL_WUM_STATE_ENABLED_WOKE; + } + + if((irqs & ST25R3911_IRQ_MASK_WCAP) != 0U) + { + gRFAL.wum.state = RFAL_WUM_STATE_ENABLED_WOKE; + } + break; + + default: + /* MISRA 16.4: no empty default statement (a comment being enough) */ + break; + } +} + + +/*******************************************************************************/ +ReturnCode rfalWakeUpModeStop( void ) +{ + if( gRFAL.wum.state == RFAL_WUM_STATE_NOT_INIT ) + { + return ERR_WRONG_STATE; + } + + gRFAL.wum.state = RFAL_WUM_STATE_NOT_INIT; + + /* Re-Enable External Field Detector */ + st25r3911SetRegisterBits( ST25R3911_REG_AUX, ST25R3911_REG_AUX_en_fd ); + + /* Disable Wake-Up Mode */ + st25r3911ClrRegisterBits( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_wu ); + st25r3911DisableInterrupts( (ST25R3911_IRQ_MASK_WT | ST25R3911_IRQ_MASK_WAM | ST25R3911_IRQ_MASK_WPH | ST25R3911_IRQ_MASK_WCAP) ); + + /* Re-Enable the Oscillator */ + st25r3911OscOn(); + + /* Set Analog configurations for Wake-up Off event */ + rfalSetAnalogConfig( (RFAL_ANALOG_CONFIG_TECH_CHIP | RFAL_ANALOG_CONFIG_CHIP_WAKEUP_OFF) ); + + return ERR_NONE; +} + +#endif /* RFAL_FEATURE_WAKEUP_MODE */ + + +/******************************************************************************* + * RF Chip * + *******************************************************************************/ + +/*******************************************************************************/ +ReturnCode rfalChipWriteReg( uint16_t reg, const uint8_t* values, uint8_t len ) +{ + if( !st25r3911IsRegValid( (uint8_t)reg) ) + { + return ERR_PARAM; + } + + st25r3911WriteMultipleRegisters( (uint8_t)reg, values, len ); + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipReadReg( uint16_t reg, uint8_t* values, uint8_t len ) +{ + if( !st25r3911IsRegValid( (uint8_t)reg) ) + { + return ERR_PARAM; + } + + st25r3911ReadMultipleRegisters( (uint8_t)reg, values, len ); + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipExecCmd( uint16_t cmd ) +{ + if( !st25r3911IsCmdValid( (uint8_t)cmd) ) + { + return ERR_PARAM; + } + + st25r3911ExecuteCommand( (uint8_t) cmd ); + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipWriteTestReg( uint16_t reg, uint8_t value ) +{ + st25r3911WriteTestRegister( (uint8_t)reg, value ); + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipReadTestReg( uint16_t reg, uint8_t* value ) +{ + st25r3911ReadTestRegister( (uint8_t)reg, value ); + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipChangeRegBits( uint16_t reg, uint8_t valueMask, uint8_t value ) +{ + st25r3911ChangeRegisterBits( (uint8_t)reg, valueMask, value ); + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipChangeTestRegBits( uint16_t reg, uint8_t valueMask, uint8_t value ) +{ + st25r3911ChangeTestRegisterBits( (uint8_t)reg, valueMask, value ); + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipSetRFO( uint8_t rfo ) +{ + st25r3911WriteRegister( ST25R3911_REG_RFO_AM_OFF_LEVEL, rfo ); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipGetRFO( uint8_t* result ) +{ + st25r3911ReadRegister(ST25R3911_REG_RFO_AM_ON_LEVEL, result); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipMeasureAmplitude( uint8_t* result ) +{ + st25r3911MeasureAmplitude( result ); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipMeasurePhase( uint8_t* result ) +{ + st25r3911MeasurePhase( result ); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipMeasureCapacitance( uint8_t* result ) +{ + st25r3911MeasureCapacitance( result ); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalChipMeasurePowerSupply( uint8_t param, uint8_t* result ) +{ + *result = st25r3911MeasurePowerSupply( param ); + + return ERR_NONE; +} + + + +/*******************************************************************************/ + +/* All bitrates defined in ST25R3911B registers are nibbles. This rfal code + * up there only works if equality to values of enum rfalBitrate is guaranteed: */ +extern uint8_t equalityGuard_RFAL_BR_106[(ST25R3911_REG_BIT_RATE_rxrate_106==(uint8_t)RFAL_BR_106)?1:(-1)]; +extern uint8_t equalityGuard_RFAL_BR_212[(ST25R3911_REG_BIT_RATE_rxrate_212==(uint8_t)RFAL_BR_212)?1:(-1)]; +extern uint8_t equalityGuard_RFAL_BR_424[(ST25R3911_REG_BIT_RATE_rxrate_424==(uint8_t)RFAL_BR_424)?1:(-1)]; +extern uint8_t equalityGuard_RFAL_BR_848[(ST25R3911_REG_BIT_RATE_rxrate_848==(uint8_t)RFAL_BR_848)?1:(-1)]; +extern uint8_t equalityGuard_RFAL_BR_1695[(ST25R3911_REG_BIT_RATE_rxrate_1695==(uint8_t)RFAL_BR_1695)?1:(-1)]; +extern uint8_t equalityGuard_RFAL_BR_3390[(ST25R3911_REG_BIT_RATE_rxrate_3390==(uint8_t)RFAL_BR_3390)?1:(-1)]; +extern uint8_t equalityGuard_RFAL_BR_6780[(ST25R3911_REG_BIT_RATE_rxrate_6780==(uint8_t)RFAL_BR_6780)?1:(-1)]; diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_st25tb.c b/Software/fab-reader2-c/components/rfal/Src/rfal_st25tb.c new file mode 100644 index 0000000..41c9430 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_st25tb.c @@ -0,0 +1,551 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_st25tb.c + * + * \author Gustavo Patricio + * + * \brief Implementation of ST25TB interface + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_st25tb.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ +#ifndef RFAL_FEATURE_ST25TB + #define RFAL_FEATURE_ST25TB false /* ST25TB module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_ST25TB + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_ST25TB_CMD_LEN 1U /*!< ST25TB length of a command */ +#define RFAL_ST25TB_SLOTS 16U /*!< ST25TB number of slots */ +#define RFAL_ST25TB_SLOTNUM_MASK 0x0FU /*!< ST25TB Slot Number bit mask on SlotMarker */ +#define RFAL_ST25TB_SLOTNUM_SHIFT 4U /*!< ST25TB Slot Number shift on SlotMarker */ + +#define RFAL_ST25TB_INITIATE_CMD1 0x06U /*!< ST25TB Initiate command byte1 */ +#define RFAL_ST25TB_INITIATE_CMD2 0x00U /*!< ST25TB Initiate command byte2 */ +#define RFAL_ST25TB_PCALL_CMD1 0x06U /*!< ST25TB Pcall16 command byte1 */ +#define RFAL_ST25TB_PCALL_CMD2 0x04U /*!< ST25TB Pcall16 command byte2 */ +#define RFAL_ST25TB_SELECT_CMD 0x0EU /*!< ST25TB Select command */ +#define RFAL_ST25TB_GET_UID_CMD 0x0BU /*!< ST25TB Get UID command */ +#define RFAL_ST25TB_COMPLETION_CMD 0x0FU /*!< ST25TB Completion command */ +#define RFAL_ST25TB_RESET_INV_CMD 0x0CU /*!< ST25TB Reset to Inventory command */ +#define RFAL_ST25TB_READ_BLOCK_CMD 0x08U /*!< ST25TB Read Block command */ +#define RFAL_ST25TB_WRITE_BLOCK_CMD 0x09U /*!< ST25TB Write Block command */ + + +#define RFAL_ST25TB_T0 2157U /*!< ST25TB t0 159 us ST25TB RF characteristics */ +#define RFAL_ST25TB_T1 2048U /*!< ST25TB t1 151 us ST25TB RF characteristics */ + +#define RFAL_ST25TB_FWT (RFAL_ST25TB_T0 + RFAL_ST25TB_T1) /*!< ST25TB FWT = T0 + T1 */ +#define RFAL_ST25TB_TW rfalConvMsTo1fc(7U) /*!< ST25TB TW : Programming time for write max 7ms */ + + +/* + ****************************************************************************** + * GLOBAL MACROS + ****************************************************************************** + */ + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! Initiate Request */ +typedef struct +{ + uint8_t cmd1; /*!< Initiate Request cmd1: 0x06 */ + uint8_t cmd2; /*!< Initiate Request cmd2: 0x00 */ +} rfalSt25tbInitiateReq; + +/*! Pcall16 Request */ +typedef struct +{ + uint8_t cmd1; /*!< Pcal16 Request cmd1: 0x06 */ + uint8_t cmd2; /*!< Pcal16 Request cmd2: 0x04 */ +} rfalSt25tbPcallReq; + + +/*! Select Request */ +typedef struct +{ + uint8_t cmd; /*!< Select Request cmd: 0x0E */ + uint8_t chipId; /*!< Chip ID */ +} rfalSt25tbSelectReq; + +/*! Read Block Request */ +typedef struct +{ + uint8_t cmd; /*!< Select Request cmd: 0x08 */ + uint8_t address; /*!< Block address */ +} rfalSt25tbReadBlockReq; + +/*! Write Block Request */ +typedef struct +{ + uint8_t cmd; /*!< Select Request cmd: 0x09 */ + uint8_t address; /*!< Block address */ + rfalSt25tbBlock data; /*!< Block Data */ +} rfalSt25tbWriteBlockReq; + + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +/*! + ***************************************************************************** + * \brief ST25TB Poller Do Collision Resolution + * + * This method performs ST25TB Collision resolution loop for each slot + * + * \param[in] devLimit : device limit value, and size st25tbDevList + * \param[out] st25tbDevList : ST35TB listener device info + * \param[out] devCnt : Devices found counter + * + * \return colPending : true if a collision was detected + ***************************************************************************** + */ +static bool rfalSt25tbPollerDoCollisionResolution( uint8_t devLimit, rfalSt25tbListenDevice *st25tbDevList, uint8_t *devCnt ); + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + + +static bool rfalSt25tbPollerDoCollisionResolution( uint8_t devLimit, rfalSt25tbListenDevice *st25tbDevList, uint8_t *devCnt ) +{ + uint8_t i; + uint8_t chipId; + ReturnCode ret; + bool col; + + col = false; + + for(i = 0; i < RFAL_ST25TB_SLOTS; i++) + { + platformDelay(1); /* Wait t2: Answer to new request delay */ + + if( i==0U ) + { + /* Step 2: Send Pcall16 */ + ret = rfalSt25tbPollerPcall( &chipId ); + } + else + { + /* Step 3-17: Send Pcall16 */ + ret = rfalSt25tbPollerSlotMarker( i, &chipId ); + } + + if( ret == ERR_NONE ) + { + /* Found another device */ + st25tbDevList[*devCnt].chipID = chipId; + st25tbDevList[*devCnt].isDeselected = false; + + /* Select Device, retrieve its UID */ + ret = rfalSt25tbPollerSelect( chipId ); + + /* By Selecting this device, the previous gets Deselected */ + if( (*devCnt) > 0U ) + { + st25tbDevList[(*devCnt)-1U].isDeselected = true; + } + + if( ERR_NONE == ret ) + { + rfalSt25tbPollerGetUID( &st25tbDevList[*devCnt].UID ); + } + + if( ERR_NONE == ret ) + { + (*devCnt)++; + } + } + else if( (ret == ERR_CRC) || (ret == ERR_FRAMING) ) + { + col = true; + } + else + { + /* MISRA 15.7 - Empty else */ + } + + if( *devCnt >= devLimit ) + { + break; + } + } + return col; +} + + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerInitialize( void ) +{ + return rfalNfcbPollerInitialize(); +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerCheckPresence( uint8_t *chipId ) +{ + ReturnCode ret; + uint8_t chipIdRes; + + chipIdRes = 0x00; + + /* Send Initiate Request */ + ret = rfalSt25tbPollerInitiate( &chipIdRes ); + + /* Check if a transmission error was detected */ + if( (ret == ERR_CRC) || (ret == ERR_FRAMING) ) + { + return ERR_NONE; + } + + /* Copy chip ID if requested */ + if( chipId != NULL ) + { + *chipId = chipIdRes; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerInitiate( uint8_t *chipId ) +{ + ReturnCode ret; + uint16_t rxLen; + rfalSt25tbInitiateReq initiateReq; + uint8_t rxBuf[RFAL_ST25TB_CHIP_ID_LEN + RFAL_ST25TB_CRC_LEN]; /* In case we receive less data that CRC, RF layer will not remove the CRC from buffer */ + + /* Compute Initiate Request */ + initiateReq.cmd1 = RFAL_ST25TB_INITIATE_CMD1; + initiateReq.cmd2 = RFAL_ST25TB_INITIATE_CMD2; + + /* Send Initiate Request */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&initiateReq, sizeof(rfalSt25tbInitiateReq), (uint8_t*)rxBuf, sizeof(rxBuf), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ST25TB_FWT ); + + /* Check for valid Select Response */ + if( (ret == ERR_NONE) && (rxLen != RFAL_ST25TB_CHIP_ID_LEN) ) + { + return ERR_PROTO; + } + + /* Copy chip ID if requested */ + if( chipId != NULL ) + { + *chipId = *rxBuf; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerPcall( uint8_t *chipId ) +{ + ReturnCode ret; + uint16_t rxLen; + rfalSt25tbPcallReq pcallReq; + + /* Compute Pcal16 Request */ + pcallReq.cmd1 = RFAL_ST25TB_PCALL_CMD1; + pcallReq.cmd2 = RFAL_ST25TB_PCALL_CMD2; + + /* Send Pcal16 Request */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&pcallReq, sizeof(rfalSt25tbPcallReq), (uint8_t*)chipId, RFAL_ST25TB_CHIP_ID_LEN, &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ST25TB_FWT ); + + /* Check for valid Select Response */ + if( (ret == ERR_NONE) && (rxLen != RFAL_ST25TB_CHIP_ID_LEN) ) + { + return ERR_PROTO; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerSlotMarker( uint8_t slotNum, uint8_t *chipIdRes ) +{ + ReturnCode ret; + uint16_t rxLen; + uint8_t slotMarker; + + if( (slotNum == 0U) || (slotNum > 15U) ) + { + return ERR_PARAM; + } + + /* Compute SlotMarker */ + slotMarker = ( ((slotNum & RFAL_ST25TB_SLOTNUM_MASK) << RFAL_ST25TB_SLOTNUM_SHIFT) | RFAL_ST25TB_PCALL_CMD1 ); + + + /* Send SlotMarker */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&slotMarker, RFAL_ST25TB_CMD_LEN, (uint8_t*)chipIdRes, RFAL_ST25TB_CHIP_ID_LEN, &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ST25TB_FWT ); + + /* Check for valid ChipID Response */ + if( (ret == ERR_NONE) && (rxLen != RFAL_ST25TB_CHIP_ID_LEN) ) + { + return ERR_PROTO; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerSelect( uint8_t chipId ) +{ + ReturnCode ret; + uint16_t rxLen; + rfalSt25tbSelectReq selectReq; + uint8_t chipIdRes; + + /* Compute Select Request */ + selectReq.cmd = RFAL_ST25TB_SELECT_CMD; + selectReq.chipId = chipId; + + /* Send Select Request */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&selectReq, sizeof(rfalSt25tbSelectReq), (uint8_t*)&chipIdRes, RFAL_ST25TB_CHIP_ID_LEN, &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ST25TB_FWT ); + + /* Check for valid Select Response */ + if( (ret == ERR_NONE) && ((rxLen != RFAL_ST25TB_CHIP_ID_LEN) || (chipIdRes != chipId)) ) + { + return ERR_PROTO; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerGetUID( rfalSt25tbUID *UID ) +{ + ReturnCode ret; + uint16_t rxLen; + uint8_t getUidReq; + + + /* Compute Get UID Request */ + getUidReq = RFAL_ST25TB_GET_UID_CMD; + + /* Send Select Request */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&getUidReq, RFAL_ST25TB_CMD_LEN, (uint8_t*)UID, sizeof(rfalSt25tbUID), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ST25TB_FWT ); + + /* Check for valid UID Response */ + if( (ret == ERR_NONE) && (rxLen != RFAL_ST25TB_UID_LEN) ) + { + return ERR_PROTO; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerCollisionResolution( uint8_t devLimit, rfalSt25tbListenDevice *st25tbDevList, uint8_t *devCnt ) +{ + + uint8_t chipId; + ReturnCode ret; + bool detected; /* collision or device was detected */ + + if( (st25tbDevList == NULL) || (devCnt == NULL) || (devLimit == 0U) ) + { + return ERR_PARAM; + } + + *devCnt = 0; + + /* Step 1: Send Initiate */ + ret = rfalSt25tbPollerInitiate( &chipId ); + if( ret == ERR_NONE ) + { + /* If only 1 answer is detected */ + st25tbDevList[*devCnt].chipID = chipId; + st25tbDevList[*devCnt].isDeselected = false; + + /* Retrieve its UID and keep it Selected*/ + ret = rfalSt25tbPollerSelect( chipId ); + + if( ERR_NONE == ret ) + { + ret = rfalSt25tbPollerGetUID( &st25tbDevList[*devCnt].UID ); + } + + if( ERR_NONE == ret ) + { + (*devCnt)++; + } + } + /* Always proceed to Pcall16 anticollision as phase differences of tags can lead to no tag recognized, even if there is one */ + if( *devCnt < devLimit ) + { + /* Multiple device responses */ + do + { + detected = rfalSt25tbPollerDoCollisionResolution( devLimit, st25tbDevList, devCnt ); + } + while( (detected == true) && (*devCnt < devLimit) ); + } + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerReadBlock( uint8_t blockAddress, rfalSt25tbBlock *blockData ) +{ + ReturnCode ret; + uint16_t rxLen; + rfalSt25tbReadBlockReq readBlockReq; + + + /* Compute Read Block Request */ + readBlockReq.cmd = RFAL_ST25TB_READ_BLOCK_CMD; + readBlockReq.address = blockAddress; + + /* Send Read Block Request */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&readBlockReq, sizeof(rfalSt25tbReadBlockReq), (uint8_t*)blockData, sizeof(rfalSt25tbBlock), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ST25TB_FWT ); + + /* Check for valid UID Response */ + if( (ret == ERR_NONE) && (rxLen != RFAL_ST25TB_BLOCK_LEN) ) + { + return ERR_PROTO; + } + + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerWriteBlock( uint8_t blockAddress, const rfalSt25tbBlock *blockData ) +{ + ReturnCode ret; + uint16_t rxLen; + rfalSt25tbWriteBlockReq writeBlockReq; + rfalSt25tbBlock tmpBlockData; + + + /* Compute Write Block Request */ + writeBlockReq.cmd = RFAL_ST25TB_WRITE_BLOCK_CMD; + writeBlockReq.address = blockAddress; + ST_MEMCPY( &writeBlockReq.data, blockData, RFAL_ST25TB_BLOCK_LEN ); + + /* Send Write Block Request */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&writeBlockReq, sizeof(rfalSt25tbWriteBlockReq), tmpBlockData, RFAL_ST25TB_BLOCK_LEN, &rxLen, RFAL_TXRX_FLAGS_DEFAULT, (RFAL_ST25TB_FWT + RFAL_ST25TB_TW) ); + + /* Check if an unexpected answer was received */ + if( ret == ERR_NONE ) + { + return ERR_PROTO; + } + /* Check there was any error besides Timeout*/ + if( ret != ERR_TIMEOUT ) + { + return ret; + } + + ret = rfalSt25tbPollerReadBlock(blockAddress, &tmpBlockData); + if( ret == ERR_NONE ) + { + if( ST_BYTECMP( &tmpBlockData, blockData, RFAL_ST25TB_BLOCK_LEN ) == 0 ) + { + return ERR_NONE; + } + return ERR_PROTO; + } + return ret; +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerCompletion( void ) +{ + uint8_t completionReq; + + /* Compute Completion Request */ + completionReq = RFAL_ST25TB_COMPLETION_CMD; + + /* Send Completion Request, no response is expected */ + return rfalTransceiveBlockingTxRx( (uint8_t*)&completionReq, RFAL_ST25TB_CMD_LEN, NULL, 0, NULL, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ST25TB_FWT ); +} + + +/*******************************************************************************/ +ReturnCode rfalSt25tbPollerResetToInventory( void ) +{ + uint8_t resetInvReq; + + /* Compute Completion Request */ + resetInvReq = RFAL_ST25TB_RESET_INV_CMD; + + /* Send Completion Request, no response is expected */ + return rfalTransceiveBlockingTxRx( (uint8_t*)&resetInvReq, RFAL_ST25TB_CMD_LEN, NULL, 0, NULL, RFAL_TXRX_FLAGS_DEFAULT, RFAL_ST25TB_FWT ); +} + +#endif /* RFAL_FEATURE_ST25TB */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_st25xv.c b/Software/fab-reader2-c/components/rfal/Src/rfal_st25xv.c new file mode 100644 index 0000000..c835004 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_st25xv.c @@ -0,0 +1,528 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_st25xv.c + * + * \author Gustavo Patricio + * + * \brief NFC-V ST25 NFC-V Tag specific features + * + * This module provides support for ST's specific features available on + * NFC-V (ISO15693) tag families: ST25D, ST25TV, M24LR + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_st25xv.h" +#include "rfal_nfcv.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_ST25xV + #define RFAL_FEATURE_ST25xV false /* ST25xV module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_ST25xV + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_ST25xV_READ_CONFIG_LEN 2U /*!< READ CONFIGURATION length */ +#define RFAL_ST25xV_READ_MSG_LEN_LEN 2U /*!< READ MESSAGE LENGTH length */ +#define RFAL_ST25xV_CONF_POINTER_LEN 1U /*!< READ/WRITE CONFIGURATION Pointer length */ +#define RFAL_ST25xV_CONF_REGISTER_LEN 1U /*!< READ/WRITE CONFIGURATION Register length */ +#define RFAL_ST25xV_PWDNUM_LEN 1U /*!< Password Number length */ +#define RFAL_ST25xV_PWD_LEN 8U /*!< Password length */ +#define RFAL_ST25xV_MBPOINTER_LEN 1U /*!< Read Message MBPointer length */ +#define RFAL_ST25xV_NUMBYTES_LEN 1U /*!< Read Message Number of Bytes length */ + +#define RFAL_ST25TV02K_TBOOT_RF 1U /*!< RF Boot time (Minimum time from carrier generation to first data) */ +#define RFAL_ST25TV02K_TRF_OFF 2U /*!< RF OFF time */ + +#define RFAL_FDT_POLL_MAX rfalConvMsTo1fc(20) /*!< Maximum Wait time FDTV,EOF 20 ms Digital 2.0 B.5 */ +#define RFAL_NFCV_FLAG_POS 0U /*!< Flag byte position */ +#define RFAL_NFCV_FLAG_LEN 1U /*!< Flag byte length */ + + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +static ReturnCode rfalST25xVPollerGenericReadConfiguration(uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t* regValue ); +static ReturnCode rfalST25xVPollerGenericWriteConfiguration( uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t regValue ); +static ReturnCode rfalST25xVPollerGenericReadMessageLength( uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t* msgLen ); +static ReturnCode rfalST25xVPollerGenericReadMessage( uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t mbPointer, uint8_t numBytes, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ); +static ReturnCode rfalST25xVPollerGenericWriteMessage( uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t msgLen, const uint8_t* msgData, uint8_t* txBuf, uint16_t txBufLen ); +/* +****************************************************************************** +* LOCAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +static ReturnCode rfalST25xVPollerGenericReadConfiguration(uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t* regValue ) +{ + ReturnCode ret; + uint8_t p; + uint16_t rcvLen; + rfalNfcvGenericRes res; + + if( regValue == NULL ) + { + return ERR_PARAM; + } + + p = pointer; + + ret = rfalNfcvPollerTransceiveReq( cmd, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, &p, sizeof(uint8_t), (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); + if( ret == ERR_NONE ) + { + if( rcvLen < RFAL_ST25xV_READ_CONFIG_LEN ) + { + ret = ERR_PROTO; + } + else + { + *regValue = res.data[0]; + } + } + return ret; +} + +/*******************************************************************************/ +static ReturnCode rfalST25xVPollerGenericWriteConfiguration( uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t regValue ) +{ + uint8_t data[RFAL_ST25xV_CONF_POINTER_LEN + RFAL_ST25xV_CONF_REGISTER_LEN]; + uint8_t dataLen; + uint16_t rcvLen; + rfalNfcvGenericRes res; + + dataLen = 0U; + + data[dataLen++] = pointer; + data[dataLen++] = regValue; + + return rfalNfcvPollerTransceiveReq( cmd, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, data, dataLen, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); + +} + +/*******************************************************************************/ +static ReturnCode rfalST25xVPollerGenericReadMessageLength( uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t* msgLen ) +{ + ReturnCode ret; + uint16_t rcvLen; + rfalNfcvGenericRes res; + + if( msgLen == NULL ) + { + return ERR_PARAM; + } + + ret = rfalNfcvPollerTransceiveReq( cmd, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, NULL, 0, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); + if( ret == ERR_NONE ) + { + if( rcvLen < RFAL_ST25xV_READ_MSG_LEN_LEN ) + { + ret = ERR_PROTO; + } + else + { + *msgLen = res.data[0]; + } + } + return ret; +} + +/*******************************************************************************/ +static ReturnCode rfalST25xVPollerGenericReadMessage( uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t mbPointer, uint8_t numBytes, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[RFAL_ST25xV_MBPOINTER_LEN + RFAL_ST25xV_NUMBYTES_LEN]; + uint8_t dataLen; + + dataLen = 0; + + /* Compute Request Data */ + data[dataLen++] = mbPointer; + data[dataLen++] = numBytes; + + return rfalNfcvPollerTransceiveReq( cmd, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +static ReturnCode rfalST25xVPollerGenericWriteMessage( uint8_t cmd, uint8_t flags, const uint8_t* uid, uint8_t msgLen, const uint8_t* msgData, uint8_t* txBuf, uint16_t txBufLen ) +{ + ReturnCode ret; + uint8_t reqFlag; + uint16_t msgIt; + rfalBitRate rxBR; + bool fastMode; + rfalNfcvGenericRes res; + uint16_t rcvLen; + + /* Calculate required Tx buf length: Mfg Code UID MSGLen MSGLen+1 */ + msgIt = (uint16_t)( msgLen + sizeof(flags) + sizeof(cmd) + 1U + ((uid != NULL) ? RFAL_NFCV_UID_LEN : 0U) + 1U + 1U ); + + /* Check for valid parameters */ + if( (txBuf == NULL) || (msgData == NULL) || (msgLen == 0U) || (msgLen == 0xFFU) || (txBufLen < msgIt) ) + { + return ERR_PARAM; + } + + msgIt = 0; + fastMode = false; + + /* Check if the command is an ST's Fast command */ + if( cmd == (uint8_t)RFAL_NFCV_CMD_FAST_WRITE_MESSAGE ) + { + /* Store current Rx bit rate and move to fast mode */ + rfalGetBitRate( NULL, &rxBR ); + rfalSetBitRate( RFAL_BR_KEEP, RFAL_BR_52p97 ); + + fastMode = true; + } + + /* Compute Request Command */ + reqFlag = (uint8_t)(flags & (~((uint32_t)RFAL_NFCV_REQ_FLAG_ADDRESS) & ~((uint32_t)RFAL_NFCV_REQ_FLAG_SELECT))); + reqFlag |= (( uid != NULL ) ? (uint8_t)RFAL_NFCV_REQ_FLAG_ADDRESS : (uint8_t)RFAL_NFCV_REQ_FLAG_SELECT); + + txBuf[msgIt++] = reqFlag; + txBuf[msgIt++] = cmd; + txBuf[msgIt++] = RFAL_NFCV_ST_IC_MFG_CODE; + + if( uid != NULL ) + { + ST_MEMCPY( &txBuf[msgIt], uid, RFAL_NFCV_UID_LEN ); + msgIt += RFAL_NFCV_UID_LEN; + } + txBuf[msgIt++] = msgLen; + ST_MEMCPY( &txBuf[msgIt], msgData, (uint8_t)(msgLen + 1U) ); /* Message Data contains (MSGLength + 1) bytes */ + msgIt += (uint8_t)(msgLen + 1U); + + /* Transceive Command */ + ret = rfalTransceiveBlockingTxRx( txBuf, msgIt, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_MAX ); + + + /* Restore Rx BitRate */ + if( fastMode ) + { + rfalSetBitRate( RFAL_BR_KEEP, rxBR ); + } + + if( ret != ERR_NONE ) + { + return ret; + } + + /* Check if the response minimum length has been received */ + if( rcvLen < (uint8_t)RFAL_NFCV_FLAG_LEN ) + { + return ERR_PROTO; + } + + /* Check if an error has been signalled */ + if( (res.RES_FLAG & (uint8_t)RFAL_NFCV_RES_FLAG_ERROR) != 0U ) + { + return ERR_PROTO; + } + + return ERR_NONE; +} + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerM24LRReadSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[RFAL_NFCV_BLOCKNUM_M24LR_LEN]; + uint8_t dataLen; + + dataLen = 0; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)blockNum; /* Set M24LR Block Number (16 bits) LSB */ + data[dataLen++] = (uint8_t)(blockNum >> 8U); /* Set M24LR Block Number (16 bits) MSB */ + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_READ_SINGLE_BLOCK, (flags | (uint8_t)RFAL_NFCV_REQ_FLAG_PROTOCOL_EXT), RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerM24LRWriteSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, const uint8_t* wrData, uint8_t blockLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_M24LR_LEN + RFAL_NFCV_MAX_BLOCK_LEN)]; + uint8_t dataLen; + uint16_t rcvLen; + rfalNfcvGenericRes res; + + /* Check for valid parameters */ + if( (blockLen == 0U) || (blockLen > (uint8_t)RFAL_NFCV_MAX_BLOCK_LEN) || (wrData == NULL) ) + { + return ERR_PARAM; + } + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)blockNum; /* Set M24LR Block Number (16 bits) LSB */ + data[dataLen++] = (uint8_t)(blockNum >> 8U); /* Set M24LR Block Number (16 bits) MSB */ + ST_MEMCPY( &data[dataLen], wrData, blockLen ); /* Append Block data to write */ + dataLen += blockLen; + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_WRITE_SINGLE_BLOCK, (flags | (uint8_t)RFAL_NFCV_REQ_FLAG_PROTOCOL_EXT), RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerM24LRReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint16_t firstBlockNum, uint8_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_M24LR_LEN + RFAL_NFCV_BLOCKNUM_M24LR_LEN)]; + uint8_t dataLen; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)firstBlockNum; /* Set M24LR Block Number (16 bits) LSB */ + data[dataLen++] = (uint8_t)(firstBlockNum >> 8U); /* Set M24LR Block Number (16 bits) MSB */ + data[dataLen++] = numOfBlocks; /* Set number of blocks to read */ + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_READ_MULTIPLE_BLOCKS, (flags | (uint8_t)RFAL_NFCV_REQ_FLAG_PROTOCOL_EXT), RFAL_NFCV_PARAM_SKIP, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastReadSingleBlock( uint8_t flags, const uint8_t* uid, uint8_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t bn; + + bn = blockNum; + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_FAST_READ_SINGLE_BLOCK, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, &bn, sizeof(uint8_t), rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerM24LRFastReadSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[RFAL_NFCV_BLOCKNUM_M24LR_LEN]; + uint8_t dataLen; + + dataLen = 0; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)blockNum; /* Set M24LR Block Number (16 bits) LSB */ + data[dataLen++] = (uint8_t)(blockNum >> 8U); /* Set M24LR Block Number (16 bits) MSB */ + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_FAST_READ_SINGLE_BLOCK, (flags | (uint8_t)RFAL_NFCV_REQ_FLAG_PROTOCOL_EXT), RFAL_NFCV_ST_IC_MFG_CODE, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerM24LRFastReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint16_t firstBlockNum, uint8_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_M24LR_LEN + RFAL_NFCV_BLOCKNUM_M24LR_LEN)]; + uint8_t dataLen; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)firstBlockNum; /* Set M24LR Block Number (16 bits) LSB */ + data[dataLen++] = (uint8_t)(firstBlockNum >> 8U); /* Set M24LR Block Number (16 bits) MSB */ + data[dataLen++] = numOfBlocks; /* Set number of blocks to read */ + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_FAST_READ_MULTIPLE_BLOCKS, (flags | (uint8_t)RFAL_NFCV_REQ_FLAG_PROTOCOL_EXT), RFAL_NFCV_ST_IC_MFG_CODE, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint8_t firstBlockNum, uint8_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_LEN + RFAL_NFCV_BLOCKNUM_LEN)]; + uint8_t dataLen; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = firstBlockNum; /* Set first Block Number */ + data[dataLen++] = numOfBlocks; /* Set number of blocks to read */ + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_FAST_READ_MULTIPLE_BLOCKS, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastExtendedReadSingleBlock( uint8_t flags, const uint8_t* uid, uint16_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[RFAL_NFCV_BLOCKNUM_EXTENDED_LEN]; + uint8_t dataLen; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)blockNum; /* TS T5T 1.0 BNo is considered as a multi-byte field. TS T5T 1.0 5.1.1.13 multi-byte field follows [DIGITAL]. [DIGITAL] 9.3.1 A multiple byte field is transmitted LSB first. */ + data[dataLen++] = (uint8_t)((blockNum >> 8U) & 0xFFU); + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_FAST_EXTENDED_READ_SINGLE_BLOCK, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastExtReadMultipleBlocks( uint8_t flags, const uint8_t* uid, uint16_t firstBlockNum, uint16_t numOfBlocks, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + uint8_t data[(RFAL_NFCV_BLOCKNUM_EXTENDED_LEN + RFAL_NFCV_BLOCKNUM_EXTENDED_LEN)]; + uint8_t dataLen; + + dataLen = 0U; + + /* Compute Request Data */ + data[dataLen++] = (uint8_t)((firstBlockNum >> 0U) & 0xFFU); + data[dataLen++] = (uint8_t)((firstBlockNum >> 8U) & 0xFFU); + data[dataLen++] = (uint8_t)((numOfBlocks >> 0U) & 0xFFU); + data[dataLen++] = (uint8_t)((numOfBlocks >> 8U) & 0xFFU); + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_FAST_EXTENDED_READ_MULTIPLE_BLOCKS, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, data, dataLen, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerReadConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t* regValue ) +{ + return rfalST25xVPollerGenericReadConfiguration(RFAL_NFCV_CMD_READ_CONFIGURATION, flags, uid, pointer, regValue ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerWriteConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t regValue ) +{ + return rfalST25xVPollerGenericWriteConfiguration( RFAL_NFCV_CMD_WRITE_CONFIGURATION, flags, uid, pointer, regValue); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerReadDynamicConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t* regValue ) +{ + return rfalST25xVPollerGenericReadConfiguration(RFAL_NFCV_CMD_READ_DYN_CONFIGURATION, flags, uid, pointer, regValue ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerWriteDynamicConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t regValue ) +{ + return rfalST25xVPollerGenericWriteConfiguration( RFAL_NFCV_CMD_WRITE_DYN_CONFIGURATION, flags, uid, pointer, regValue); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastReadDynamicConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t* regValue ) +{ + return rfalST25xVPollerGenericReadConfiguration(RFAL_NFCV_CMD_FAST_READ_DYN_CONFIGURATION, flags, uid, pointer, regValue ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastWriteDynamicConfiguration( uint8_t flags, const uint8_t* uid, uint8_t pointer, uint8_t regValue ) +{ + return rfalST25xVPollerGenericWriteConfiguration( RFAL_NFCV_CMD_FAST_WRITE_DYN_CONFIGURATION, flags, uid, pointer, regValue); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerPresentPassword( uint8_t flags, const uint8_t* uid, uint8_t pwdNum, const uint8_t *pwd, uint8_t pwdLen) +{ + uint8_t data[RFAL_ST25xV_PWDNUM_LEN + RFAL_ST25xV_PWD_LEN]; + uint8_t dataLen; + uint16_t rcvLen; + rfalNfcvGenericRes res; + + if( (pwdLen > RFAL_ST25xV_PWD_LEN) || (pwd == NULL) ) + { + return ERR_PARAM; + } + + dataLen = 0U; + data[dataLen++] = pwdNum;; + if( pwdLen > 0U ) + { + ST_MEMCPY(&data[dataLen], pwd, pwdLen); + } + dataLen += pwdLen; + + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_PRESENT_PASSWORD, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, data, dataLen, (uint8_t*)&res, sizeof(rfalNfcvGenericRes), &rcvLen ); + +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerGetRandomNumber( uint8_t flags, const uint8_t* uid, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + rfalFieldOff(); + platformDelay(RFAL_ST25TV02K_TRF_OFF); + rfalNfcvPollerInitialize(); + rfalFieldOnAndStartGT(); + platformDelay(RFAL_ST25TV02K_TBOOT_RF); + return rfalNfcvPollerTransceiveReq( RFAL_NFCV_CMD_GET_RANDOM_NUMBER, flags, RFAL_NFCV_ST_IC_MFG_CODE, uid, NULL, 0U, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerWriteMessage( uint8_t flags, const uint8_t* uid, uint8_t msgLen, const uint8_t* msgData, uint8_t* txBuf, uint16_t txBufLen ) +{ + return rfalST25xVPollerGenericWriteMessage( RFAL_NFCV_CMD_WRITE_MESSAGE, flags, uid, msgLen, msgData, txBuf, txBufLen); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastWriteMessage( uint8_t flags, const uint8_t* uid, uint8_t msgLen, const uint8_t* msgData, uint8_t* txBuf, uint16_t txBufLen ) +{ + return rfalST25xVPollerGenericWriteMessage( RFAL_NFCV_CMD_FAST_WRITE_MESSAGE, flags, uid, msgLen, msgData, txBuf, txBufLen); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerReadMessageLength( uint8_t flags, const uint8_t* uid, uint8_t* msgLen ) +{ + return rfalST25xVPollerGenericReadMessageLength(RFAL_NFCV_CMD_READ_MESSAGE_LENGTH, flags, uid, msgLen); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastReadMsgLength( uint8_t flags, const uint8_t* uid, uint8_t* msgLen ) +{ + return rfalST25xVPollerGenericReadMessageLength(RFAL_NFCV_CMD_FAST_READ_MESSAGE_LENGTH, flags, uid, msgLen); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerReadMessage( uint8_t flags, const uint8_t* uid, uint8_t mbPointer, uint8_t numBytes, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + return rfalST25xVPollerGenericReadMessage(RFAL_NFCV_CMD_READ_MESSAGE, flags, uid, mbPointer, numBytes, rxBuf, rxBufLen, rcvLen ); +} + +/*******************************************************************************/ +ReturnCode rfalST25xVPollerFastReadMessage( uint8_t flags, const uint8_t* uid, uint8_t mbPointer, uint8_t numBytes, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) +{ + return rfalST25xVPollerGenericReadMessage(RFAL_NFCV_CMD_FAST_READ_MESSAGE, flags, uid, mbPointer, numBytes, rxBuf, rxBufLen, rcvLen ); +} + +#endif /* RFAL_FEATURE_ST25xV */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_t1t.c b/Software/fab-reader2-c/components/rfal/Src/rfal_t1t.c new file mode 100644 index 0000000..995899c --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_t1t.c @@ -0,0 +1,220 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_t1t.c + * + * \author Gustavo Patricio + * + * \brief Provides NFC-A T1T convenience methods and definitions + * + * This module provides an interface to perform as a NFC-A Reader/Writer + * to handle a Type 1 Tag T1T (Topaz) + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ +#include "rfal_t1t.h" +#include "utils.h" + +/* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_T1T + #define RFAL_FEATURE_T1T false /* T1T module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_T1T + +/* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + +#define RFAL_T1T_DRD_READ (1236U*2U) /*!< DRD for Reads with n=9 => 1236/fc ~= 91 us T1T 1.2 4.4.2 */ +#define RFAL_T1T_DRD_WRITE 36052U /*!< DRD for Write with n=281 => 36052/fc ~= 2659 us T1T 1.2 4.4.2 */ +#define RFAL_T1T_DRD_WRITE_E 70996U /*!< DRD for Write/Erase with n=554 => 70996/fc ~= 5236 us T1T 1.2 4.4.2 */ + +#define RFAL_T1T_RID_RES_HR0_VAL 0x10U /*!< HR0 indicating NDEF support Digital 2.0 (Candidate) 11.6.2.1 */ +#define RFAL_T1T_RID_RES_HR0_MASK 0xF0U /*!< HR0 most significant nibble mask */ + +/* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! NFC-A T1T (Topaz) RID_REQ Digital 1.1 10.6.1 & Table 49 */ +typedef struct +{ + uint8_t cmd; /*!< T1T cmd: RID */ + uint8_t add; /*!< ADD: undefined value */ + uint8_t data; /*!< DATA: undefined value */ + uint8_t uid[RFAL_T1T_UID_LEN]; /*!< UID-echo: undefined value */ +} rfalT1TRidReq; + + +/*! NFC-A T1T (Topaz) RALL_REQ T1T 1.2 Table 4 */ +typedef struct +{ + uint8_t cmd; /*!< T1T cmd: RALL */ + uint8_t add1; /*!< ADD: 0x00 */ + uint8_t add0; /*!< ADD: 0x00 */ + uint8_t uid[RFAL_T1T_UID_LEN]; /*!< UID */ +} rfalT1TRallReq; + + +/*! NFC-A T1T (Topaz) WRITE_REQ T1T 1.2 Table 4 */ +typedef struct +{ + uint8_t cmd; /*!< T1T cmd: RALL */ + uint8_t add; /*!< ADD */ + uint8_t data; /*!< DAT */ + uint8_t uid[RFAL_T1T_UID_LEN]; /*!< UID */ +} rfalT1TWriteReq; + + +/*! NFC-A T1T (Topaz) WRITE_RES T1T 1.2 Table 4 */ +typedef struct +{ + uint8_t add; /*!< ADD */ + uint8_t data; /*!< DAT */ +} rfalT1TWriteRes; + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + +ReturnCode rfalT1TPollerInitialize( void ) +{ + ReturnCode ret; + + EXIT_ON_ERR(ret, rfalSetMode( RFAL_MODE_POLL_NFCA_T1T, RFAL_BR_106, RFAL_BR_106 ) ); + rfalSetErrorHandling( RFAL_ERRORHANDLING_NFC ); + + rfalSetGT( RFAL_GT_NONE ); /* T1T should only be initialized after NFC-A mode, therefore the GT has been fulfilled */ + rfalSetFDTListen( RFAL_FDT_LISTEN_NFCA_POLLER ); /* T1T uses NFC-A FDT Listen with n=9 Digital 1.1 10.7.2 */ + rfalSetFDTPoll( RFAL_FDT_POLL_NFCA_T1T_POLLER ); + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalT1TPollerRid( rfalT1TRidRes *ridRes ) +{ + ReturnCode ret; + rfalT1TRidReq ridReq; + uint16_t rcvdLen; + + if( ridRes == NULL ) + { + return ERR_PARAM; + } + + /* Compute RID command and set Undefined Values to 0x00 Digital 1.1 10.6.1 */ + ST_MEMSET( &ridReq, 0x00, sizeof(rfalT1TRidReq) ); + ridReq.cmd = (uint8_t)RFAL_T1T_CMD_RID; + + EXIT_ON_ERR( ret, rfalTransceiveBlockingTxRx( (uint8_t*)&ridReq, sizeof(rfalT1TRidReq), (uint8_t*)ridRes, sizeof(rfalT1TRidRes), &rcvdLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_T1T_DRD_READ ) ); + + /* Check expected RID response length and the HR0 Digital 2.0 (Candidate) 11.6.2.1 */ + if( (rcvdLen != sizeof(rfalT1TRidRes)) || ((ridRes->hr0 & RFAL_T1T_RID_RES_HR0_MASK) != RFAL_T1T_RID_RES_HR0_VAL) ) + { + return ERR_PROTO; + } + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalT1TPollerRall( const uint8_t* uid, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rxRcvdLen ) +{ + rfalT1TRallReq rallReq; + + if( (rxBuf == NULL) || (uid == NULL) || (rxRcvdLen == NULL) ) + { + return ERR_PARAM; + } + + /* Compute RALL command and set Add to 0x00 */ + ST_MEMSET( &rallReq, 0x00, sizeof(rfalT1TRallReq) ); + rallReq.cmd = (uint8_t)RFAL_T1T_CMD_RALL; + ST_MEMCPY(rallReq.uid, uid, RFAL_T1T_UID_LEN); + + return rfalTransceiveBlockingTxRx( (uint8_t*)&rallReq, sizeof(rfalT1TRallReq), (uint8_t*)rxBuf, rxBufLen, rxRcvdLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_T1T_DRD_READ ); +} + + +/*******************************************************************************/ +ReturnCode rfalT1TPollerWrite( const uint8_t* uid, uint8_t address, uint8_t data ) +{ + rfalT1TWriteReq writeReq; + rfalT1TWriteRes writeRes; + uint16_t rxRcvdLen; + ReturnCode err; + + if( uid == NULL ) + { + return ERR_PARAM; + } + + writeReq.cmd = (uint8_t)RFAL_T1T_CMD_WRITE_E; + writeReq.add = address; + writeReq.data = data; + ST_MEMCPY(writeReq.uid, uid, RFAL_T1T_UID_LEN); + + err = rfalTransceiveBlockingTxRx( (uint8_t*)&writeReq, sizeof(rfalT1TWriteReq), (uint8_t*)&writeRes, sizeof(rfalT1TWriteRes), &rxRcvdLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_T1T_DRD_WRITE_E ); + + if( err == ERR_NONE ) + { + if( (writeReq.add != writeRes.add) || (writeReq.data != writeRes.data) || (rxRcvdLen != sizeof(rfalT1TWriteRes)) ) + { + return ERR_PROTO; + } + } + return err; +} + +#endif /* RFAL_FEATURE_T1T */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_t2t.c b/Software/fab-reader2-c/components/rfal/Src/rfal_t2t.c new file mode 100644 index 0000000..de80a81 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_t2t.c @@ -0,0 +1,242 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2018 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_t2t.c + * + * \author + * + * \brief Provides NFC-A T2T convenience methods and definitions + * + * This module provides an interface to perform as a NFC-A Reader/Writer + * to handle a Type 2 Tag T2T + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ + #include "rfal_t2t.h" + #include "utils.h" + + /* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_T2T + #define RFAL_FEATURE_T2T false /* T2T module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_T2T + + /* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ + #define RFAL_FDT_POLL_READ_MAX rfalConvMsTo1fc(5U) /*!< Maximum Wait time for Read command as defined in TS T2T 1.0 table 18 */ + #define RFAL_FDT_POLL_WRITE_MAX rfalConvMsTo1fc(10U) /*!< Maximum Wait time for Write command as defined in TS T2T 1.0 table 18 */ + #define RFAL_FDT_POLL_SL_MAX rfalConvMsTo1fc(1U) /*!< Maximum Wait time for Sector Select as defined in TS T2T 1.0 table 18 */ + #define RFAL_T2T_ACK_NACK_LEN 1U /*!< Len of NACK in bytes (4 bits) */ + #define RFAL_T2T_ACK 0x0AU /*!< ACK value */ + #define RFAL_T2T_ACK_MASK 0x0FU /*!< ACK value */ + + + #define RFAL_T2T_SECTOR_SELECT_P1_BYTE2 0xFFU /*!< Sector Select Packet 1 byte 2 */ + #define RFAL_T2T_SECTOR_SELECT_P2_RFU_LEN 3U /*!< Sector Select RFU length */ + + + + /* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + +/*! NFC-A T2T command set T2T 1.0 5.1 */ +typedef enum +{ + RFAL_T2T_CMD_READ = 0x30, /*!< T2T Read */ + RFAL_T2T_CMD_WRITE = 0xA2, /*!< T2T Write */ + RFAL_T2T_CMD_SECTOR_SELECT = 0xC2 /*!< T2T Sector Select */ +} rfalT2Tcmds; + + + /*! NFC-A T2T READ T2T 1.0 5.2 and table 11 */ +typedef struct +{ + uint8_t code; /*!< Command code */ + uint8_t blNo; /*!< Block number */ +} rfalT2TReadReq; + + + /*! NFC-A T2T WRITE T2T 1.0 5.3 and table 12 */ +typedef struct +{ + uint8_t code; /*!< Command code */ + uint8_t blNo; /*!< Block number */ + uint8_t data[RFAL_T2T_WRITE_DATA_LEN]; /*!< Data */ +} rfalT2TWriteReq; + + +/*! NFC-A T2T SECTOR SELECT Packet 1 T2T 1.0 5.4 and table 13 */ +typedef struct +{ + uint8_t code; /*!< Command code */ + uint8_t byte2; /*!< Sector Select Packet 1 byte 2 */ +} rfalT2TSectorSelectP1Req; + + +/*! NFC-A T2T SECTOR SELECT Packet 2 T2T 1.0 5.4 and table 13 */ +typedef struct +{ + uint8_t secNo; /*!< Block number */ + uint8_t rfu[RFAL_T2T_SECTOR_SELECT_P2_RFU_LEN]; /*!< Sector Select Packet RFU */ +} rfalT2TSectorSelectP2Req; + + + +/* + ****************************************************************************** + * GLOBAL FUNCTIONS + ****************************************************************************** + */ + + ReturnCode rfalT2TPollerRead( uint8_t blockNum, uint8_t* rxBuf, uint16_t rxBufLen, uint16_t *rcvLen ) + { + ReturnCode ret; + rfalT2TReadReq req; + + if( (rxBuf == NULL) || (rcvLen == NULL) ) + { + return ERR_PARAM; + } + + req.code = (uint8_t)RFAL_T2T_CMD_READ; + req.blNo = blockNum; + + /* Transceive Command */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&req, sizeof(rfalT2TReadReq), rxBuf, rxBufLen, rcvLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_READ_MAX ); + + /* T2T 1.0 5.2.1.7 The Reader/Writer SHALL treat a NACK in response to a READ Command as a Protocol Error */ + if( (ret == ERR_INCOMPLETE_BYTE) && (*rcvLen == RFAL_T2T_ACK_NACK_LEN) && ((*rxBuf & RFAL_T2T_ACK_MASK) != RFAL_T2T_ACK) ) + { + return ERR_PROTO; + } + return ret; + } + + + /*******************************************************************************/ + ReturnCode rfalT2TPollerWrite( uint8_t blockNum, const uint8_t* wrData ) + { + ReturnCode ret; + rfalT2TWriteReq req; + uint8_t res; + uint16_t rxLen; + + req.code = (uint8_t)RFAL_T2T_CMD_WRITE; + req.blNo = blockNum; + ST_MEMCPY(req.data, wrData, RFAL_T2T_WRITE_DATA_LEN); + + + /* Transceive WRITE Command */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&req, sizeof(rfalT2TWriteReq), &res, sizeof(uint8_t), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_READ_MAX ); + + /* Check for a valid ACK */ + if( (ret == ERR_INCOMPLETE_BYTE) || (ret == ERR_NONE) ) + { + ret = ERR_PROTO; + + if( (rxLen == RFAL_T2T_ACK_NACK_LEN) && ((res & RFAL_T2T_ACK_MASK) == RFAL_T2T_ACK) ) + { + ret = ERR_NONE; + } + } + + return ret; + } + + + /*******************************************************************************/ + ReturnCode rfalT2TPollerSectorSelect( uint8_t sectorNum ) + { + rfalT2TSectorSelectP1Req p1Req; + rfalT2TSectorSelectP2Req p2Req; + ReturnCode ret; + uint8_t res; + uint16_t rxLen; + + + /* Compute SECTOR SELECT Packet 1 */ + p1Req.code = (uint8_t)RFAL_T2T_CMD_SECTOR_SELECT; + p1Req.byte2 = RFAL_T2T_SECTOR_SELECT_P1_BYTE2; + + /* Transceive SECTOR SELECT Packet 1 */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&p1Req, sizeof(rfalT2TSectorSelectP1Req), &res, sizeof(uint8_t), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_SL_MAX ); + + /* Check and report any transmission error */ + if( (ret != ERR_INCOMPLETE_BYTE) && (ret != ERR_NONE) ) + { + return ret; + } + + /* Ensure that an ACK was received */ + if( (ret != ERR_INCOMPLETE_BYTE) || (rxLen != RFAL_T2T_ACK_NACK_LEN) || ((res & RFAL_T2T_ACK_MASK) != RFAL_T2T_ACK) ) + { + return ERR_PROTO; + } + + + /* Compute SECTOR SELECT Packet 2 */ + p2Req.secNo = sectorNum; + ST_MEMSET( &p2Req.rfu, 0x00, RFAL_T2T_SECTOR_SELECT_P2_RFU_LEN ); + + + /* Transceive SECTOR SELECT Packet 2 */ + ret = rfalTransceiveBlockingTxRx( (uint8_t*)&p2Req, sizeof(rfalT2TSectorSelectP2Req), &res, sizeof(uint8_t), &rxLen, RFAL_TXRX_FLAGS_DEFAULT, RFAL_FDT_POLL_SL_MAX ); + + /* T2T 1.0 5.4.1.14 The Reader/Writer SHALL treat any response received before the end of PATT2T,SL,MAX as a Protocol Error */ + if( (ret == ERR_NONE) || (ret == ERR_INCOMPLETE_BYTE) ) + { + return ERR_PROTO; + } + + /* T2T 1.0 5.4.1.13 The Reader/Writer SHALL treat the transmission of the SECTOR SELECT Command Packet 2 as being successful when it receives no response until PATT2T,SL,MAX. */ + if( ret == ERR_TIMEOUT ) + { + return ERR_NONE; + } + + return ret; + } + +#endif /* RFAL_FEATURE_T2T */ diff --git a/Software/fab-reader2-c/components/rfal/Src/rfal_t4t.c b/Software/fab-reader2-c/components/rfal/Src/rfal_t4t.c new file mode 100644 index 0000000..3353f91 --- /dev/null +++ b/Software/fab-reader2-c/components/rfal/Src/rfal_t4t.c @@ -0,0 +1,398 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2018 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + +/* + * PROJECT: ST25R391x firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file rfal_t4t.h + * + * \author Gustavo Patricio + * + * \brief Provides convenience methods and definitions for T4T (ISO7816-4) + * + * This module provides an interface to exchange T4T APDUs according to + * NFC Forum T4T and ISO7816-4 + * + * This implementation was based on the following specs: + * - ISO/IEC 7816-4 3rd Edition 2013-04-15 + * - NFC Forum T4T Technical Specification 1.0 2017-08-28 + * + */ + +/* + ****************************************************************************** + * INCLUDES + ****************************************************************************** + */ + #include "rfal_t4t.h" + #include "utils.h" + + /* + ****************************************************************************** + * ENABLE SWITCH + ****************************************************************************** + */ + +#ifndef RFAL_FEATURE_T4T + #define RFAL_FEATURE_T4T false /* T4T module configuration missing. Disabled by default */ +#endif + +#if RFAL_FEATURE_T4T + + /* + ****************************************************************************** + * GLOBAL DEFINES + ****************************************************************************** + */ +#define RFAL_T4T_OFFSET_DO 0x54U /*!< Tag value for offset BER-TLV data object */ +#define RFAL_T4T_LENGTH_DO 0x03U /*!< Len value for offset BER-TLV data object */ +#define RFAL_T4T_DATA_DO 0x53U /*!< Tag value for data BER-TLV data object */ + +#define RFAL_T4T_MAX_LC 255U /*!< Maximum Lc value for short Lc coding */ + /* +****************************************************************************** +* GLOBAL TYPES +****************************************************************************** +*/ + + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ + + +/* + ****************************************************************************** + * LOCAL VARIABLES + ****************************************************************************** + */ + + +/* + ****************************************************************************** + * GLOBAL FUNCTIONS + ****************************************************************************** + */ + +/*******************************************************************************/ +ReturnCode rfalT4TPollerComposeCAPDU( rfalT4tCApduParam *apduParam ) +{ + uint8_t hdrLen; + uint16_t msgIt; + + if( (apduParam == NULL) || (apduParam->cApduBuf == NULL) || (apduParam->cApduLen == NULL) ) + { + return ERR_PARAM; + } + + msgIt = 0; + *(apduParam->cApduLen) = 0; + + /*******************************************************************************/ + /* Compute Command-APDU according to the format T4T 1.0 5.1.2 & ISO7816-4 2013 Table 1 */ + + /* Check if Data is present */ + if( apduParam->LcFlag ) + { + if( apduParam->Lc == 0U ) + { + /* Extented field coding not supported */ + return ERR_PARAM; + } + + /* Check whether requested Lc fits */ + if( (uint16_t)apduParam->Lc > (uint16_t)(RFAL_FEATURE_ISO_DEP_APDU_MAX_LEN - RFAL_T4T_LE_LEN) ) + { + return ERR_PARAM; /* PRQA S 2880 # MISRA 2.1 - Unreachable code due to configuration option being set/unset */ + } + + /* Calculate the header length a place the data/body where it should be */ + hdrLen = RFAL_T4T_MAX_CAPDU_PROLOGUE_LEN + RFAL_T4T_LC_LEN; + + /* make sure not to exceed buffer size */ + if( ((uint16_t)hdrLen + (uint16_t)apduParam->Lc + (apduParam->LeFlag ? RFAL_T4T_LC_LEN : 0U)) > RFAL_FEATURE_ISO_DEP_APDU_MAX_LEN ) + { + return ERR_NOMEM; /* PRQA S 2880 # MISRA 2.1 - Unreachable code due to configuration option being set/unset */ + } + ST_MEMMOVE( &apduParam->cApduBuf->apdu[hdrLen], apduParam->cApduBuf->apdu, apduParam->Lc ); + } + + /* Prepend the ADPDU's header */ + apduParam->cApduBuf->apdu[msgIt++] = apduParam->CLA; + apduParam->cApduBuf->apdu[msgIt++] = apduParam->INS; + apduParam->cApduBuf->apdu[msgIt++] = apduParam->P1; + apduParam->cApduBuf->apdu[msgIt++] = apduParam->P2; + + + /* Check if Data field length is to be added */ + if( apduParam->LcFlag ) + { + apduParam->cApduBuf->apdu[msgIt++] = apduParam->Lc; + msgIt += apduParam->Lc; + } + + /* Check if Expected Response Length is to be added */ + if( apduParam->LeFlag ) + { + apduParam->cApduBuf->apdu[msgIt++] = apduParam->Le; + } + + *(apduParam->cApduLen) = msgIt; + + return ERR_NONE; +} + + +/*******************************************************************************/ +ReturnCode rfalT4TPollerParseRAPDU( rfalT4tRApduParam *apduParam ) +{ + if( (apduParam == NULL) || (apduParam->rApduBuf == NULL) ) + { + return ERR_PARAM; + } + + if( apduParam->rcvdLen < RFAL_T4T_MAX_RAPDU_SW1SW2_LEN ) + { + return ERR_PROTO; + } + + apduParam->rApduBodyLen = (apduParam->rcvdLen - (uint16_t)RFAL_T4T_MAX_RAPDU_SW1SW2_LEN); + apduParam->statusWord = GETU16( &apduParam->rApduBuf->apdu[ apduParam->rApduBodyLen ] ); + + /* Check SW1 SW2 T4T 1.0 5.1.3 NOTE */ + if( apduParam->statusWord == RFAL_T4T_ISO7816_STATUS_COMPLETE ) + { + return ERR_NONE; + } + + return ERR_REQUEST; +} + + +/*******************************************************************************/ +ReturnCode rfalT4TPollerComposeSelectAppl( rfalIsoDepApduBufFormat *cApduBuf, const uint8_t* aid, uint8_t aidLen, uint16_t *cApduLen ) +{ + rfalT4tCApduParam cAPDU; + + /* CLA INS P1 P2 Lc Data Le */ + /* 00h A4h 00h 00h 07h AID 00h */ + cAPDU.CLA = RFAL_T4T_CLA; + cAPDU.INS = (uint8_t)RFAL_T4T_INS_SELECT; + cAPDU.P1 = RFAL_T4T_ISO7816_P1_SELECT_BY_DF_NAME; + cAPDU.P2 = RFAL_T4T_ISO7816_P2_SELECT_FIRST_OR_ONLY_OCCURENCE | RFAL_T4T_ISO7816_P2_SELECT_RETURN_FCI_TEMPLATE; + cAPDU.Lc = aidLen; + cAPDU.Le = 0x00; + cAPDU.LcFlag = true; + cAPDU.LeFlag = true; + cAPDU.cApduBuf = cApduBuf; + cAPDU.cApduLen = cApduLen; + + if( aidLen > 0U ) + { + ST_MEMCPY( cAPDU.cApduBuf->apdu, aid, aidLen ); + } + + return rfalT4TPollerComposeCAPDU( &cAPDU ); +} + + +/*******************************************************************************/ +ReturnCode rfalT4TPollerComposeSelectFile( rfalIsoDepApduBufFormat *cApduBuf, const uint8_t* fid, uint8_t fidLen, uint16_t *cApduLen ) +{ + rfalT4tCApduParam cAPDU; + + /* CLA INS P1 P2 Lc Data Le */ + /* 00h A4h 00h 0Ch 02h FID - */ + cAPDU.CLA = RFAL_T4T_CLA; + cAPDU.INS = (uint8_t)RFAL_T4T_INS_SELECT; + cAPDU.P1 = RFAL_T4T_ISO7816_P1_SELECT_BY_FILEID; + cAPDU.P2 = RFAL_T4T_ISO7816_P2_SELECT_FIRST_OR_ONLY_OCCURENCE | RFAL_T4T_ISO7816_P2_SELECT_NO_RESPONSE_DATA; + cAPDU.Lc = fidLen; + cAPDU.Le = 0x00; + cAPDU.LcFlag = true; + cAPDU.LeFlag = false; + cAPDU.cApduBuf = cApduBuf; + cAPDU.cApduLen = cApduLen; + + if( fidLen > 0U ) + { + ST_MEMCPY( cAPDU.cApduBuf->apdu, fid, fidLen ); + } + + return rfalT4TPollerComposeCAPDU( &cAPDU ); +} + + +/*******************************************************************************/ +ReturnCode rfalT4TPollerComposeSelectFileV1Mapping( rfalIsoDepApduBufFormat *cApduBuf, const uint8_t* fid, uint8_t fidLen, uint16_t *cApduLen ) +{ + rfalT4tCApduParam cAPDU; + + /* CLA INS P1 P2 Lc Data Le */ + /* 00h A4h 00h 00h 02h FID - */ + cAPDU.CLA = RFAL_T4T_CLA; + cAPDU.INS = (uint8_t)RFAL_T4T_INS_SELECT; + cAPDU.P1 = RFAL_T4T_ISO7816_P1_SELECT_BY_FILEID; + cAPDU.P2 = RFAL_T4T_ISO7816_P2_SELECT_FIRST_OR_ONLY_OCCURENCE | RFAL_T4T_ISO7816_P2_SELECT_RETURN_FCI_TEMPLATE; + cAPDU.Lc = fidLen; + cAPDU.Le = 0x00; + cAPDU.LcFlag = true; + cAPDU.LeFlag = false; + cAPDU.cApduBuf = cApduBuf; + cAPDU.cApduLen = cApduLen; + + if( fidLen > 0U ) + { + ST_MEMCPY( cAPDU.cApduBuf->apdu, fid, fidLen ); + } + + return rfalT4TPollerComposeCAPDU( &cAPDU ); +} + + +/*******************************************************************************/ +ReturnCode rfalT4TPollerComposeReadData( rfalIsoDepApduBufFormat *cApduBuf, uint16_t offset, uint8_t expLen, uint16_t *cApduLen ) +{ + rfalT4tCApduParam cAPDU; + + /* CLA INS P1 P2 Lc Data Le */ + /* 00h B0h [Offset] - - len */ + cAPDU.CLA = RFAL_T4T_CLA; + cAPDU.INS = (uint8_t)RFAL_T4T_INS_READBINARY; + cAPDU.P1 = (uint8_t)((offset >> 8U) & 0xFFU); + cAPDU.P2 = (uint8_t)((offset >> 0U) & 0xFFU); + cAPDU.Le = expLen; + cAPDU.LcFlag = false; + cAPDU.LeFlag = true; + cAPDU.cApduBuf = cApduBuf; + cAPDU.cApduLen = cApduLen; + + return rfalT4TPollerComposeCAPDU( &cAPDU ); +} + + +/*******************************************************************************/ +ReturnCode rfalT4TPollerComposeReadDataODO( rfalIsoDepApduBufFormat *cApduBuf, uint32_t offset, uint8_t expLen, uint16_t *cApduLen ) +{ + rfalT4tCApduParam cAPDU; + uint8_t dataIt; + + /* CLA INS P1 P2 Lc Data Le */ + /* 00h B1h 00h 00h Lc 54 03 xxyyzz len */ + /* [Offset] */ + cAPDU.CLA = RFAL_T4T_CLA; + cAPDU.INS = (uint8_t)RFAL_T4T_INS_READBINARY_ODO; + cAPDU.P1 = 0x00U; + cAPDU.P2 = 0x00U; + cAPDU.Le = expLen; + cAPDU.LcFlag = true; + cAPDU.LeFlag = true; + cAPDU.cApduBuf = cApduBuf; + cAPDU.cApduLen = cApduLen; + + dataIt = 0U; + cApduBuf->apdu[dataIt++] = RFAL_T4T_OFFSET_DO; + cApduBuf->apdu[dataIt++] = RFAL_T4T_LENGTH_DO; + cApduBuf->apdu[dataIt++] = (uint8_t)(offset >> 16U); + cApduBuf->apdu[dataIt++] = (uint8_t)(offset >> 8U); + cApduBuf->apdu[dataIt++] = (uint8_t)(offset); + cAPDU.Lc = dataIt; + + return rfalT4TPollerComposeCAPDU( &cAPDU ); +} + + +/*******************************************************************************/ +ReturnCode rfalT4TPollerComposeWriteData( rfalIsoDepApduBufFormat *cApduBuf, uint16_t offset, const uint8_t* data, uint8_t dataLen, uint16_t *cApduLen ) +{ + rfalT4tCApduParam cAPDU; + + + /* CLA INS P1 P2 Lc Data Le */ + /* 00h D6h [Offset] len Data - */ + cAPDU.CLA = RFAL_T4T_CLA; + cAPDU.INS = (uint8_t)RFAL_T4T_INS_UPDATEBINARY; + cAPDU.P1 = (uint8_t)((offset >> 8U) & 0xFFU); + cAPDU.P2 = (uint8_t)((offset >> 0U) & 0xFFU); + cAPDU.Lc = dataLen; + cAPDU.LcFlag = true; + cAPDU.LeFlag = false; + cAPDU.cApduBuf = cApduBuf; + cAPDU.cApduLen = cApduLen; + + if( dataLen > 0U ) + { + ST_MEMCPY( cAPDU.cApduBuf->apdu, data, dataLen ); + } + + return rfalT4TPollerComposeCAPDU( &cAPDU ); +} + +/*******************************************************************************/ +ReturnCode rfalT4TPollerComposeWriteDataODO( rfalIsoDepApduBufFormat *cApduBuf, uint32_t offset, const uint8_t* data, uint8_t dataLen, uint16_t *cApduLen ) +{ + rfalT4tCApduParam cAPDU; + uint8_t dataIt; + + /* CLA INS P1 P2 Lc Data Le */ + /* 00h D7h 00h 00h len 54 03 xxyyzz 53 Ld data - */ + /* [offset] [data] */ + cAPDU.CLA = RFAL_T4T_CLA; + cAPDU.INS = (uint8_t)RFAL_T4T_INS_UPDATEBINARY_ODO; + cAPDU.P1 = 0x00U; + cAPDU.P2 = 0x00U; + cAPDU.LcFlag = true; + cAPDU.LeFlag = false; + cAPDU.cApduBuf = cApduBuf; + cAPDU.cApduLen = cApduLen; + + dataIt = 0U; + cApduBuf->apdu[dataIt++] = RFAL_T4T_OFFSET_DO; + cApduBuf->apdu[dataIt++] = RFAL_T4T_LENGTH_DO; + cApduBuf->apdu[dataIt++] = (uint8_t)(offset >> 16U); + cApduBuf->apdu[dataIt++] = (uint8_t)(offset >> 8U); + cApduBuf->apdu[dataIt++] = (uint8_t)(offset); + cApduBuf->apdu[dataIt++] = RFAL_T4T_DATA_DO; + cApduBuf->apdu[dataIt++] = dataLen; + + if( (((uint32_t)dataLen + (uint32_t)dataIt) >= RFAL_T4T_MAX_LC) || (((uint32_t)dataLen + (uint32_t)dataIt) >= RFAL_FEATURE_ISO_DEP_APDU_MAX_LEN) ) + { + return (ERR_NOMEM); + } + + if( dataLen > 0U ) + { + ST_MEMCPY( &cAPDU.cApduBuf->apdu[dataIt], data, dataLen ); + } + dataIt += dataLen; + cAPDU.Lc = dataIt; + + return rfalT4TPollerComposeCAPDU( &cAPDU ); +} + + +#endif /* RFAL_FEATURE_T4T */ diff --git a/Software/fab-reader2-c/components/st25r3911/CMakeLists.txt b/Software/fab-reader2-c/components/st25r3911/CMakeLists.txt new file mode 100644 index 0000000..66900f1 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "st25r3911.c" "st25r3911_com.c" "st25r3911_interrupt.c" "timer.c" "st25r3911_spi.c" "utils.c" + INCLUDE_DIRS "." REQUIRES driver) diff --git a/Software/fab-reader2-c/components/st25r3911/Release_Notes.html b/Software/fab-reader2-c/components/st25r3911/Release_Notes.html new file mode 100644 index 0000000..cefbfb6 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/Release_Notes.html @@ -0,0 +1,177 @@ + + + + + + + + + + + + + Release Notes for ST25R3911 Driver + + + + + + + + + +
+


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Release +Notes for ST25R3911 driver

+

Copyright +2017 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Update +History

+ + +

V1.0.0 +/ 15-March-2017

+

Main +Changes

+ + +
    +
  • First +official release.
    • +
+ +

License
+

+
Redistribution +and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met:
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    +
  1. Redistributions +of source code must retain the above copyright notice, this list of +conditions and the following disclaimer.
    2. +
  2. Redistributions +in binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution.
    3. +
  3. Neither the +name of STMicroelectronics nor the names of its contributors may be +used to endorse or promote products derived
    +
    4. +
+        +from this software without specific prior written permission.
+
+ THIS +SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +THE POSSIBILITY OF SUCH DAMAGE.
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For +complete documentation on STM32 Microcontrollers +visit www.st.com/STM32

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+
+ + \ No newline at end of file diff --git a/Software/fab-reader2-c/components/st25r3911/platform.h b/Software/fab-reader2-c/components/st25r3911/platform.h new file mode 100644 index 0000000..c61c170 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/platform.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ +/*! \file + * + * \author + * + * \brief Platform header file. Defining platform independent functionality. + * + */ + + +/* + * PROJECT: + * $Revision: $ + * LANGUAGE: ISO C99 + */ + +/*! \file platform.h + * + * \author Gustavo Patricio + * + * \brief Platform specific definition layer + * + * This should contain all platform and hardware specifics such as + * GPIO assignment, system resources, locks, IRQs, etc + * + * Each distinct platform/system/board must provide this definitions + * for all SW layers to use + * + */ + +#ifndef PLATFORM_H +#define PLATFORM_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include + +#include + +#include +#include +#include +#include + +#include "st25r3911_spi.h" +#include "timer.h" + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ +#define ST25R391X_SS_PIN 4 /*!< GPIO pin used for ST25R3911 SPI SS */ +#define ST25R391X_SS_PORT /*!< GPIO port used for ST25R3911 SPI SS port */ + +#define ST25R391X_INT_PIN 15 /*!< GPIO pin used for ST25R3911 External Interrupt */ +#define ST25R391X_INT_PORT /*!< GPIO port used for ST25R3911 External Interrupt */ + +#ifdef LED_FIELD_Pin +#define PLATFORM_LED_FIELD_PIN LED_FIELD_Pin /*!< GPIO pin used as field LED */ +#endif + +#ifdef LED_FIELD_GPIO_Port +#define PLATFORM_LED_FIELD_PORT LED_FIELD_GPIO_Port /*!< GPIO port used as field LED */ +#endif + + +#define PLATFORM_LED_A_PIN LED_A_Pin /*!< GPIO pin used for LED A */ +#define PLATFORM_LED_A_PORT LED_A_GPIO_Port /*!< GPIO port used for LED A */ +#define PLATFORM_LED_B_PIN LED_B_Pin /*!< GPIO pin used for LED B */ +#define PLATFORM_LED_B_PORT LED_B_GPIO_Port /*!< GPIO port used for LED B */ +#define PLATFORM_LED_F_PIN LED_F_Pin /*!< GPIO pin used for LED F */ +#define PLATFORM_LED_F_PORT LED_F_GPIO_Port /*!< GPIO port used for LED F */ +#define PLATFORM_LED_V_PIN LED_V_Pin /*!< GPIO pin used for LED V */ +#define PLATFORM_LED_V_PORT LED_V_GPIO_Port /*!< GPIO port used for LED V */ +#define PLATFORM_LED_AP2P_PIN LED_AP2P_Pin /*!< GPIO pin used for LED AP2P */ +#define PLATFORM_LED_AP2P_PORT LED_AP2P_GPIO_Port /*!< GPIO port used for LED AP2P*/ + +#define PLATFORM_USER_BUTTON_PIN 12 /*!< GPIO pin user button */ +#define PLATFORM_USER_BUTTON_PORT B1_GPIO_Port /*!< GPIO port user button */ + + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ +#define platformProtectST25R391xComm() taskENTER_CRITICAL(&CommProtectLock) /*!< Protect unique access to ST25R391x communication channel - IRQ disable on single thread environment (MCU) ; Mutex lock on a multi thread environment */ +#define platformUnprotectST25R391xComm() taskEXIT_CRITICAL(&CommProtectLock) /*!< Unprotect unique access to ST25R391x communication channel - IRQ enable on a single thread environment (MCU) ; Mutex unlock on a multi thread environment */ + +#define platformProtectST25R391xIrqStatus() platformProtectST25R391xComm() /*!< Protect unique access to IRQ status var - IRQ disable on single thread environment (MCU) ; Mutex lock on a multi thread environment */ +#define platformUnprotectST25R391xIrqStatus() platformUnprotectST25R391xComm() /*!< Unprotect the IRQ status var - IRQ enable on a single thread environment (MCU) ; Mutex unlock on a multi thread environment */ + +#define platformProtectWorker() /* Protect RFAL Worker/Task/Process from concurrent execution on multi thread platforms */ +#define platformUnprotectWorker() /* Unprotect RFAL Worker/Task/Process from concurrent execution on multi thread platforms */ + + +#define platformIrqST25R3911SetCallback( cb ) +#define platformIrqST25R3911PinInitialize() + +#define platformIrqST25R3916SetCallback( cb ) +#define platformIrqST25R3916PinInitialize() + + +#define platformLedsInitialize() /*!< Initializes the pins used as LEDs to outputs*/ + +#define platformLedOff( port, pin ) platformGpioClear((port), (pin)) /*!< Turns the given LED Off */ +#define platformLedOn( port, pin ) platformGpioSet((port), (pin)) /*!< Turns the given LED On */ +#define platformLedToogle( port, pin ) platformGpioToogle((port), (pin)) /*!< Toogle the given LED */ + +#define platformGpioSet( port, pin ) ESP_ERROR_CHECK(gpio_set_level(pin, 1)) /*!< Turns the given GPIO High */ +#define platformGpioClear( port, pin ) ESP_ERROR_CHECK(gpio_set_level(pin, 0)) /*!< Turns the given GPIO Low */ +#define platformGpioToogle( port, pin ) ESP_ERROR_CHECK(gpio_set_level(pin, !gpio_get_level(pin))) /*!< Toogles the given GPIO */ +#define platformGpioIsHigh( port, pin ) (gpio_get_level(pin)) /*!< Checks if the given LED is High */ +#define platformGpioIsLow( port, pin ) (!platformGpioIsHigh(port, pin)) /*!< Checks if the given LED is Low */ + +#define platformTimerCreate( t ) timerCalculateTimer(t) /*!< Create a timer with the given time (ms) */ +#define platformTimerIsExpired( timer ) timerIsExpired(timer) /*!< Checks if the given timer is expired */ +#define platformDelay( t ) vTaskDelay(pdMS_TO_TICKS(t)) /*!< Performs a delay for the given time (ms) */ + +#define platformGetSysTick() pdTICKS_TO_MS(xTaskGetTickCount()) /*!< Get System Tick ( 1 tick = 1 ms) */ + +#define platformSpiSelect() platformGpioClear( ST25R391X_SS_PORT, ST25R391X_SS_PIN ) /*!< SPI SS\CS: Chip|Slave Select */ +#define platformSpiDeselect() platformGpioSet( ST25R391X_SS_PORT, ST25R391X_SS_PIN ) /*!< SPI SS\CS: Chip|Slave Deselect */ +#define platformSpiTxRx( txBuf, rxBuf, len ) st25r3911_spiTxRx( (txBuf), (rxBuf), (len) ) /*!< SPI transceive */ + + +#define platformI2CTx( txBuf, len ) /*!< I2C Transmit */ +#define platformI2CRx( txBuf, len ) /*!< I2C Receive */ +#define platformI2CStart() /*!< I2C Start condition */ +#define platformI2CStop() /*!< I2C Stop condition */ +#define platformI2CRepeatStart() /*!< I2C Repeat Start */ +#define platformI2CSlaveAddrWR(add) /*!< I2C Slave address for Write operation */ +#define platformI2CSlaveAddrRD(add) /*!< I2C Slave address for Read operation */ + +#define platformLog(...) ESP_LOGI("RFAL",__VA_ARGS__) /*!< Log method */ + +/* +****************************************************************************** +* GLOBAL VARIABLES +****************************************************************************** +*/ +extern portMUX_TYPE CommProtectLock; /* Global Protection Counter provided per platform - instantiated in main.c */ + +/* +****************************************************************************** +* RFAL FEATURES CONFIGURATION +****************************************************************************** +*/ + +#define RFAL_FEATURE_LISTEN_MODE false /*!< Enable/Disable RFAL support for Listen Mode */ +#define RFAL_FEATURE_WAKEUP_MODE true /*!< Enable/Disable RFAL support for the Wake-Up mode */ +#define RFAL_FEATURE_NFCA true /*!< Enable/Disable RFAL support for NFC-A (ISO14443A) */ +#define RFAL_FEATURE_NFCB true /*!< Enable/Disable RFAL support for NFC-B (ISO14443B) */ +#define RFAL_FEATURE_NFCF false /*!< Enable/Disable RFAL support for NFC-F (FeliCa) */ +#define RFAL_FEATURE_NFCV false /*!< Enable/Disable RFAL support for NFC-V (ISO15693) */ +#define RFAL_FEATURE_T1T false /*!< Enable/Disable RFAL support for T1T (Topaz) */ +#define RFAL_FEATURE_T2T true /*!< Enable/Disable RFAL support for T2T */ +#define RFAL_FEATURE_T4T true /*!< Enable/Disable RFAL support for T4T */ +#define RFAL_FEATURE_ST25TB false /*!< Enable/Disable RFAL support for ST25TB */ +#define RFAL_FEATURE_ST25xV false /*!< Enable/Disable RFAL support for ST25TV/ST25DV */ +#define RFAL_FEATURE_DYNAMIC_ANALOG_CONFIG false /*!< Enable/Disable Analog Configs to be dynamically updated (RAM) */ +#define RFAL_FEATURE_DYNAMIC_POWER false /*!< Enable/Disable RFAL dynamic power support */ +#define RFAL_FEATURE_ISO_DEP true /*!< Enable/Disable RFAL support for ISO-DEP (ISO14443-4) */ +#define RFAL_FEATURE_ISO_DEP_POLL true /*!< Enable/Disable RFAL support for Poller mode (PCD) ISO-DEP (ISO14443-4) */ +#define RFAL_FEATURE_ISO_DEP_LISTEN false /*!< Enable/Disable RFAL support for Listen mode (PICC) ISO-DEP (ISO14443-4) */ +#define RFAL_FEATURE_NFC_DEP false /*!< Enable/Disable RFAL support for NFC-DEP (NFCIP1/P2P) */ + + +#define RFAL_FEATURE_ISO_DEP_IBLOCK_MAX_LEN 256U /*!< ISO-DEP I-Block max length. Please use values as defined by rfalIsoDepFSx */ +#define RFAL_FEATURE_ISO_DEP_APDU_MAX_LEN 1024U /*!< ISO-DEP APDU max length. Please use multiples of I-Block max length */ + +#endif /* PLATFORM_H */ + + diff --git a/Software/fab-reader2-c/components/st25r3911/st25r3911.c b/Software/fab-reader2-c/components/st25r3911/st25r3911.c new file mode 100644 index 0000000..20410a6 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st25r3911.c @@ -0,0 +1,656 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R3911 firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Ulrich Herrmann + * + * \brief ST25R3911 high level interface + * + */ + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ + +#include "st25r3911.h" +#include "st25r3911_com.h" +#include "st25r3911_interrupt.h" +#include "utils.h" + +/* +****************************************************************************** +* LOCAL DEFINES +****************************************************************************** +*/ + +#define ST25R3911_OSC_STABLE_TIMEOUT 10U /*!< Timeout for Oscillator to get stable, datasheet: 700us, take 5 ms */ +#define ST25R3911_CA_TIMEOUT 10U /*!< Timeout for Collision Avoidance command */ +#define ST25R3911_TOUT_CALIBRATE_CAP_SENSOR 4U /*!< Max duration Calibrate Capacitive Sensor command Datasheet: 3ms */ + +/* +****************************************************************************** +* LOCAL CONSTANTS +****************************************************************************** +*/ + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ +static uint32_t st25r3911NoResponseTime_64fcs; + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +static ReturnCode st25r3911ExecuteCommandAndGetResult(uint8_t cmd, uint8_t resreg, uint8_t sleeptime, uint8_t* result); + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + +void st25r3911TxRxOn( void ) +{ + st25r3911SetRegisterBits(ST25R3911_REG_OP_CONTROL, (ST25R3911_REG_OP_CONTROL_rx_en | ST25R3911_REG_OP_CONTROL_tx_en) ); +} + +void st25r3911TxRxOff( void ) +{ + st25r3911ClrRegisterBits(ST25R3911_REG_OP_CONTROL, (ST25R3911_REG_OP_CONTROL_rx_en | ST25R3911_REG_OP_CONTROL_tx_en) ); +} + + +void st25r3911OscOn( void ) +{ + /* Check if oscillator is already turned on and stable */ + /* Use ST25R3911_REG_OP_CONTROL_en instead of ST25R3911_REG_AUX_DISPLAY_osc_ok to be on the safe side */ + if( !st25r3911CheckReg( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_en, ST25R3911_REG_OP_CONTROL_en ) ) + { + /* Clear any eventual previous oscillator IRQ */ + st25r3911GetInterrupt( ST25R3911_IRQ_MASK_OSC ); + + /* enable oscillator frequency stable interrupt */ + st25r3911EnableInterrupts(ST25R3911_IRQ_MASK_OSC); + + /* enable oscillator and regulator output */ + st25r3911ModifyRegister(ST25R3911_REG_OP_CONTROL, 0x00, ST25R3911_REG_OP_CONTROL_en); + + /* wait for the oscillator interrupt */ + st25r3911WaitForInterruptsTimed(ST25R3911_IRQ_MASK_OSC, ST25R3911_OSC_STABLE_TIMEOUT); + st25r3911DisableInterrupts(ST25R3911_IRQ_MASK_OSC); + } + +} + + +void st25r3911Initialize(void) +{ + uint16_t vdd_mV; + + /* first, reset the st25r3911 */ + st25r3911ExecuteCommand(ST25R3911_CMD_SET_DEFAULT); + + /* Set Operation Control Register to default value */ + st25r3911WriteRegister(ST25R3911_REG_OP_CONTROL, 0x00); + + /* enable pull downs on miso line */ + st25r3911ModifyRegister(ST25R3911_REG_IO_CONF2, 0, + ST25R3911_REG_IO_CONF2_miso_pd1 | + ST25R3911_REG_IO_CONF2_miso_pd2); + + /* after reset all interrupts are enabled. so disable them at first */ + st25r3911DisableInterrupts(ST25R3911_IRQ_MASK_ALL); + /* and clear them, just to be sure... */ + st25r3911ClearInterrupts(); + + st25r3911OscOn(); + + /* Measure vdd and set sup3V bit accordingly */ + vdd_mV = st25r3911MeasureVoltage(ST25R3911_REG_REGULATOR_CONTROL_mpsv_vdd); + + st25r3911ModifyRegister(ST25R3911_REG_IO_CONF2, + ST25R3911_REG_IO_CONF2_sup3V, + (uint8_t)((vdd_mV < 3600U)?ST25R3911_REG_IO_CONF2_sup3V:0U)); + + /* Make sure Transmitter and Receiver are disabled */ + st25r3911TxRxOff(); + + return; +} + +void st25r3911Deinitialize(void) +{ + st25r3911DisableInterrupts(ST25R3911_IRQ_MASK_ALL); + + /* Disabe Tx and Rx, Keep OSC */ + st25r3911TxRxOff(); + + return; +} + +ReturnCode st25r3911AdjustRegulators(uint16_t* result_mV) +{ + uint8_t result; + uint8_t io_conf2; + ReturnCode err = ERR_NONE; + + /* Reset logic and set regulated voltages to be defined by result of Adjust Regulators command */ + st25r3911SetRegisterBits( ST25R3911_REG_REGULATOR_CONTROL, ST25R3911_REG_REGULATOR_CONTROL_reg_s ); + st25r3911ClrRegisterBits( ST25R3911_REG_REGULATOR_CONTROL, ST25R3911_REG_REGULATOR_CONTROL_reg_s ); + + st25r3911ExecuteCommandAndGetResult(ST25R3911_CMD_ADJUST_REGULATORS, + ST25R3911_REG_REGULATOR_RESULT, + 5, + &result); + + st25r3911ReadRegister(ST25R3911_REG_IO_CONF2, &io_conf2); + + result >>= ST25R3911_REG_REGULATOR_RESULT_shift_reg; + result -= 5U; + if (result_mV != NULL) + { + if((io_conf2 & ST25R3911_REG_IO_CONF2_sup3V) != 0U) + { + *result_mV = 2400; + *result_mV += (uint16_t)result * 100U; + } + else + { + *result_mV = 3900; + *result_mV += (uint16_t)result * 120U; + } + } + return err; +} + +void st25r3911MeasureAmplitude(uint8_t* result) +{ + st25r3911ExecuteCommandAndGetResult(ST25R3911_CMD_MEASURE_AMPLITUDE, + ST25R3911_REG_AD_RESULT, + 10, + result); +} + +void st25r3911MeasurePhase(uint8_t* result) +{ + st25r3911ExecuteCommandAndGetResult(ST25R3911_CMD_MEASURE_PHASE, + ST25R3911_REG_AD_RESULT, + 10, + result); +} + +void st25r3911MeasureCapacitance(uint8_t* result) +{ + st25r3911ExecuteCommandAndGetResult(ST25R3911_CMD_MEASURE_CAPACITANCE, + ST25R3911_REG_AD_RESULT, + 10, + result); +} + +void st25r3911CalibrateAntenna(uint8_t* result) +{ + st25r3911ExecuteCommandAndGetResult(ST25R3911_CMD_CALIBRATE_ANTENNA, + ST25R3911_REG_ANT_CAL_RESULT, + 10, + result); +} + +void st25r3911CalibrateModulationDepth(uint8_t* result) +{ + st25r3911ExecuteCommandAndGetResult(ST25R3911_CMD_CALIBRATE_MODULATION, + ST25R3911_REG_AM_MOD_DEPTH_RESULT, + 10, + result); +} + + +ReturnCode st25r3911CalibrateCapacitiveSensor(uint8_t* result) +{ + ReturnCode ret; + uint8_t res; + + /* Clear Manual calibration values to enable automatic calibration mode */ + st25r3911ClrRegisterBits( ST25R3911_REG_CAP_SENSOR_CONTROL, ST25R3916_REG_CAP_SENSOR_CONTROL_mask_cs_mcal ); + + /* Execute automatic calibration */ + ret = st25r3911ExecuteCommandAndGetResult( ST25R3911_CMD_CALIBRATE_C_SENSOR, ST25R3911_REG_CAP_SENSOR_RESULT, ST25R3911_TOUT_CALIBRATE_CAP_SENSOR, &res ); + + /* Check wether the calibration was successull */ + if( ((res & ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_end) != ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_end) || + ((res & ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_err) == ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_err) || (ret != ERR_NONE) ) + { + return ERR_IO; + } + + if( result != NULL ) + { + (*result) = (uint8_t)(res >> ST25R3911_REG_CAP_SENSOR_CONTROL_shift_cs_mcal); + } + + return ERR_NONE; +} + + +ReturnCode st25r3911SetBitrate(uint8_t txRate, uint8_t rxRate) +{ + uint8_t reg; + + st25r3911ReadRegister(ST25R3911_REG_BIT_RATE, ®); + if (rxRate != ST25R3911_BR_DO_NOT_SET) + { + if(rxRate > ST25R3911_BR_3390) + { + return ERR_PARAM; + } + else + { + reg = (uint8_t)(reg & ~ST25R3911_REG_BIT_RATE_mask_rxrate); /* MISRA 10.3 */ + reg |= rxRate << ST25R3911_REG_BIT_RATE_shift_rxrate; + } + } + if (txRate != ST25R3911_BR_DO_NOT_SET) + { + if(txRate > ST25R3911_BR_6780) + { + return ERR_PARAM; + } + else + { + reg = (uint8_t)(reg & ~ST25R3911_REG_BIT_RATE_mask_txrate); /* MISRA 10.3 */ + reg |= txRate<> ST25R3911_REG_FIFO_RX_STATUS2_shift_fifo_lb); +} + +uint32_t st25r3911GetNoResponseTime_64fcs(void) +{ + return st25r3911NoResponseTime_64fcs; +} + +void st25r3911StartGPTimer_8fcs(uint16_t gpt_8fcs, uint8_t trigger_source) +{ + st25r3911SetGPTime_8fcs(gpt_8fcs); + + st25r3911ModifyRegister(ST25R3911_REG_GPT_CONTROL, + ST25R3911_REG_GPT_CONTROL_gptc_mask, + trigger_source); + if (trigger_source == 0U) + { + st25r3911ExecuteCommand(ST25R3911_CMD_START_GP_TIMER); + } + + return; +} + +void st25r3911SetGPTime_8fcs(uint16_t gpt_8fcs) +{ + st25r3911WriteRegister(ST25R3911_REG_GPT1, (uint8_t)(gpt_8fcs >> 8)); + st25r3911WriteRegister(ST25R3911_REG_GPT2, (uint8_t)(gpt_8fcs & 0xffU)); + + return; +} + +bool st25r3911CheckReg( uint8_t reg, uint8_t mask, uint8_t value ) +{ + uint8_t regVal; + + regVal = 0; + st25r3911ReadRegister( reg, ®Val ); + + return ((regVal & mask) == value ); +} + + +bool st25r3911CheckChipID( uint8_t *rev ) +{ + uint8_t ID; + + ID = 0; + st25r3911ReadRegister( ST25R3911_REG_IC_IDENTITY, &ID ); + + platformLog("Chip ID: 0x%02x", ID); + /* Check if IC Identity Register contains ST25R3911's IC type code */ + if( (ID & ST25R3911_REG_IC_IDENTITY_mask_ic_type) != ST25R3911_REG_IC_IDENTITY_ic_type ) + { + return false; + } + + if(rev != NULL) + { + *rev = (ID & ST25R3911_REG_IC_IDENTITY_mask_ic_rev); + } + + return true; +} + +ReturnCode st25r3911SetNoResponseTime_64fcs(uint32_t nrt_64fcs) +{ + ReturnCode err = ERR_NONE; + uint8_t nrt_step = 0; + uint32_t noResponseTime_64fcs = nrt_64fcs; /* MISRA 17.8: Use intermediate variable */ + + st25r3911NoResponseTime_64fcs = noResponseTime_64fcs; + if (noResponseTime_64fcs > (uint32_t)0xFFFFU) + { + nrt_step = ST25R3911_REG_GPT_CONTROL_nrt_step; + noResponseTime_64fcs = (noResponseTime_64fcs + 63U) / 64U; + if (noResponseTime_64fcs > (uint32_t)0xFFFFU) + { + noResponseTime_64fcs = 0xFFFFU; + err = ERR_PARAM; + } + st25r3911NoResponseTime_64fcs = 64U * noResponseTime_64fcs; + } + + st25r3911ModifyRegister(ST25R3911_REG_GPT_CONTROL, ST25R3911_REG_GPT_CONTROL_nrt_step, nrt_step); + st25r3911WriteRegister(ST25R3911_REG_NO_RESPONSE_TIMER1, (uint8_t)(noResponseTime_64fcs >> 8)); + st25r3911WriteRegister(ST25R3911_REG_NO_RESPONSE_TIMER2, (uint8_t)(noResponseTime_64fcs & 0xffU)); + + return err; +} + +ReturnCode st25r3911SetStartNoResponseTime_64fcs(uint32_t nrt_64fcs) +{ + ReturnCode err; + + err = st25r3911SetNoResponseTime_64fcs( nrt_64fcs ); + if(err == ERR_NONE) + { + st25r3911ExecuteCommand(ST25R3911_CMD_START_NO_RESPONSE_TIMER); + } + + return err; +} + +ReturnCode st25r3911PerformCollisionAvoidance( uint8_t FieldONCmd, uint8_t pdThreshold, uint8_t caThreshold, uint8_t nTRFW ) +{ + uint8_t treMask; + uint32_t irqs; + + if( (FieldONCmd != ST25R3911_CMD_INITIAL_RF_COLLISION) && + (FieldONCmd != ST25R3911_CMD_RESPONSE_RF_COLLISION_0) && + (FieldONCmd != ST25R3911_CMD_RESPONSE_RF_COLLISION_N) ) + { + return ERR_PARAM; + } + + /* Check if new thresholds are to be applied */ + if( (pdThreshold != ST25R3911_THRESHOLD_DO_NOT_SET) || (caThreshold != ST25R3911_THRESHOLD_DO_NOT_SET) ) + { + treMask = 0; + + if(pdThreshold != ST25R3911_THRESHOLD_DO_NOT_SET) + { + treMask |= ST25R3911_REG_FIELD_THRESHOLD_mask_trg; + } + + if(caThreshold != ST25R3911_THRESHOLD_DO_NOT_SET) + { + treMask |= ST25R3911_REG_FIELD_THRESHOLD_mask_rfe; + } + + /* Set Detection Threshold and|or Collision Avoidance Threshold */ + st25r3911ChangeRegisterBits( ST25R3911_REG_FIELD_THRESHOLD, treMask, (pdThreshold & ST25R3911_REG_FIELD_THRESHOLD_mask_trg) | (caThreshold & ST25R3911_REG_FIELD_THRESHOLD_mask_rfe ) ); + } + + /* Set n x TRFW */ + st25r3911ModifyRegister(ST25R3911_REG_AUX, ST25R3911_REG_AUX_mask_nfc_n, (nTRFW & ST25R3911_REG_AUX_mask_nfc_n) ); + + /* Enable and clear CA specific interrupts and execute command */ + st25r3911EnableInterrupts( (ST25R3911_IRQ_MASK_CAC | ST25R3911_IRQ_MASK_CAT) ); + st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_CAC | ST25R3911_IRQ_MASK_CAT) ); + + st25r3911ExecuteCommand(FieldONCmd); + + irqs = st25r3911WaitForInterruptsTimed(ST25R3911_IRQ_MASK_CAC | ST25R3911_IRQ_MASK_CAT, ST25R3911_CA_TIMEOUT ); + + /* Clear any previous External Field events and disable CA specific interrupts */ + st25r3911GetInterrupt( (ST25R3911_IRQ_MASK_EOF | ST25R3911_IRQ_MASK_EON) ); + st25r3911DisableInterrupts(ST25R3911_IRQ_MASK_CAC | ST25R3911_IRQ_MASK_CAT); + + + if((ST25R3911_IRQ_MASK_CAC & irqs) != 0U) /* Collision occurred */ + { + return ERR_RF_COLLISION; + } + + if((ST25R3911_IRQ_MASK_CAT & irqs) != 0U) /* No Collision detected, Field On */ + { + return ERR_NONE; + } + + /* No interrupt detected */ + return ERR_INTERNAL; +} + +ReturnCode st25r3911GetRegsDump(uint8_t* resRegDump, uint8_t* sizeRegDump) +{ + uint8_t regIt; + uint8_t regDump[ST25R3911_REG_IC_IDENTITY+1U]; + + if(!sizeRegDump || !resRegDump) + { + return ERR_PARAM; + } + + for( regIt = ST25R3911_REG_IO_CONF1; regIt < SIZEOF_ARRAY(regDump); regIt++ ) + { + st25r3911ReadRegister(regIt, ®Dump[regIt] ); + } + + *sizeRegDump = MIN(*sizeRegDump, regIt); + if( *sizeRegDump > 0U ) /* MISRA 21.18 */ + { + ST_MEMCPY(resRegDump, regDump, *sizeRegDump ); + } + + return ERR_NONE; +} + + +void st25r3911SetNumTxBits( uint32_t nBits ) +{ + st25r3911WriteRegister(ST25R3911_REG_NUM_TX_BYTES2, (uint8_t)((nBits >> 0) & 0xffU)); + st25r3911WriteRegister(ST25R3911_REG_NUM_TX_BYTES1, (uint8_t)((nBits >> 8) & 0xffU)); +} + + +bool st25r3911IsCmdValid( uint8_t cmd ) +{ + if( !((cmd >= ST25R3911_CMD_SET_DEFAULT) && (cmd <= ST25R3911_CMD_ANALOG_PRESET)) && + !((cmd >= ST25R3911_CMD_MASK_RECEIVE_DATA) && (cmd <= ST25R3911_CMD_CLEAR_RSSI)) && + !((cmd >= ST25R3911_CMD_TRANSPARENT_MODE) && (cmd <= ST25R3911_CMD_START_NO_RESPONSE_TIMER)) && + !((cmd >= ST25R3911_CMD_TEST_CLEARA) && (cmd <= ST25R3911_CMD_FUSE_PPROM)) ) + { + return false; + } + return true; +} + +ReturnCode st25r3911StreamConfigure(const struct st25r3911StreamConfig *config) +{ + uint8_t smd = 0; + uint8_t mode; + + if (config->useBPSK != 0U) + { + mode = ST25R3911_REG_MODE_om_bpsk_stream; + if ((config->din<2U) || (config->din>4U)) /* not in fc/4 .. fc/16 */ + { + return ERR_PARAM; + } + smd |= (4U - config->din) << ST25R3911_REG_STREAM_MODE_shift_scf; + + } + else + { + mode = ST25R3911_REG_MODE_om_subcarrier_stream; + if ((config->din<3U) || (config->din>6U)) /* not in fc/8 .. fc/64 */ + { + return ERR_PARAM; + } + smd |= (6U - config->din) << ST25R3911_REG_STREAM_MODE_shift_scf; + if (config->report_period_length == 0U) + { + return ERR_PARAM; + } + } + + if ((config->dout<1U) || (config->dout>7U)) /* not in fc/2 .. fc/128 */ + { + return ERR_PARAM; + } + smd |= (7U - config->dout) << ST25R3911_REG_STREAM_MODE_shift_stx; + + if (config->report_period_length > 3U) + { + return ERR_PARAM; + } + smd |= config->report_period_length << ST25R3911_REG_STREAM_MODE_shift_scp; + + st25r3911WriteRegister(ST25R3911_REG_STREAM_MODE, smd); + st25r3911ChangeRegisterBits(ST25R3911_REG_MODE, ST25R3911_REG_MODE_mask_om, mode); + + return ERR_NONE; +} + +/*******************************************************************************/ +ReturnCode st25r3911GetRSSI( uint16_t *amRssi, uint16_t *pmRssi ) +{ + /*******************************************************************************/ + /* MISRA 8.9 An object should be defined at block scope if its identifier only appears in a single function */ + /*< ST25R3911 RSSI Display Reg values:0 1 2 3 4 5 6 7 8 9 a b c d e f */ + const uint16_t st25r3911Rssi2mV[] = { 0 ,20 ,27 ,37 ,52 ,72 ,99 ,136 ,190 ,262 ,357 ,500 ,686 ,950, 0, 0 }; + + /* ST25R3911 2/3 stage gain reduction [dB] 0 0 0 0 0 3 6 9 12 15 18 na na na na na */ + const uint16_t st25r3911Gain2Percent[] = { 100, 100, 100, 100, 100, 141, 200, 281, 398, 562, 794, 1, 1, 1, 1, 1 }; + /*******************************************************************************/ + + uint8_t rssi; + uint8_t gainRed; + + st25r3911ReadRegister( ST25R3911_REG_RSSI_RESULT, &rssi ); + st25r3911ReadRegister( ST25R3911_REG_GAIN_RED_STATE, &gainRed ); + + if( amRssi != NULL ) + { + *amRssi = (uint16_t) ( ( (uint32_t)st25r3911Rssi2mV[ (rssi >> ST25R3911_REG_RSSI_RESULT_shift_rssi_am) ] * (uint32_t)st25r3911Gain2Percent[ (gainRed >> ST25R3911_REG_GAIN_RED_STATE_shift_gs_am) ] ) / 100U ); + } + + if( pmRssi != NULL ) + { + *pmRssi = (uint16_t) ( ( (uint32_t)st25r3911Rssi2mV[ (rssi & ST25R3911_REG_RSSI_RESULT_mask_rssi_pm) ] * (uint32_t)st25r3911Gain2Percent[ (gainRed & ST25R3911_REG_GAIN_RED_STATE_mask_gs_pm) ] ) / 100U ); + } + + return ERR_NONE; +} + +/* +****************************************************************************** +* LOCAL FUNCTIONS +****************************************************************************** +*/ +/*! + ***************************************************************************** + * \brief Executes a direct command and returns the result + * + * This function executes the direct command given by \a cmd waits for + * \a sleeptime for I_dct and returns the result read from register \a resreg. + * No checking of the validity of the cmd is performed. + * + * \param[in] cmd: direct command to execute. + * \param[in] resreg: Address of the register containing the result. + * \param[in] sleeptime: time in milliseconds to wait before reading the result. + * \param[out] result: 8 bit long result + * + ***************************************************************************** + */ +static ReturnCode st25r3911ExecuteCommandAndGetResult(uint8_t cmd, uint8_t resreg, uint8_t sleeptime, uint8_t* result) +{ + + st25r3911EnableInterrupts(ST25R3911_IRQ_MASK_DCT); + st25r3911GetInterrupt(ST25R3911_IRQ_MASK_DCT); + st25r3911ExecuteCommand(cmd); + st25r3911WaitForInterruptsTimed(ST25R3911_IRQ_MASK_DCT, sleeptime); + st25r3911DisableInterrupts(ST25R3911_IRQ_MASK_DCT); + + /* read out the result if the pointer is not NULL */ + if (result != NULL) + { + st25r3911ReadRegister(resreg, result); + } + + return ERR_NONE; +} diff --git a/Software/fab-reader2-c/components/st25r3911/st25r3911.h b/Software/fab-reader2-c/components/st25r3911/st25r3911.h new file mode 100644 index 0000000..3a81b34 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st25r3911.h @@ -0,0 +1,601 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R3911 firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Ulrich Herrmann + * + * \brief ST25R3911 declaration file + * + * API: + * - Initialize ST25R3911 driver: #st25r3911Initialize + * - Deinitialize ST25R3911 driver: #st25r3911Deinitialize + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-HAL + * \brief RFAL Hardware Abstraction Layer + * @{ + * + * \addtogroup ST25R3911 + * \brief RFAL ST25R3911 Driver + * @{ + * + * \addtogroup ST25R3911_Driver + * \brief RFAL ST25R3911 Driver + * @{ + * + */ + +#ifndef ST25R3911_H +#define ST25R3911_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" +#include "st_errno.h" + +/* +****************************************************************************** +* GLOBAL DATATYPES +****************************************************************************** +*/ + +/*! Parameters how the stream mode should work */ +struct st25r3911StreamConfig { + uint8_t useBPSK; /*!< 0: subcarrier, 1:BPSK */ + uint8_t din; /*!< the divider for the in subcarrier frequency: fc/2^din */ + uint8_t dout; /*!< the divider for the in subcarrier frequency fc/2^dout */ + uint8_t report_period_length; /*!< the length of the reporting period 2^report_period_length */ +}; + + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ +#define ST25R3911_FDT_NONE 0x00U /*!< Value indicating not to perform FDT */ + +#define MS_TO_64FCS(A) ((A) * 212U) /*!< Converts from ms to 64/fc steps */ +#define MS_FROM_64FCS(A) ((A) / 212U) /*!< Converts from 64/fc steps to ms */ + +/* ST25R3911 direct commands */ +#define ST25R3911_CMD_SET_DEFAULT 0xC1U /*!< Puts the chip in default state (same as after power-up) */ +#define ST25R3911_CMD_CLEAR_FIFO 0xC2U /*!< Stops all activities and clears FIFO */ +#define ST25R3911_CMD_TRANSMIT_WITH_CRC 0xC4U /*!< Transmit with CRC */ +#define ST25R3911_CMD_TRANSMIT_WITHOUT_CRC 0xC5U /*!< Transmit without CRC */ +#define ST25R3911_CMD_TRANSMIT_REQA 0xC6U /*!< Transmit REQA */ +#define ST25R3911_CMD_TRANSMIT_WUPA 0xC7U /*!< Transmit WUPA */ +#define ST25R3911_CMD_INITIAL_RF_COLLISION 0xC8U /*!< NFC transmit with Initial RF Collision Avoidance */ +#define ST25R3911_CMD_RESPONSE_RF_COLLISION_N 0xC9U /*!< NFC transmit with Response RF Collision Avoidance */ +#define ST25R3911_CMD_RESPONSE_RF_COLLISION_0 0xCAU /*!< NFC transmit with Response RF Collision Avoidance with n=0 */ +#define ST25R3911_CMD_NORMAL_NFC_MODE 0xCBU /*!< NFC switch to normal NFC mode */ +#define ST25R3911_CMD_ANALOG_PRESET 0xCCU /*!< Analog Preset */ +#define ST25R3911_CMD_MASK_RECEIVE_DATA 0xD0U /*!< Mask recive data */ +#define ST25R3911_CMD_UNMASK_RECEIVE_DATA 0xD1U /*!< Unmask recive data */ +#define ST25R3911_CMD_MEASURE_AMPLITUDE 0xD3U /*!< Measure singal amplitude on RFI inputs */ +#define ST25R3911_CMD_SQUELCH 0xD4U /*!< Squelch */ +#define ST25R3911_CMD_CLEAR_SQUELCH 0xD5U /*!< Clear Squelch */ +#define ST25R3911_CMD_ADJUST_REGULATORS 0xD6U /*!< Adjust regulators */ +#define ST25R3911_CMD_CALIBRATE_MODULATION 0xD7U /*!< Calibrate modulation depth */ +#define ST25R3911_CMD_CALIBRATE_ANTENNA 0xD8U /*!< Calibrate antenna */ +#define ST25R3911_CMD_MEASURE_PHASE 0xD9U /*!< Measure phase between RFO and RFI signal */ +#define ST25R3911_CMD_CLEAR_RSSI 0xDAU /*!< clear RSSI bits and restart the measurement */ +#define ST25R3911_CMD_TRANSPARENT_MODE 0xDCU /*!< Transparent mode */ +#define ST25R3911_CMD_CALIBRATE_C_SENSOR 0xDDU /*!< Calibrate the capacitive sensor */ +#define ST25R3911_CMD_MEASURE_CAPACITANCE 0xDEU /*!< Measure capacitance */ +#define ST25R3911_CMD_MEASURE_VDD 0xDFU /*!< Measure power supply voltage */ +#define ST25R3911_CMD_START_GP_TIMER 0xE0U /*!< Start the general purpose timer */ +#define ST25R3911_CMD_START_WUP_TIMER 0xE1U /*!< Start the wake-up timer */ +#define ST25R3911_CMD_START_MASK_RECEIVE_TIMER 0xE2U /*!< Start the mask-receive timer */ +#define ST25R3911_CMD_START_NO_RESPONSE_TIMER 0xE3U /*!< Start the no-repsonse timer */ +#define ST25R3911_CMD_TEST_CLEARA 0xFAU /*!< Clear Test register */ +#define ST25R3911_CMD_TEST_CLEARB 0xFBU /*!< Clear Test register */ +#define ST25R3911_CMD_TEST_ACCESS 0xFCU /*!< Enable R/W access to the test registers */ +#define ST25R3911_CMD_LOAD_PPROM 0xFDU /*!< Load data from the poly fuses to RAM */ +#define ST25R3911_CMD_FUSE_PPROM 0xFEU /*!< Fuse poly fuses with data from the RAM */ + + +#define ST25R3911_FIFO_DEPTH 96U /*!< Depth of FIFO */ + +#define ST25R3911_THRESHOLD_DO_NOT_SET 0xFFU /*!< Indicates not to change this Threshold */ + +#define ST25R3911_BR_DO_NOT_SET 0xFFU /*!< Indicates not to change this Bit Rate */ +#define ST25R3911_BR_106 0x00U /*!< ST25R3911 Bit Rate 106 kbit/s (fc/128) */ +#define ST25R3911_BR_212 0x01U /*!< ST25R3911 Bit Rate 212 kbit/s (fc/64) */ +#define ST25R3911_BR_424 0x02U /*!< ST25R3911 Bit Rate 424 kbit/s (fc/32) */ +#define ST25R3911_BR_848 0x03U /*!< ST25R3911 Bit Rate 848 kbit/s (fc/16) */ +#define ST25R3911_BR_1695 0x04U /*!< ST25R3911 Bit Rate 1696 kbit/s (fc/8) */ +#define ST25R3911_BR_3390 0x05U /*!< ST25R3911 Bit Rate 3390 kbit/s (fc/4) */ +#define ST25R3911_BR_6780 0x06U /*!< ST25R3911 Bit Rate 6780 kbit/s (fc/2) */ + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ + +/*! Checks if General Purpose Timer is still running by reading gpt_on flag */ +#define st25r3911IsGPTRunning( ) ( st25r3911CheckReg(ST25R3911_REG_REGULATOR_RESULT, ST25R3911_REG_REGULATOR_RESULT_gpt_on, ST25R3911_REG_REGULATOR_RESULT_gpt_on) ) + +/*! Checks if CRC is configured to be in FIFO */ +#define st25r3911IsCRCinFIFO( ) ( st25r3911CheckReg(ST25R3911_REG_AUX, ST25R3911_REG_AUX_crc_2_fifo, ST25R3911_REG_AUX_crc_2_fifo) ) + +/*! Checks if External Filed is detected by reading ST25R3911 External Field + * Detector output */ +#define st25r3911IsExtFieldOn() ( st25r3911CheckReg(ST25R3911_REG_AUX_DISPLAY, ST25R3911_REG_AUX_DISPLAY_efd_o, ST25R3911_REG_AUX_DISPLAY_efd_o ) ) + +/*! Checks if Transmitter is enabled (Field On) */ +#define st25r3911IsTxEnabled() ( st25r3911CheckReg(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en, ST25R3911_REG_OP_CONTROL_tx_en ) ) + +/*! Turn Off Tx (Field Off) */ +#define st25r3911TxOff() st25r3911ClrRegisterBits(ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_tx_en ); + +/*! Checks if last FIFO byte is complete */ +#define st25r3911IsLastFIFOComplete() st25r3911CheckReg( ST25R3911_REG_FIFO_RX_STATUS2, ST25R3911_REG_FIFO_RX_STATUS2_mask_fifo_lb, 0 ) + +/*! Checks if the Oscillator is enabled */ +#define st25r3911IsOscOn() st25r3911CheckReg( ST25R3911_REG_OP_CONTROL, ST25R3911_REG_OP_CONTROL_en, ST25R3911_REG_OP_CONTROL_en ) + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +/*! + ***************************************************************************** + * \brief Turn on Oscillator and Regulator + * + * This function turn on oscillator and regulator and wait for the oscillator to + * become stable. + * + ***************************************************************************** + */ +extern void st25r3911OscOn( void ); + +/*! + ***************************************************************************** + * \brief Turn On Tx and Rx + * + * This function turns On Tx and Rx (Field On) + * + ***************************************************************************** + */ +extern void st25r3911TxRxOn( void ); + +/*! + ***************************************************************************** + * \brief Turn Off Tx and Rx + * + * This function turns Off Tx and Rx (Field Off) + * + ***************************************************************************** + */ +extern void st25r3911TxRxOff( void ); + +/*! + ***************************************************************************** + * \brief Initialise ST25R3911 driver + * + * This function initialises the ST25R3911 driver. + * + ***************************************************************************** + */ +extern void st25r3911Initialize( void ); + +/*! + ***************************************************************************** + * \brief Deinitialize ST25R3911 driver + * + * Calling this function deinitializes the ST25R3911 driver. + * + ***************************************************************************** + */ +extern void st25r3911Deinitialize( void ); + + +/*! + ***************************************************************************** + * \brief Sets the bitrate registers + * + * This function sets the bitrate register for rx and tx + * + * \param txRate : speed is 2^txrate * 106 kb/s + * 0xff : don't set txrate + * \param rxRate : speed is 2^rxrate * 106 kb/s + * 0xff : don't set rxrate + * + * \return ERR_NONE : No error, both bit rates were set + * \return ERR_PARAM: At least one bit rate was invalid + * + ***************************************************************************** + */ +extern ReturnCode st25r3911SetBitrate( uint8_t txRate, uint8_t rxRate ); + +/*! + ***************************************************************************** + * \brief Adjusts supply regulators according to the current supply voltage + * + * On this function the power level is measured in maximum load conditions and + * the regulated voltage reference is set to 250mV below this level. + * Execution of this function lasts arround 5ms. + * + * The regulated voltages will be set to the result of Adjust Regulators + * + * \param [out] result_mV : Result of calibration in milliVolts. + * + * \return ERR_IO : Error during communication with ST25R3911. + * \return ERR_NONE : No error. + * + ***************************************************************************** + */ +extern ReturnCode st25r3911AdjustRegulators( uint16_t* result_mV ); + +/*! + ***************************************************************************** + * \brief Measure Amplitude + * + * This function measured the amplitude on the RFI inputs and stores the + * result in parameter \a result. + * + * \param[out] result: 8 bit long result of RF measurement. + * + ***************************************************************************** + */ +extern void st25r3911MeasureAmplitude( uint8_t* result ); + +/*! + ***************************************************************************** + * \brief Measure Capacitance + * + * This function performs the capacitance measurement and stores the + * result in parameter \a result. + * + * \param[out] result: 8 bit long result of RF measurement. + * + ***************************************************************************** + */ +extern void st25r3911MeasureCapacitance( uint8_t* result ); + +/*! + ***************************************************************************** + * \brief Measure Voltage + * + * This function measures the voltage on one of VDD and VSP_* + * result in parameter \a result. + * + * \param[in] mpsv : one of ST25R3911_REG_REGULATOR_CONTROL_mpsv_vdd + * ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_rf + * ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_a + * or ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_d + * + * \return the measured voltage raw values + * + ***************************************************************************** + */ +extern uint8_t st25r3911MeasurePowerSupply( uint8_t mpsv ); + +/*! + ***************************************************************************** + * \brief Measure Voltage + * + * This function measures the voltage on one of VDD and VSP_* + * result in parameter \a result. + * + * \param[in] mpsv : one of ST25R3911_REG_REGULATOR_CONTROL_mpsv_vdd + * ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_rf + * ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_a + * or ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_d + * + * \return the measured voltage in mV + * + ***************************************************************************** + */ +extern uint16_t st25r3911MeasureVoltage( uint8_t mpsv ); + +/*! + ***************************************************************************** + * \brief Calibrate antenna + * + * This function is used to calibrate the antenna using a special sequence. + * The result is stored in the \a result parameter. + * + * \param[out] result: 8 bit long result of antenna calibration algorithm. + * + ***************************************************************************** + */ +extern void st25r3911CalibrateAntenna( uint8_t* result ); + +/*! + ***************************************************************************** + * \brief Measure Phase + * + * This function performs a Phase measurement. + * The result is stored in the \a result parameter. + * + * \param[out] result: 8 bit long result of the measurement. + * + ***************************************************************************** + */ +extern void st25r3911MeasurePhase( uint8_t* result ); + +/*! + ***************************************************************************** + * \brief Calibrate modulation depth + * + * This function is used to calibrate the modulation depth using a special sequence. + * The result is stored in the \a result parameter. + * + * \param[out] result: 8 bit long result of antenna calibration algorithm. + * + ***************************************************************************** + */ +extern void st25r3911CalibrateModulationDepth( uint8_t* result ); + + +/*! + ***************************************************************************** + * \brief Calibrate Capacitive Sensor + * + * This function performs automatic calibration of the capacitive sensor + * and stores the result in parameter \a result. + * + * \warning To avoid interference with Xtal oscillator and reader magnetic + * field, it is strongly recommended to perform calibration + * in Power-down mode only. + * This method does not modify the Oscillator nor transmitter state, + * these should be configured before by user. + * + * \param[out] result: 5 bit long result of the calibration. + * Binary weighted, step 0.1 pF, max 3.1 pF + * + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_IO : The calibration was not successful + * \return ERR_NONE : No error + * + ***************************************************************************** + */ +extern ReturnCode st25r3911CalibrateCapacitiveSensor( uint8_t* result ); + +/*! + ***************************************************************************** + * \brief set no response time + * + * This function executes sets the no response time to the defines value + * + * \param nrt_64fcs : no response time in 64/fc = 4.72us + * completion interrupt + * + * \return ERR_PARAM : if time is too large + */ +extern ReturnCode st25r3911SetNoResponseTime_64fcs( uint32_t nrt_64fcs ); + +/*! + ***************************************************************************** + * \brief set no response time + * + * This function executes sets and immediately start the no response timer + * to the defines value + * This is used when needs to add more time before timeout whitout Tx + * + * \param nrt_64fcs : no response time in 64/fc = 4.72us + * completion interrupt + * + * \return ERR_PARAM : if time is too large + */ +extern ReturnCode st25r3911SetStartNoResponseTime_64fcs( uint32_t nrt_64fcs ); + +/*! + ***************************************************************************** + * \brief Perform Collision Avoidance + * + * Performs Collision Avoidance with the given threshold and with the + * n number of TRFW + * + * \param[in] FieldONCmd : Field ON command to be executed ST25R3911_CMD_INITIAL_RF_COLLISION + * or ST25R3911_CMD_RESPONSE_RF_COLLISION_0/N + * \param[in] pdThreshold : Peer Detection Threshold (ST25R3916_REG_FIELD_THRESHOLD_trg_xx) + * 0xff : don't set Threshold (ST25R3916_THRESHOLD_DO_NOT_SET) + * \param[in] caThreshold : Collision Avoidance Threshold (ST25R3916_REG_FIELD_THRESHOLD_rfe_xx) + * 0xff : don't set Threshold (ST25R3916_THRESHOLD_DO_NOT_SET) + * \param[in] nTRFW : Number of TRFW + * + * \return ERR_NONE : no collision detected + * \return ERR_RF_COLLISION : collision detected + */ +extern ReturnCode st25r3911PerformCollisionAvoidance( uint8_t FieldONCmd, uint8_t pdThreshold, uint8_t caThreshold, uint8_t nTRFW ); + + +/*! + ***************************************************************************** + * \brief Get amount of bits of the last FIFO byte if incomplete + * + * Gets the number of bits of the last FIFO byte if incomplete + * + * \return the number of bits of the last FIFO byte if incomplete, 0 if + * the last byte is complete + * + ***************************************************************************** + */ +extern uint8_t st25r3911GetNumFIFOLastBits( void ); + +/*! + ***************************************************************************** + * \brief Get NRT time + * + * This returns the last value set on the NRT + * + * \warning it does not reads chip register, just the sw var that contains the + * last value set before + * + * \return the value of the NRT + */ +extern uint32_t st25r3911GetNoResponseTime_64fcs( void ); + +/*! + ***************************************************************************** + * \brief set general purpose timer timeout + * + * This function sets the proper registers but does not start the timer actually + * + * \param gpt_8fcs : general purpose timer timeout in 8/fc = 590ns + * + */ +extern void st25r3911SetGPTime_8fcs( uint16_t gpt_8fcs ); +/*! + ***************************************************************************** + * \brief Starts GPT with given timeout + * + * This function starts the general purpose timer with the given timeout + * + * \param gpt_8fcs : general purpose timer timeout in 8/fc = 590ns + * \param trigger_source : no trigger, start of Rx, end of Rx, end of Tx in NFC mode + */ +extern void st25r3911StartGPTimer_8fcs( uint16_t gpt_8fcs, uint8_t trigger_source ); + +/*! + ***************************************************************************** + * \brief Checks if register contains a expected value + * + * This function checks if the given reg contains a value that once masked + * equals the expected value + * + * \param reg : the register to check the value + * \param mask : the mask apply on register value + * \param value : expected value to be compared to + * + * \return true when reg contains the expected value | false otherwise + */ +bool st25r3911CheckReg( uint8_t reg, uint8_t mask, uint8_t value ); + +/*! + ***************************************************************************** + * \brief Sets the number Tx Bits + * + * Sets ST25R3911 internal registers with correct number of complete bytes and + * bits to be sent + * + * \param nBits : the number bits to be transmitted + ***************************************************************************** + */ +void st25r3911SetNumTxBits( uint32_t nBits ); + +/*! + ***************************************************************************** + * \brief Check Identity + * + * Checks if the chip ID is as expected. + * + * 5 bit IC type code for ST25R3911: 00001 + * The 3 lsb contain the IC revision code + * + * + * \param[out] rev : the IC revision code + * + * \return true when IC type is as expected + * + ***************************************************************************** + */ +bool st25r3911CheckChipID( uint8_t *rev ); + +/*! + ***************************************************************************** + * \brief Check if command is valid + * + * Checks if the given command is a valid ST25R3911 command + * + * \param[in] cmd: Command to check + * + * \return true if is a valid command + * \return false otherwise + * + ***************************************************************************** + */ +bool st25r3911IsCmdValid( uint8_t cmd ); + +/*! + ***************************************************************************** + * \brief Configure the stream mode of ST25R3911 + * + * This function initializes the stream with the given parameters + * + * \param[in] config : all settings for bitrates, type, etc. + + * \return ERR_NONE : No error, stream mode driver initialized. + * + ***************************************************************************** + */ +extern ReturnCode st25r3911StreamConfigure( const struct st25r3911StreamConfig *config ); + +/*! + ***************************************************************************** + * \brief Retrieves all internal registers from st25r3911 + */ +extern ReturnCode st25r3911GetRegsDump( uint8_t* resRegDump, uint8_t* sizeRegDump ); + + +/*! + ***************************************************************************** + * \brief Gets the RSSI values + * + * This function gets the RSSI value of the previous reception taking into + * account the gain reductions that were used. + * RSSI value for both AM and PM channel can be retrieved. + * + * \param[out] amRssi: the RSSI on the AM channel expressed in mV + * \param[out] pmRssi: the RSSI on the PM channel expressed in mV + * + * \return ERR_PARAM : Invalid parameter + * \return ERR_NONE : No error + * + ***************************************************************************** + */ +ReturnCode st25r3911GetRSSI( uint16_t *amRssi, uint16_t *pmRssi ); + + +#endif /* ST25R3911_H */ + +/** + * @} + * + * @} + * + * @} + * + * @} + */ + diff --git a/Software/fab-reader2-c/components/st25r3911/st25r3911_com.c b/Software/fab-reader2-c/components/st25r3911/st25r3911_com.c new file mode 100644 index 0000000..4ee4ac7 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st25r3911_com.c @@ -0,0 +1,457 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R3911 firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Ulrich Herrmann + * + * \brief Implementation of ST25R3911 communication. + * + */ + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "st25r3911_com.h" +#include "st25r3911.h" +#include "utils.h" + + +/* +****************************************************************************** +* LOCAL DEFINES +****************************************************************************** +*/ + +#define ST25R3911_WRITE_MODE (0U) /*!< ST25R3911 SPI Operation Mode: Write */ +#define ST25R3911_READ_MODE (1U << 6) /*!< ST25R3911 SPI Operation Mode: Read */ +#define ST25R3911_FIFO_LOAD (2U << 6) /*!< ST25R3911 SPI Operation Mode: FIFO Load */ +#define ST25R3911_FIFO_READ (0xBFU) /*!< ST25R3911 SPI Operation Mode: FIFO Read */ +#define ST25R3911_CMD_MODE (3U << 6) /*!< ST25R3911 SPI Operation Mode: Direct Command */ + +#define ST25R3911_CMD_LEN (1U) /*!< ST25R3911 CMD length */ +#define ST25R3911_BUF_LEN (ST25R3911_CMD_LEN+ST25R3911_FIFO_DEPTH) /*!< ST25R3911 communication buffer: CMD + FIFO length */ + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ + +#ifdef ST25R391X_COM_SINGLETXRX +static uint8_t comBuf[ST25R3911_BUF_LEN]; /*!< ST25R3911 communication buffer */ +#endif /* ST25R391X_COM_SINGLETXRX */ + +/* +****************************************************************************** +* LOCAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +static inline void st25r3911CheckFieldSetLED(uint8_t value) +{ + if ((ST25R3911_REG_OP_CONTROL_tx_en & value) != 0U) + { +#ifdef PLATFORM_LED_FIELD_PIN + platformLedOn( PLATFORM_LED_FIELD_PORT, PLATFORM_LED_FIELD_PIN ); + } + else + { + platformLedOff( PLATFORM_LED_FIELD_PORT, PLATFORM_LED_FIELD_PIN ); +#endif /* PLATFORM_LED_FIELD_PIN */ + } +} + + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ +void st25r3911ReadRegister(uint8_t reg, uint8_t* value) +{ +#ifdef ST25R391X_COM_SINGLETXRX + uint8_t* buf = comBuf; +#else /* ST25R391X_COM_SINGLETXRX */ + uint8_t buf[2]; +#endif /* ST25R391X_COM_SINGLETXRX */ + + platformProtectST25R391xComm(); + platformSpiSelect(); + + buf[0] = (reg | ST25R3911_READ_MODE); + buf[1] = 0; + + platformSpiTxRx(buf, buf, 2); + + if(value != NULL) + { + *value = buf[1]; + } + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + + return; +} + + +void st25r3911ReadMultipleRegisters(uint8_t reg, uint8_t* values, uint8_t length) +{ +#if !defined(ST25R391X_COM_SINGLETXRX) + uint8_t cmd = (reg | ST25R3911_READ_MODE); +#endif /* !ST25R391X_COM_SINGLETXRX */ + + if (length > 0U) + { + platformProtectST25R391xComm(); + platformSpiSelect(); + +#ifdef ST25R391X_COM_SINGLETXRX + + ST_MEMSET( comBuf, 0x00, MIN( (ST25R3911_CMD_LEN + (uint32_t)length), ST25R3911_BUF_LEN ) ); + comBuf[0] = (reg | ST25R3911_READ_MODE); + + platformSpiTxRx(comBuf, comBuf, MIN( (ST25R3911_CMD_LEN + length), ST25R3911_BUF_LEN ) ); /* Transceive as a single SPI call */ + ST_MEMCPY( values, &comBuf[ST25R3911_CMD_LEN], MIN( length, ST25R3911_BUF_LEN - ST25R3911_CMD_LEN ) ); /* Copy from local buf to output buffer and skip cmd byte */ + +#else /* ST25R391X_COM_SINGLETXRX */ + + /* Since the result comes one byte later, let's first transmit the adddress with discarding the result */ + platformSpiTxRx(&cmd, NULL, ST25R3911_CMD_LEN); + platformSpiTxRx(NULL, values, length); + +#endif /* ST25R391X_COM_SINGLETXRX */ + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + } + + return; +} + +void st25r3911ReadTestRegister(uint8_t reg, uint8_t* value) +{ + +#ifdef ST25R391X_COM_SINGLETXRX + uint8_t* buf = comBuf; +#else /* ST25R391X_COM_SINGLETXRX */ + uint8_t buf[3]; +#endif /* ST25R391X_COM_SINGLETXRX */ + + platformProtectST25R391xComm(); + platformSpiSelect(); + + buf[0] = ST25R3911_CMD_TEST_ACCESS; + buf[1] = (reg | ST25R3911_READ_MODE); + buf[2] = 0x00; + + platformSpiTxRx(buf, buf, 3); + + if(value != NULL) + { + *value = buf[2]; + } + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + + return; +} + +void st25r3911WriteTestRegister(uint8_t reg, uint8_t value) +{ +#ifdef ST25R391X_COM_SINGLETXRX + uint8_t* buf = comBuf; +#else /* ST25R391X_COM_SINGLETXRX */ + uint8_t buf[3]; +#endif /* ST25R391X_COM_SINGLETXRX */ + + platformProtectST25R391xComm(); + platformSpiSelect(); + + buf[0] = ST25R3911_CMD_TEST_ACCESS; + buf[1] = (reg | ST25R3911_WRITE_MODE); + buf[2] = value; + + platformSpiTxRx(buf, NULL, 3); + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + + return; +} + +void st25r3911WriteRegister(uint8_t reg, uint8_t value) +{ +#ifdef ST25R391X_COM_SINGLETXRX + uint8_t* buf = comBuf; +#else /* ST25R391X_COM_SINGLETXRX */ + uint8_t buf[2]; +#endif /* ST25R391X_COM_SINGLETXRX */ + + if (ST25R3911_REG_OP_CONTROL == reg) + { + st25r3911CheckFieldSetLED(value); + } + + platformProtectST25R391xComm(); + platformSpiSelect(); + + buf[0] = reg | ST25R3911_WRITE_MODE; + buf[1] = value; + + platformSpiTxRx(buf, NULL, 2); + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + + return; +} + +void st25r3911ClrRegisterBits( uint8_t reg, uint8_t clr_mask ) +{ + uint8_t tmp; + + st25r3911ReadRegister(reg, &tmp); + tmp &= ~clr_mask; + st25r3911WriteRegister(reg, tmp); + + return; +} + + +void st25r3911SetRegisterBits( uint8_t reg, uint8_t set_mask ) +{ + uint8_t tmp; + + st25r3911ReadRegister(reg, &tmp); + tmp |= set_mask; + st25r3911WriteRegister(reg, tmp); + + return; +} + +void st25r3911ChangeRegisterBits(uint8_t reg, uint8_t valueMask, uint8_t value) +{ + st25r3911ModifyRegister(reg, valueMask, (valueMask & value) ); +} + +void st25r3911ModifyRegister(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) +{ + uint8_t tmp; + + st25r3911ReadRegister(reg, &tmp); + + /* mask out the bits we don't want to change */ + tmp &= ~clr_mask; + /* set the new value */ + tmp |= set_mask; + st25r3911WriteRegister(reg, tmp); + + return; +} + +void st25r3911ChangeTestRegisterBits( uint8_t reg, uint8_t valueMask, uint8_t value ) +{ + uint8_t rdVal; + uint8_t wrVal; + + /* Read current reg value */ + st25r3911ReadTestRegister(reg, &rdVal); + + /* Compute new value */ + wrVal = (rdVal & ~valueMask); + wrVal |= (value & valueMask); + + /* Write new reg value */ + st25r3911WriteTestRegister(reg, wrVal ); + + return; +} + +void st25r3911WriteMultipleRegisters(uint8_t reg, const uint8_t* values, uint8_t length) +{ +#if !defined(ST25R391X_COM_SINGLETXRX) + uint8_t cmd = (reg | ST25R3911_WRITE_MODE); +#endif /* !ST25R391X_COM_SINGLETXRX */ + + if ((reg <= ST25R3911_REG_OP_CONTROL) && ((reg+length) >= ST25R3911_REG_OP_CONTROL)) + { + st25r3911CheckFieldSetLED(values[ST25R3911_REG_OP_CONTROL-reg]); + } + + if (length > 0U) + { + /* make this operation atomic */ + platformProtectST25R391xComm(); + platformSpiSelect(); + +#ifdef ST25R391X_COM_SINGLETXRX + + comBuf[0] = (reg | ST25R3911_WRITE_MODE); + ST_MEMCPY( &comBuf[ST25R3911_CMD_LEN], values, MIN( length, ST25R3911_BUF_LEN - ST25R3911_CMD_LEN ) ); + + platformSpiTxRx( comBuf, NULL, MIN( (ST25R3911_CMD_LEN + length), ST25R3911_BUF_LEN ) ); + +#else /*ST25R391X_COM_SINGLETXRX*/ + + platformSpiTxRx( &cmd, NULL, ST25R3911_CMD_LEN ); + platformSpiTxRx( values, NULL, length ); + +#endif /*ST25R391X_COM_SINGLETXRX*/ + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + } + + return; +} + + +void st25r3911WriteFifo(const uint8_t* values, uint8_t length) +{ +#if !defined(ST25R391X_COM_SINGLETXRX) + uint8_t cmd = ST25R3911_FIFO_LOAD; +#endif /* !ST25R391X_COM_SINGLETXRX */ + + if (length > 0U) + { + platformProtectST25R391xComm(); + platformSpiSelect(); + +#ifdef ST25R391X_COM_SINGLETXRX + + comBuf[0] = ST25R3911_FIFO_LOAD; + ST_MEMCPY( &comBuf[ST25R3911_CMD_LEN], values, MIN( length, ST25R3911_BUF_LEN - ST25R3911_CMD_LEN ) ); + + platformSpiTxRx( comBuf, NULL, MIN( (ST25R3911_CMD_LEN + length), ST25R3911_BUF_LEN ) ); + +#else /*ST25R391X_COM_SINGLETXRX*/ + + platformSpiTxRx( &cmd, NULL, ST25R3911_CMD_LEN ); + platformSpiTxRx( values, NULL, length ); + +#endif /*ST25R391X_COM_SINGLETXRX*/ + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + } + + return; +} + +void st25r3911ReadFifo(uint8_t* buf, uint8_t length) +{ +#if !defined(ST25R391X_COM_SINGLETXRX) + uint8_t cmd = ST25R3911_FIFO_READ; +#endif /* !ST25R391X_COM_SINGLETXRX */ + + if(length > 0U) + { + platformProtectST25R391xComm(); + platformSpiSelect(); + +#ifdef ST25R391X_COM_SINGLETXRX + + ST_MEMSET( comBuf, 0x00, MIN( (ST25R3911_CMD_LEN + (uint32_t)length), ST25R3911_BUF_LEN ) ); + comBuf[0] = ST25R3911_FIFO_READ; + + platformSpiTxRx( comBuf, comBuf, MIN( (ST25R3911_CMD_LEN + length), ST25R3911_BUF_LEN ) ); /* Transceive as a single SPI call */ + ST_MEMCPY( buf, &comBuf[ST25R3911_CMD_LEN], MIN( length, ST25R3911_BUF_LEN - ST25R3911_CMD_LEN ) ); /* Copy from local buf to output buffer and skip cmd byte */ + +#else /*ST25R391X_COM_SINGLETXRX*/ + + platformSpiTxRx( &cmd, NULL, ST25R3911_CMD_LEN ); + platformSpiTxRx( NULL, buf, length ); + +#endif /*ST25R391X_COM_SINGLETXRX*/ + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + } + + return; +} + +void st25r3911ExecuteCommand( uint8_t cmd ) +{ + uint8_t tmpCmd; /* MISRA 17.8 */ + +#ifdef PLATFORM_LED_FIELD_PIN + if ( (cmd >= ST25R3911_CMD_TRANSMIT_WITH_CRC) && (cmd <= ST25R3911_CMD_RESPONSE_RF_COLLISION_0)) + { + platformLedOff(PLATFORM_LED_FIELD_PORT, PLATFORM_LED_FIELD_PIN); + } +#endif /* PLATFORM_LED_FIELD_PIN */ + + tmpCmd = (cmd | ST25R3911_CMD_MODE); + + platformProtectST25R391xComm(); + platformSpiSelect(); + + platformSpiTxRx( &tmpCmd, NULL, ST25R3911_CMD_LEN ); + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + + return; +} + + +void st25r3911ExecuteCommands(const uint8_t *cmds, uint8_t length) +{ + platformProtectST25R391xComm(); + platformSpiSelect(); + + platformSpiTxRx(cmds, NULL, length); + + platformSpiDeselect(); + platformUnprotectST25R391xComm(); + + return; +} + +bool st25r3911IsRegValid( uint8_t reg ) +{ + if( !(( (int16_t)reg >= (int16_t)ST25R3911_REG_IO_CONF1) && (reg <= ST25R3911_REG_CAPACITANCE_MEASURE_RESULT)) && (reg != ST25R3911_REG_IC_IDENTITY) ) + { + return false; + } + return true; +} + +/* +****************************************************************************** +* LOCAL FUNCTIONS +****************************************************************************** +*/ + diff --git a/Software/fab-reader2-c/components/st25r3911/st25r3911_com.h b/Software/fab-reader2-c/components/st25r3911/st25r3911_com.h new file mode 100644 index 0000000..c5f540f --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st25r3911_com.h @@ -0,0 +1,816 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R3911 firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Ulrich Herrmann + * + * \brief ST25R3911 communication declaration file + * + */ +/*! + * This driver provides basic abstraction for communication with the ST25R3911. + * It uses the SPI driver for interfacing with the ST25R3911. + * + * API: + * - Read Register: #st25r3911ReadRegister + * - Modify Register: #st25r3911ModifyRegister + * - Write Register: #st25r3911WriteRegister + * - Write Multiple Registers: #st25r3911WriteMultipleRegisters + * - Load ST25R3911 FIFO with data: #st25r3911WriteFifo + * - Read from ST25R3911 FIFO: #st25r3911ReadFifo + * - Execute direct command: #st25r3911ExecuteCommand + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-HAL + * \brief RFAL Hardware Abstraction Layer + * @{ + * + * \addtogroup ST25R3911 + * \brief RFAL ST25R3911 Driver + * @{ + * + * \addtogroup ST25R3911_Com + * \brief RFAL ST25R3911 Communication + * @{ + * + */ + +#ifndef ST25R3911_COM_H +#define ST25R3911_COM_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" +#include "st_errno.h" + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ + +#define ST25R3911_FIFO_STATUS_LEN 2 /*!< Number of FIFO Status Register */ + + + + +#define ST25R3911_REG_IO_CONF1 0x00U /*!< RW IO Configuration Register 1 */ +#define ST25R3911_REG_IO_CONF2 0x01U /*!< RW IO Configuration Register 2 */ + +#define ST25R3911_REG_OP_CONTROL 0x02U /*!< RW Operation Control Register */ +#define ST25R3911_REG_MODE 0x03U /*!< RW Mode Definition Register */ +#define ST25R3911_REG_BIT_RATE 0x04U /*!< RW Bit Rate Definition Register */ + +#define ST25R3911_REG_ISO14443A_NFC 0x05U /*!< RW ISO14443A and NFC 106 kBit/s Settings Register */ +#define ST25R3911_REG_ISO14443B_1 0x06U /*!< RW ISO14443B Settings Register 1 */ +#define ST25R3911_REG_ISO14443B_2 0x07U /*!< RW ISO14443B Settings Register 2 */ +#define ST25R3911_REG_STREAM_MODE 0x08U /*!< RW Stream Mode Definition Register */ +#define ST25R3911_REG_AUX 0x09U /*!< RW Auxiliary Definition Register */ +#define ST25R3911_REG_RX_CONF1 0x0AU /*!< RW Receiver Configuration Register 1 */ +#define ST25R3911_REG_RX_CONF2 0x0BU /*!< RW Receiver Configuration Register 2 */ +#define ST25R3911_REG_RX_CONF3 0x0CU /*!< RW Receiver Configuration Register 3 */ +#define ST25R3911_REG_RX_CONF4 0x0DU /*!< RW Receiver Configuration Register 4 */ + +#define ST25R3911_REG_MASK_RX_TIMER 0x0EU /*!< RW Mask Receive Timer Register */ +#define ST25R3911_REG_NO_RESPONSE_TIMER1 0x0FU /*!< RW No-response Timer Register 1 */ +#define ST25R3911_REG_NO_RESPONSE_TIMER2 0x10U /*!< RW No-response Timer Register 2 */ +#define ST25R3911_REG_GPT_CONTROL 0x11U /*!< RW General Purpose Timer Control Register */ +#define ST25R3911_REG_GPT1 0x12U /*!< RW General Purpose Timer Register 1 */ +#define ST25R3911_REG_GPT2 0x13U /*!< RW General Purpose Timer Register 2 */ + +#define ST25R3911_REG_IRQ_MASK_MAIN 0x14U /*!< RW Mask Main Interrupt Register */ +#define ST25R3911_REG_IRQ_MASK_TIMER_NFC 0x15U /*!< RW Mask Timer and NFC Interrupt Register */ +#define ST25R3911_REG_IRQ_MASK_ERROR_WUP 0x16U /*!< RW Mask Error and Wake-up Interrupt Register */ +#define ST25R3911_REG_IRQ_MAIN 0x17U /*!< R Main Interrupt Register */ +#define ST25R3911_REG_IRQ_TIMER_NFC 0x18U /*!< R Timer and NFC Interrupt Register */ +#define ST25R3911_REG_IRQ_ERROR_WUP 0x19U /*!< R Error and Wake-up Interrupt Register */ +#define ST25R3911_REG_FIFO_RX_STATUS1 0x1AU /*!< R FIFO RX Status Register 1 */ +#define ST25R3911_REG_FIFO_RX_STATUS2 0x1BU /*!< R FIFO RX Status Register 2 */ +#define ST25R3911_REG_COLLISION_STATUS 0x1CU /*!< R Collision Display Register */ + +#define ST25R3911_REG_NUM_TX_BYTES1 0x1DU /*!< RW Number of Transmitted Bytes Register 1 */ +#define ST25R3911_REG_NUM_TX_BYTES2 0x1EU /*!< RW Number of Transmitted Bytes Register 2 */ + +#define ST25R3911_REG_NFCIP1_BIT_RATE 0x1FU /*!< R NFCIP Bit Rate Detection Display Register */ + +#define ST25R3911_REG_AD_RESULT 0x20U /*!< R A/D Converter Output Register */ + +#define ST25R3911_REG_ANT_CAL_CONTROL 0x21U /*!< RW Antenna Calibration Control Register */ +#define ST25R3911_REG_ANT_CAL_TARGET 0x22U /*!< RW Antenna Calibration Target Register */ +#define ST25R3911_REG_ANT_CAL_RESULT 0x23U /*!< R Antenna Calibration Display Register */ + +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL 0x24U /*!< RW AM Modulation Depth Control Register */ +#define ST25R3911_REG_AM_MOD_DEPTH_RESULT 0x25U /*!< R AM Modulation Depth Display Register */ +#define ST25R3911_REG_RFO_AM_ON_LEVEL 0x26U /*!< RW RFO AM Modulation (On) Level Definition Register */ +#define ST25R3911_REG_RFO_AM_OFF_LEVEL 0x27U /*!< RW RFO Normal (AM Off) Level Definition Register */ + +#define ST25R3911_REG_FIELD_THRESHOLD 0x29U /*!< RW External Field Detector Threshold Register */ + +#define ST25R3911_REG_REGULATOR_CONTROL 0x2AU /*!< RW Regulated Voltage Control Register */ +#define ST25R3911_REG_REGULATOR_RESULT 0x2BU /*!< R Regulator Display Register */ + +#define ST25R3911_REG_RSSI_RESULT 0x2CU /*!< R RSSI Display Register*/ +#define ST25R3911_REG_GAIN_RED_STATE 0x2DU /*!< R Gain Reduction State Register*/ + +#define ST25R3911_REG_CAP_SENSOR_CONTROL 0x2EU /*!< RW Capacitive Sensor Control Register */ +#define ST25R3911_REG_CAP_SENSOR_RESULT 0x2FU /*!< R Capacitive Sensor Display Register */ + +#define ST25R3911_REG_AUX_DISPLAY 0x30U /*!< R Auxiliary Display Register */ + +#define ST25R3911_REG_WUP_TIMER_CONTROL 0x31U /*!< RW Wake-up Timer Control Register */ +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF 0x32U /*!< RW Amplitude Measurement Configuration Register */ +#define ST25R3911_REG_AMPLITUDE_MEASURE_REF 0x33U /*!< RW Amplitude Measurement Reference Register */ +#define ST25R3911_REG_AMPLITUDE_MEASURE_AA_RESULT 0x34U /*!< R Amplitude Measurement Auto Averaging Display Register */ +#define ST25R3911_REG_AMPLITUDE_MEASURE_RESULT 0x35U /*!< R Amplitude Measurement Display Register */ +#define ST25R3911_REG_PHASE_MEASURE_CONF 0x36U /*!< RW Phase Measurement Configuration Register */ +#define ST25R3911_REG_PHASE_MEASURE_REF 0x37U /*!< RW Phase Measurement Reference Register */ +#define ST25R3911_REG_PHASE_MEASURE_AA_RESULT 0x38U /*!< R Phase Measurement Auto Averaging Display Register */ +#define ST25R3911_REG_PHASE_MEASURE_RESULT 0x39U /*!< R Phase Measurement Display Register */ +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF 0x3AU /*!< RW Capacitance Measurement Configuration Register */ +#define ST25R3911_REG_CAPACITANCE_MEASURE_REF 0x3BU /*!< RW Capacitance Measurement Reference Register */ +#define ST25R3911_REG_CAPACITANCE_MEASURE_AA_RESULT 0x3CU /*!< R Capacitance Measurement Auto Averaging Display Register */ +#define ST25R3911_REG_CAPACITANCE_MEASURE_RESULT 0x3DU /*!< R Capacitance Measurement Display Register */ + +#define ST25R3911_REG_IC_IDENTITY 0x3FU /*!< R Chip Id: 0 for old silicon, v2 silicon: 0x09 */ + + +/*! Register bit definitions \cond DOXYGEN_SUPRESS */ + +#define ST25R3911_REG_IO_CONF1_lf_clk_off (1U<<0) +#define ST25R3911_REG_IO_CONF1_out_cl0 (1U<<1) +#define ST25R3911_REG_IO_CONF1_out_cl1 (1U<<2) +#define ST25R3911_REG_IO_CONF1_mask_out_cl (3U<<1) +#define ST25R3911_REG_IO_CONF1_osc (1U<<3) +#define ST25R3911_REG_IO_CONF1_fifo_lt (1U<<4) +#define ST25R3911_REG_IO_CONF1_fifo_lt_32bytes (0U<<4) +#define ST25R3911_REG_IO_CONF1_fifo_lt_16bytes (1U<<4) +#define ST25R3911_REG_IO_CONF1_fifo_lr (1U<<5) +#define ST25R3911_REG_IO_CONF1_fifo_lr_64bytes (0U<<5) +#define ST25R3911_REG_IO_CONF1_fifo_lr_80bytes (1U<<5) +#define ST25R3911_REG_IO_CONF1_rfo2 (1U<<6) +#define ST25R3911_REG_IO_CONF1_single (1U<<7) +#define ST25R3911_REG_IO_CONF2_slow_up (1U<<0) +#define ST25R3911_REG_IO_CONF2_io_18 (1U<<2) +#define ST25R3911_REG_IO_CONF2_miso_pd1 (1U<<3) +#define ST25R3911_REG_IO_CONF2_miso_pd2 (1U<<4) +#define ST25R3911_REG_IO_CONF2_vspd_off (1U<<6) +#define ST25R3911_REG_IO_CONF2_sup3V (1U<<7) +#define ST25R3911_REG_OP_CONTROL_wu (1U<<2) +#define ST25R3911_REG_OP_CONTROL_tx_en (1U<<3) +#define ST25R3911_REG_OP_CONTROL_rx_man (1U<<4) +#define ST25R3911_REG_OP_CONTROL_rx_chn (1U<<5) +#define ST25R3911_REG_OP_CONTROL_rx_en (1U<<6) +#define ST25R3911_REG_OP_CONTROL_en (1U<<7) +#define ST25R3911_REG_MODE_nfc_ar (1U<<0) +#define ST25R3911_REG_MODE_nfc_ar_on (1U<<0) +#define ST25R3911_REG_MODE_nfc_ar_off (0U<<0) +#define ST25R3911_REG_MODE_mask_om (0xfU<<3) +#define ST25R3911_REG_MODE_om_nfc (0x0U<<3) +#define ST25R3911_REG_MODE_om_iso14443a (0x1U<<3) +#define ST25R3911_REG_MODE_om_iso14443b (0x2U<<3) +#define ST25R3911_REG_MODE_om_felica (0x3U<<3) +#define ST25R3911_REG_MODE_om_topaz (0x4U<<3) +#define ST25R3911_REG_MODE_om_subcarrier_stream (0xeU<<3) +#define ST25R3911_REG_MODE_om_bpsk_stream (0xfU<<3) +#define ST25R3911_REG_MODE_om_bit_rate_detection (0x0U<<3) +#define ST25R3911_REG_MODE_om_nfcip1_normal_mode (0x1U<<3) +#define ST25R3911_REG_MODE_targ (1U<<7) +#define ST25R3911_REG_MODE_targ_targ (1U<<7) +#define ST25R3911_REG_MODE_targ_init (0U<<7) +#define ST25R3911_REG_BIT_RATE_mask_txrate (0xfU<<4) +#define ST25R3911_REG_BIT_RATE_shift_txrate (4U) +#define ST25R3911_REG_BIT_RATE_txrate_106 (0x0U<<4) +#define ST25R3911_REG_BIT_RATE_txrate_212 (0x1U<<4) +#define ST25R3911_REG_BIT_RATE_txrate_424 (0x2U<<4) +#define ST25R3911_REG_BIT_RATE_txrate_848 (0x3U<<4) +#define ST25R3911_REG_BIT_RATE_txrate_1695 (0x4U<<4) +#define ST25R3911_REG_BIT_RATE_txrate_3390 (0x5U<<4) +#define ST25R3911_REG_BIT_RATE_txrate_6780 (0x6U<<4) +#define ST25R3911_REG_BIT_RATE_mask_rxrate (0xfU<<0) +#define ST25R3911_REG_BIT_RATE_shift_rxrate (0U) +#define ST25R3911_REG_BIT_RATE_rxrate_106 (0x0U<<0) +#define ST25R3911_REG_BIT_RATE_rxrate_212 (0x1U<<0) +#define ST25R3911_REG_BIT_RATE_rxrate_424 (0x2U<<0) +#define ST25R3911_REG_BIT_RATE_rxrate_848 (0x3U<<0) +#define ST25R3911_REG_BIT_RATE_rxrate_1695 (0x4U<<0) +#define ST25R3911_REG_BIT_RATE_rxrate_3390 (0x5U<<0) +#define ST25R3911_REG_BIT_RATE_rxrate_6780 (0x6U<<0) +#define ST25R3911_REG_ISO14443A_NFC_antcl (1U<<0) +#define ST25R3911_REG_ISO14443A_NFC_mask_p_len (0xfU<<1) +#define ST25R3911_REG_ISO14443A_NFC_shift_p_len (1U) +#define ST25R3911_REG_ISO14443A_NFC_nfc_f0 (1U<<5) +#define ST25R3911_REG_ISO14443A_NFC_nfc_f0_off (0U<<5) +#define ST25R3911_REG_ISO14443A_NFC_no_rx_par (1U<<6) +#define ST25R3911_REG_ISO14443A_NFC_no_rx_par_off (0U<<6) +#define ST25R3911_REG_ISO14443A_NFC_no_tx_par (1U<<7) +#define ST25R3911_REG_ISO14443A_NFC_no_tx_par_off (0U<<7) +#define ST25R3911_REG_ISO14443B_1_mask_eof (1U<<2) +#define ST25R3911_REG_ISO14443B_1_eof_10etu (0U<<2) +#define ST25R3911_REG_ISO14443B_1_eof_11etu (1U<<2) +#define ST25R3911_REG_ISO14443B_1_mask_sof (3U<<3) +#define ST25R3911_REG_ISO14443B_1_mask_sof_0 (1U<<4) +#define ST25R3911_REG_ISO14443B_1_sof_0_10etu (0U<<4) +#define ST25R3911_REG_ISO14443B_1_sof_0_11etu (1U<<4) +#define ST25R3911_REG_ISO14443B_1_mask_sof_1 (1U<<3) +#define ST25R3911_REG_ISO14443B_1_sof_1_2etu (0U<<3) +#define ST25R3911_REG_ISO14443B_1_sof_2_3etu (1U<<3) +#define ST25R3911_REG_ISO14443B_1_mask_egt (7U<<5) +#define ST25R3911_REG_ISO14443B_1_shift_egt (5U) +#define ST25R3911_REG_ISO14443B_2_eof_12 (1U<<3) +#define ST25R3911_REG_ISO14443B_2_eof_12_10to11etu (0U<<3) +#define ST25R3911_REG_ISO14443B_2_eof_12_10to12etu (1U<<3) +#define ST25R3911_REG_ISO14443B_2_no_eof (1U<<4) +#define ST25R3911_REG_ISO14443B_2_no_sof (1U<<5) +#define ST25R3911_REG_ISO14443B_2_mask_tr1 (3U<<6) +#define ST25R3911_REG_ISO14443B_2_shift_tr1 (6U) +#define ST25R3911_REG_ISO14443B_2_tr1_0 (1U<<6) +#define ST25R3911_REG_ISO14443B_2_tr1_1 (1U<<7) +#define ST25R3911_REG_ISO14443B_2_tr1_80fs80fs (0U<<6) +#define ST25R3911_REG_ISO14443B_2_tr1_64fs32fs (1U<<6) +#define ST25R3911_REG_STREAM_MODE_mask_stx (7U<<0) +#define ST25R3911_REG_STREAM_MODE_shift_stx (0U) +#define ST25R3911_REG_STREAM_MODE_stx_106 (0U<<0) +#define ST25R3911_REG_STREAM_MODE_stx_212 (1U<<0) +#define ST25R3911_REG_STREAM_MODE_stx_424 (2U<<0) +#define ST25R3911_REG_STREAM_MODE_stx_848 (3U<<0) +#define ST25R3911_REG_STREAM_MODE_stx_1695 (4U<<0) +#define ST25R3911_REG_STREAM_MODE_stx_3390 (5U<<0) +#define ST25R3911_REG_STREAM_MODE_stx_6780 (6U<<0) +#define ST25R3911_REG_STREAM_MODE_mask_scp (3U<<3) +#define ST25R3911_REG_STREAM_MODE_shift_scp (3U) +#define ST25R3911_REG_STREAM_MODE_scp_1pulse (0U<<3) +#define ST25R3911_REG_STREAM_MODE_scp_2pulses (1U<<3) +#define ST25R3911_REG_STREAM_MODE_scp_4pulses (2U<<3) +#define ST25R3911_REG_STREAM_MODE_scp_8pulses (3U<<3) +#define ST25R3911_REG_STREAM_MODE_mask_scf (3U<<5) +#define ST25R3911_REG_STREAM_MODE_shift_scf (5U) +#define ST25R3911_REG_STREAM_MODE_scf_bpsk848 (0U<<5) +#define ST25R3911_REG_STREAM_MODE_scf_bpsk1695 (1U<<5) +#define ST25R3911_REG_STREAM_MODE_scf_bpsk3390 (2U<<5) +#define ST25R3911_REG_STREAM_MODE_scf_bpsk106 (3U<<5) +#define ST25R3911_REG_STREAM_MODE_scf_sc212 (0U<<5) +#define ST25R3911_REG_STREAM_MODE_scf_sc424 (1U<<5) +#define ST25R3911_REG_STREAM_MODE_scf_sc848 (2U<<5) +#define ST25R3911_REG_STREAM_MODE_scf_sc1695 (3U<<5) +#define ST25R3911_REG_AUX_mask_nfc_n (3U<<0) +#define ST25R3911_REG_AUX_nfc_n0 (1U<<0) +#define ST25R3911_REG_AUX_nfc_n1 (1U<<1) +#define ST25R3911_REG_AUX_rx_tol (1U<<2) +#define ST25R3911_REG_AUX_ook_hr (1U<<3) +#define ST25R3911_REG_AUX_en_fd (1U<<4) +#define ST25R3911_REG_AUX_tr_am (1U<<5) +#define ST25R3911_REG_AUX_crc_2_fifo (1U<<6) +#define ST25R3911_REG_AUX_no_crc_rx (1U<<7) +#define ST25R3911_REG_RX_CONF1_z12k (1U<<0) +#define ST25R3911_REG_RX_CONF1_h80 (1U<<1) +#define ST25R3911_REG_RX_CONF1_h200 (1U<<2) +#define ST25R3911_REG_RX_CONF1_mask_lp (7U<<3) +#define ST25R3911_REG_RX_CONF1_lp_1200khz (0U<<3) +#define ST25R3911_REG_RX_CONF1_lp_600khz (1U<<3) +#define ST25R3911_REG_RX_CONF1_lp_300khz (2U<<3) +#define ST25R3911_REG_RX_CONF1_lp_2000khz (4U<<3) +#define ST25R3911_REG_RX_CONF1_lp_7000khz (5U<<3) +#define ST25R3911_REG_RX_CONF1_amd_sel (1U<<6) +#define ST25R3911_REG_RX_CONF1_ch_sel (1U<<7) +#define ST25R3911_REG_RX_CONF2_sqm_dyn (1U<<1) +#define ST25R3911_REG_RX_CONF2_agc_alg (1U<<2) +#define ST25R3911_REG_RX_CONF2_agc_m (1U<<3) +#define ST25R3911_REG_RX_CONF2_agc_en (1U<<4) +#define ST25R3911_REG_RX_CONF2_lf_en (1U<<5) +#define ST25R3911_REG_RX_CONF2_lf_op (1U<<6) +#define ST25R3911_REG_RX_CONF2_rx_lp (1U<<7) +#define ST25R3911_REG_RX_CONF3_rg_nfc (1U<<0) +#define ST25R3911_REG_RX_CONF3_lim (1U<<1) +#define ST25R3911_REG_RX_CONF3_shift_rg1_pm (2U) +#define ST25R3911_REG_RX_CONF3_mask_rg1_pm (0x7U<<2) +#define ST25R3911_REG_RX_CONF3_rg1_pm0 (1U<<2) +#define ST25R3911_REG_RX_CONF3_rg1_pm1 (1U<<3) +#define ST25R3911_REG_RX_CONF3_rg1_pm2 (1U<<4) +#define ST25R3911_REG_RX_CONF3_shift_rg1_am (5U) +#define ST25R3911_REG_RX_CONF3_mask_rg1_am (0x7U<<5) +#define ST25R3911_REG_RX_CONF3_rg1_am0 (1U<<5) +#define ST25R3911_REG_RX_CONF3_rg1_am1 (1U<<6) +#define ST25R3911_REG_RX_CONF3_rg1_am2 (1U<<7) +#define ST25R3911_REG_RX_CONF4_shift_rg2_pm (0U) +#define ST25R3911_REG_RX_CONF4_mask_rg2_pm (0xfU<<0) +#define ST25R3911_REG_RX_CONF4_rg2_pm0 (1U<<0) +#define ST25R3911_REG_RX_CONF4_rg2_pm1 (1U<<1) +#define ST25R3911_REG_RX_CONF4_rg2_pm2 (1U<<2) +#define ST25R3911_REG_RX_CONF4_rg2_pm3 (1U<<3) +#define ST25R3911_REG_RX_CONF4_shift_rg2_am (4U) +#define ST25R3911_REG_RX_CONF4_mask_rg2_am (0xfU<<4) +#define ST25R3911_REG_RX_CONF4_rg2_am0 (1U<<4) +#define ST25R3911_REG_RX_CONF4_rg2_am1 (1U<<5) +#define ST25R3911_REG_RX_CONF4_rg2_am2 (1U<<6) +#define ST25R3911_REG_RX_CONF4_rg2_am3 (1U<<7) +#define ST25R3911_REG_GPT_CONTROL_nrt_step (1U<<0) +#define ST25R3911_REG_GPT_CONTROL_nrt_emv (1U<<1) +#define ST25R3911_REG_GPT_CONTROL_gptc0 (1U<<5) +#define ST25R3911_REG_GPT_CONTROL_gptc1 (1U<<6) +#define ST25R3911_REG_GPT_CONTROL_gptc2 (1U<<7) +#define ST25R3911_REG_GPT_CONTROL_gptc_mask (0x7U<<5) +#define ST25R3911_REG_GPT_CONTROL_gptc_no_trigger (0x0U<<5) +#define ST25R3911_REG_GPT_CONTROL_gptc_erx (0x1U<<5) +#define ST25R3911_REG_GPT_CONTROL_gptc_srx (0x2U<<5) +#define ST25R3911_REG_GPT_CONTROL_gptc_etx_nfc (0x3U<<5) +#define ST25R3911_REG_FIFO_RX_STATUS2_np_lb (1U<<0) +#define ST25R3911_REG_FIFO_RX_STATUS2_mask_fifo_lb (7U<<1) +#define ST25R3911_REG_FIFO_RX_STATUS2_shift_fifo_lb (1U) +#define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb0 (1U<<1) +#define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb1 (1U<<2) +#define ST25R3911_REG_FIFO_RX_STATUS2_fifo_lb2 (1U<<3) +#define ST25R3911_REG_FIFO_RX_STATUS2_fifo_ncp (1U<<4) +#define ST25R3911_REG_FIFO_RX_STATUS2_fifo_ovr (1U<<5) +#define ST25R3911_REG_FIFO_RX_STATUS2_fifo_unf (1U<<6) +#define ST25R3911_REG_COLLISION_STATUS_c_pb (1U<<0) +#define ST25R3911_REG_COLLISION_STATUS_mask_c_bit (3U<<1) +#define ST25R3911_REG_COLLISION_STATUS_shift_c_bit (1U) +#define ST25R3911_REG_COLLISION_STATUS_mask_c_byte (0xfU<<4) +#define ST25R3911_REG_COLLISION_STATUS_shift_c_byte (4U) +#define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate0 (1U<<4) +#define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate1 (1U<<5) +#define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate2 (1U<<6) +#define ST25R3911_ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate3 (1U<<7) +#define ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_mask (0xfU<<4) +#define ST25R3911_REG_NFCIP1_BIT_RATE_nfc_rate_shift (4U) +#define ST25R3911_REG_ANT_CAL_CONTROL_mask_tre (0xfU<<3) +#define ST25R3911_REG_ANT_CAL_CONTROL_shift_tre (3U) +#define ST25R3911_REG_ANT_CAL_CONTROL_tre_0 (1U<<3) +#define ST25R3911_REG_ANT_CAL_CONTROL_tre_1 (1U<<4) +#define ST25R3911_REG_ANT_CAL_CONTROL_tre_2 (1U<<5) +#define ST25R3911_REG_ANT_CAL_CONTROL_tre_3 (1U<<6) +#define ST25R3911_REG_ANT_CAL_CONTROL_trim_s (1U<<7) +#define ST25R3911_REG_ANT_CAL_RESULT_tri_err (1U<<3) +#define ST25R3911_REG_ANT_CAL_RESULT_tri_0 (1U<<4) +#define ST25R3911_REG_ANT_CAL_RESULT_tri_1 (1U<<5) +#define ST25R3911_REG_ANT_CAL_RESULT_tri_2 (1U<<6) +#define ST25R3911_REG_ANT_CAL_RESULT_tri_3 (1U<<7) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mask_mod (0x3fU<<1) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_shift_mod (1U) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_8percent (0xbU<<1) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_10percent (0xeU<<1) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_14percent (0x14U<<1) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_20percent (0x20U<<1) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_25percent (0x2aU<<1) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_30percent (0x37U<<1) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_mod_33percent (0x3fU<<1) +#define ST25R3911_REG_AM_MOD_DEPTH_CONTROL_am_s (1U<<7) +#define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram0 (1U<<0) +#define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram1 (1U<<1) +#define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram2 (1U<<2) +#define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram3 (1U<<3) +#define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram4 (1U<<4) +#define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram5 (1U<<5) +#define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram6 (1U<<6) +#define ST25R3911_REG_RFO_AM_MOD_LEVEL_dram7 (1U<<7) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_t0 (1U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_t1 (1U<<1) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_t2 (1U<<2) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_t3 (1U<<3) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_l0 (1U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_l1 (1U<<5) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_l2 (1U<<6) +#define ST25R3911_REG_FIELD_THRESHOLD_mask_trg (0x07U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_75mV (0x00U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_105mV (0x01U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_150mV (0x02U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_205mV (0x03U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_290mV (0x04U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_400mV (0x05U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_560mV (0x06U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_trg_800mV (0x07U<<4) +#define ST25R3911_REG_FIELD_THRESHOLD_mask_rfe (0x0FU<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_75mV (0x00U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_105mV (0x01U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_150mV (0x02U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_205mV (0x03U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_290mV (0x04U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_400mV (0x05U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_560mV (0x06U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_800mV (0x07U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_25mV (0x08U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_33mV (0x09U<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_47mV (0x0AU<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_64mV (0x0BU<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_90mV (0x0CU<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_125mV (0x0DU<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_175mV (0x0EU<<0) +#define ST25R3911_REG_FIELD_THRESHOLD_rfe_250mV (0x0FU<<0) +#define ST25R3911_REG_REGULATOR_CONTROL_shift_mpsv (1U) +#define ST25R3911_REG_REGULATOR_CONTROL_mask_mpsv (3U<<1) +#define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vdd (0U<<1) +#define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_a (1U<<1) +#define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_d (2U<<1) +#define ST25R3911_REG_REGULATOR_CONTROL_mpsv_vsp_rf (3U<<1) +#define ST25R3911_REG_REGULATOR_CONTROL_mask_rege (0xfU<<3) +#define ST25R3911_REG_REGULATOR_CONTROL_shift_rege (3U) +#define ST25R3911_REG_REGULATOR_CONTROL_reg_s (1U<<7) +#define ST25R3911_REG_REGULATOR_RESULT_mrt_on (1U<<0) +#define ST25R3911_REG_REGULATOR_RESULT_nrt_on (1U<<1) +#define ST25R3911_REG_REGULATOR_RESULT_gpt_on (1U<<2) +#define ST25R3911_REG_REGULATOR_RESULT_mask_reg (0xfU<<4) +#define ST25R3911_REG_REGULATOR_RESULT_shift_reg (4U) +#define ST25R3911_REG_REGULATOR_RESULT_reg_0 (1U<<4) +#define ST25R3911_REG_REGULATOR_RESULT_reg_1 (1U<<5) +#define ST25R3911_REG_REGULATOR_RESULT_reg_2 (1U<<6) +#define ST25R3911_REG_REGULATOR_RESULT_reg_3 (1U<<7) +#define ST25R3911_REG_RSSI_RESULT_mask_rssi_pm (0xfU) +#define ST25R3911_REG_RSSI_RESULT_shift_rssi_pm (0U) +#define ST25R3911_REG_RSSI_RESULT_rssi_pm0 (1U<<0) +#define ST25R3911_REG_RSSI_RESULT_rssi_pm1 (1U<<1) +#define ST25R3911_REG_RSSI_RESULT_rssi_pm2 (1U<<2) +#define ST25R3911_REG_RSSI_RESULT_rssi_pm3 (1U<<3) +#define ST25R3911_REG_RSSI_RESULT_mask_rssi_am (0xfU<<4) +#define ST25R3911_REG_RSSI_RESULT_shift_rssi_am (4U) +#define ST25R3911_REG_RSSI_RESULT_rssi_am_0 (1U<<4) +#define ST25R3911_REG_RSSI_RESULT_rssi_am_1 (1U<<5) +#define ST25R3911_REG_RSSI_RESULT_rssi_am_2 (1U<<6) +#define ST25R3911_REG_RSSI_RESULT_rssi_am_3 (1U<<7) +#define ST25R3911_REG_GAIN_RED_STATE_mask_gs_pm (0xfU) +#define ST25R3911_REG_GAIN_RED_STATE_shift_gs_pm (0U) +#define ST25R3911_REG_GAIN_RED_STATE_gs_pm_0 (1U<<0) +#define ST25R3911_REG_GAIN_RED_STATE_gs_pm_1 (1U<<1) +#define ST25R3911_REG_GAIN_RED_STATE_gs_pm_2 (1U<<2) +#define ST25R3911_REG_GAIN_RED_STATE_gs_pm_3 (1U<<3) +#define ST25R3911_REG_GAIN_RED_STATE_mask_gs_am (0xfU<<4) +#define ST25R3911_REG_GAIN_RED_STATE_shift_gs_am (4U) +#define ST25R3911_REG_GAIN_RED_STATE_gs_am_0 (1U<<4) +#define ST25R3911_REG_GAIN_RED_STATE_gs_am_1 (1U<<5) +#define ST25R3911_REG_GAIN_RED_STATE_gs_am_2 (1U<<6) +#define ST25R3911_REG_GAIN_RED_STATE_gs_am_3 (1U<<7) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g0 (1U<<0) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g1 (1U<<1) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_g2 (1U<<2) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_mask_cs_g (7U<<0) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal0 (1U<<3) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal1 (1U<<4) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal2 (1U<<5) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal3 (1U<<6) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_cs_mcal4 (1U<<7) +#define ST25R3916_REG_CAP_SENSOR_CONTROL_mask_cs_mcal (0x1fU<<3) +#define ST25R3911_REG_CAP_SENSOR_CONTROL_shift_cs_mcal (3U) +#define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_err (1U<<1) +#define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal_end (1U<<2) +#define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal0 (1U<<3) +#define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal1 (1U<<4) +#define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal2 (1U<<5) +#define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal3 (1U<<6) +#define ST25R3911_REG_CAP_SENSOR_RESULT_cs_cal4 (1U<<7) +#define ST25R3911_REG_AUX_DISPLAY_mrt_on (1U<<0) +#define ST25R3911_REG_AUX_DISPLAY_nrt_on (1U<<1) +#define ST25R3911_REG_AUX_DISPLAY_gpt_on (1U<<2) +#define ST25R3911_REG_AUX_DISPLAY_rx_on (1U<<3) +#define ST25R3911_REG_AUX_DISPLAY_osc_ok (1U<<4) +#define ST25R3911_REG_AUX_DISPLAY_tx_on (1U<<5) +#define ST25R3911_REG_AUX_DISPLAY_efd_o (1U<<6) +#define ST25R3911_REG_AUX_DISPLAY_a_cha (1U<<7) +#define ST25R3911_REG_WUP_TIMER_CONTROL_wcap (1U<<0) +#define ST25R3911_REG_WUP_TIMER_CONTROL_wph (1U<<1) +#define ST25R3911_REG_WUP_TIMER_CONTROL_wam (1U<<2) +#define ST25R3911_REG_WUP_TIMER_CONTROL_wto (1U<<3) +#define ST25R3911_REG_WUP_TIMER_CONTROL_wut0 (1U<<4) +#define ST25R3911_REG_WUP_TIMER_CONTROL_wut1 (1U<<5) +#define ST25R3911_REG_WUP_TIMER_CONTROL_wut2 (1U<<6) +#define ST25R3911_REG_WUP_TIMER_CONTROL_shift_wut (4U) +#define ST25R3911_REG_WUP_TIMER_CONTROL_wur (1U<<7) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_ae (1U<<0) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aew0 (1U<<1) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aew1 (1U<<2) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_aew (1U) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_mask_am_aew (3U<<1) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_aam (1U<<3) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d0 (1U<<4) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d1 (1U<<5) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d2 (1U<<6) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_am_d3 (1U<<7) +#define ST25R3911_REG_AMPLITUDE_MEASURE_CONF_shift_am_d (4U) +#define ST25R3911_REG_PHASE_MEASURE_CONF_pm_ae (1U<<0) +#define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aew0 (1U<<1) +#define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aew1 (1U<<2) +#define ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_aew (1U) +#define ST25R3911_REG_PHASE_MEASURE_CONF_mask_pm_aew (3U<<1) +#define ST25R3911_REG_PHASE_MEASURE_CONF_pm_aam (1U<<3) +#define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d0 (1U<<4) +#define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d1 (1U<<5) +#define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d2 (1U<<6) +#define ST25R3911_REG_PHASE_MEASURE_CONF_pm_d3 (1U<<7) +#define ST25R3911_REG_PHASE_MEASURE_CONF_shift_pm_d (4U) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_ae (1U<<0) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aew0 (1U<<1) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aew1 (1U<<2) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_shift_cm_aew (1U) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_mask_cm_aew (3U<<1) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_aam (1U<<3) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d0 (1U<<4) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d1 (1U<<5) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d2 (1U<<6) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_cm_d3 (1U<<7) +#define ST25R3911_REG_CAPACITANCE_MEASURE_CONF_shift_cm_d (4U) +#define ST25R3911_REG_IC_IDENTITY_v2 (0x09U) +#define ST25R3911_REG_IC_IDENTITY_ic_type (1U<<3) +#define ST25R3911_REG_IC_IDENTITY_mask_ic_type (0x1FU<<3) +#define ST25R3911_REG_IC_IDENTITY_shift_ic_type (3U) +#define ST25R3911_REG_IC_IDENTITY_mask_ic_rev (7U) + +/*! \endcond DOXYGEN_SUPRESS */ + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ +/*! + ***************************************************************************** + * \brief Returns the content of a register within the ST25R3911 + * + * This function is used to read out the content of ST25R3911 registers. + * + * \param[in] reg: Address of register to read. + * \param[out] value: Returned value. + * + ***************************************************************************** + */ +extern void st25r3911ReadRegister(uint8_t reg, uint8_t* value); + +/*! + ***************************************************************************** + * \brief Writes a given value to a register within the ST25R3911 + * + * This function is used to write \a value to address \a reg within the ST25R3911. + * + * \param[in] reg: Address of the register to write. + * \param[in] value: Value to be written. + * + ***************************************************************************** + */ +extern void st25r3911WriteRegister(uint8_t reg, uint8_t value); + +/*! + ***************************************************************************** + * \brief Cleart bits on Register + * + * This function clears the given bitmask on the register + * + * \warning This method does not guarantee consistency of register content + * when called from multiple contexts (task, ISR, thread) + * + * \param[in] reg: Address of the register clear + * \param[in] clr_mask: Bitmask of bit to be cleared + * + ***************************************************************************** + */ +extern void st25r3911ClrRegisterBits( uint8_t reg, uint8_t clr_mask ); + + +/*! + ***************************************************************************** + * \brief Set bits on Register + * + * This function sets the given bitmask on the register + * + * \warning This method does not guarantee consistency of register content + * when called from multiple contexts (task, ISR, thread) + * + * \param[in] reg: Address of the register clear + * \param[in] set_mask: Bitmask of bit to be cleared + * + ***************************************************************************** + */ +extern void st25r3911SetRegisterBits( uint8_t reg, uint8_t set_mask ); + + +/*! + ***************************************************************************** + * \brief Changes the given bits on a ST25R3911 register + * + * This function is used if only a particular bits should be changed within + * an ST25R3911 register. + * + * \warning This method does not guarantee consistency of register content + * when called from multiple contexts (task, ISR, thread) + * + * \param[in] reg: Address of the register to write. + * \param[in] valueMask: bitmask of bits to be changed + * \param[in] value: the bits to be written on the enabled valueMask bits + * + ***************************************************************************** + */ +extern void st25r3911ChangeRegisterBits(uint8_t reg, uint8_t valueMask, uint8_t value); + +/*! + ***************************************************************************** + * \brief Read a test register within the ST25R3911 + * + * This function is used to read the content of test address \a reg within the ST25R3911. + * + * \param[in] reg: Address of the register to read. + * \param[out] value: Returned read. + * + ***************************************************************************** + */ +extern void st25r3911ReadTestRegister(uint8_t reg, uint8_t* value); + +/*! + ***************************************************************************** + * \brief Writes a given value to a test register within the ST25R3911 + * + * This function is used to write \a value to test address \a reg within the ST25R3911. + * + * \param[in] reg: Address of the register to write. + * \param[in] value: Value to be written. + * + ***************************************************************************** + */ +extern void st25r3911WriteTestRegister(uint8_t reg, uint8_t value); + +/*! + ***************************************************************************** + * \brief Modifies a value within a ST25R3911 register + * + * This function is used if only a particular bits should be changed within + * an ST25R3911 register. + * + * \warning This method does not guarantee consistency of register content + * when called from multiple contexts (task, ISR, thread) + * + * \param[in] reg: Address of the register to write. + * \param[in] clr_mask: bitmask of bits to be cleared to 0. + * \param[in] set_mask: bitmask of bits to be set to 1. + * + ***************************************************************************** + */ +extern void st25r3911ModifyRegister(uint8_t reg, uint8_t clr_mask, uint8_t set_mask); + + +/*! + ***************************************************************************** + * \brief Changes the given bits on a ST25R3911 Test register + * + * This function is used if only a particular bits should be changed within + * an ST25R3916 register. + * + * \param[in] reg: Address of the Test register to change. + * \param[in] valueMask: bitmask of bits to be changed + * \param[in] value: the bits to be written on the enabled valueMask bits + * + * \warning This method does not guarantee consistency of register content + * when called from multiple contexts (task, ISR, thread) + + * \return ERR_NONE : Operation successful + * \return ERR_PARAM : Invalid parameter + * \return ERR_SEND : Transmission error or acknowledge not received + ***************************************************************************** + */ +extern void st25r3911ChangeTestRegisterBits( uint8_t reg, uint8_t valueMask, uint8_t value ); + +/*! + ***************************************************************************** + * \brief Writes multiple values to ST25R3911 registers + * + * This function is used to write multiple values to the ST25R3911 using the + * auto-increment feature. That is, after each write the address pointer + * inside the ST25R3911 gets incremented automatically. + * + * \param[in] reg: Address of the frist register to write. + * \param[in] values: pointer to a buffer containing the values to be written. + * \param[in] length: Number of values to be written. + * + ***************************************************************************** + */ +extern void st25r3911WriteMultipleRegisters(uint8_t reg, const uint8_t* values, uint8_t length); + +/*! + ***************************************************************************** + * \brief Reads from multiple ST25R3911 registers + * + * This function is used to read from multiple registers using the + * auto-increment feature. That is, after each read the address pointer + * inside the ST25R3911 gets incremented automatically. + * + * \param[in] reg: Address of the frist register to read from. + * \param[in] values: pointer to a buffer where the result shall be written to. + * \param[in] length: Number of registers to be read out. + * + ***************************************************************************** + */ +extern void st25r3911ReadMultipleRegisters(uint8_t reg, uint8_t* values, uint8_t length); + +/*! + ***************************************************************************** + * \brief Writes values to ST25R3911 FIFO + * + * This function needs to be called in order to write to the ST25R3911 FIFO. + * + * \param[in] values: pointer to a buffer containing the values to be written + * to the FIFO. + * \param[in] length: Number of values to be written. + * + ***************************************************************************** + */ +extern void st25r3911WriteFifo(const uint8_t* values, uint8_t length); + +/*! + ***************************************************************************** + * \brief Read values from ST25R3911 FIFO + * + * This function needs to be called in order to read from ST25R3911 FIFO. + * + * \param[out] buf: pointer to a buffer where the FIFO content shall be + * written to. + * \param[in] length: Number of bytes to read. (= size of \a buf) + * \note: This function doesn't check whether \a length is really the + * number of available bytes in FIFO + * + ***************************************************************************** + */ +extern void st25r3911ReadFifo(uint8_t* buf, uint8_t length); + +/*! + ***************************************************************************** + * \brief Execute a direct command + * + * This function is used to start so-called direct command. These commands + * are implemented inside the chip and each command has unique code (see + * datasheet). + * + * \param[in] cmd : code of the direct command to be executed. + * + ***************************************************************************** + */ +extern void st25r3911ExecuteCommand(uint8_t cmd); + +/*! + ***************************************************************************** + * \brief Execute several direct commands + * + * This function is used to start so-called direct command. These commands + * are implemented inside the chip and each command has unique code (see + * datasheet). + * + * \param[in] cmds : codes of the direct command to be executed. + * \param[in] length : number of commands to be executed + * + ***************************************************************************** + */ +extern void st25r3911ExecuteCommands(const uint8_t *cmds, uint8_t length); + +/*! + ***************************************************************************** + * \brief Check if register ID is valid + * + * Checks if the given register ID a valid ST25R3911 register + * + * \param[in] reg: Address of register to check + * + * \return true if is a valid register ID + * \return false otherwise + * + ***************************************************************************** + */ +extern bool st25r3911IsRegValid( uint8_t reg ); + +#endif /* ST25R3911_COM_H */ + +/** + * @} + * + * @} + * + * @} + * + * @} + */ + diff --git a/Software/fab-reader2-c/components/st25r3911/st25r3911_interrupt.c b/Software/fab-reader2-c/components/st25r3911/st25r3911_interrupt.c new file mode 100644 index 0000000..abb3082 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st25r3911_interrupt.c @@ -0,0 +1,249 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R3911 firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Ulrich Herrmann + * + * \brief ST25R3911 Interrupt handling + * + */ + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "st25r3911_interrupt.h" +#include "st25r3911_com.h" +#include "st25r3911.h" +#include "st_errno.h" +#include "utils.h" + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ + +/*! Length of the interrupt registers */ +#define ST25R3911_INT_REGS_LEN ( (ST25R3911_REG_IRQ_ERROR_WUP - ST25R3911_REG_IRQ_MAIN) + 1U ) + +/* + ****************************************************************************** + * LOCAL DATA TYPES + ****************************************************************************** + */ + +/*! Holds current and previous interrupt callback pointer as well as current Interrupt status and mask */ +typedef struct +{ + void (*prevCallback)(void); /*!< call back function for 3911 interrupt */ + void (*callback)(void); /*!< call back function for 3911 interrupt */ + uint32_t status; /*!< latest interrupt status */ + uint32_t mask; /*!< Interrupt mask. Negative mask = ST25R3911 mask regs */ +}t_st25r3911Interrupt; + +/* +****************************************************************************** +* GLOBAL VARIABLES +****************************************************************************** +*/ + +static volatile t_st25r3911Interrupt st25r3911interrupt; /*!< Instance of ST25R3911 interrupt */ + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ +void st25r3911InitInterrupts( void ) +{ + platformIrqST25R3911PinInitialize(); + platformIrqST25R3911SetCallback( st25r3911Isr ); + + st25r3911interrupt.callback = NULL; + st25r3911interrupt.prevCallback = NULL; + st25r3911interrupt.status = ST25R3911_IRQ_MASK_NONE; + st25r3911interrupt.mask = ST25R3911_IRQ_MASK_NONE; + + /* Initialize LEDs if existing and defined */ + platformLedsInitialize(); + +#ifdef PLATFORM_LED_RX_PIN + platformLedOff( PLATFORM_LED_RX_PORT, PLATFORM_LED_RX_PIN ); +#endif /* PLATFORM_LED_RX_PIN */ + +#ifdef PLATFORM_LED_FIELD_PIN + platformLedOff( PLATFORM_LED_FIELD_PORT, PLATFORM_LED_FIELD_PIN ); +#endif /* PLATFORM_LED_FIELD_PIN */ +} + +void st25r3911Isr( void ) +{ + st25r3911CheckForReceivedInterrupts(); + + if (NULL != st25r3911interrupt.callback) + { + st25r3911interrupt.callback(); + } +} + +void st25r3911CheckForReceivedInterrupts( void ) +{ + uint8_t iregs[ST25R3911_INT_REGS_LEN]; + uint32_t irqStatus; + + irqStatus = ST25R3911_IRQ_MASK_NONE; + ST_MEMSET( iregs, (int32_t)(ST25R3911_IRQ_MASK_ALL & 0xFFU), ST25R3911_INT_REGS_LEN ); /* MISRA 10.3 */ + + /* In case the IRQ is Edge (not Level) triggered read IRQs until done */ + while( platformGpioIsHigh( ST25R391X_INT_PORT, ST25R391X_INT_PIN ) ) + { + st25r3911ReadMultipleRegisters(ST25R3911_REG_IRQ_MAIN, iregs, sizeof(iregs)); + +#ifdef PLATFORM_LED_FIELD_PIN + if ((iregs[0] & ST25R3911_IRQ_MASK_TXE) != 0U) + { + platformLedOn( PLATFORM_LED_FIELD_PORT, PLATFORM_LED_FIELD_PIN ); + } +#endif /* PLATFORM_LED_FIELD_PIN */ + +#ifdef PLATFORM_LED_RX_PIN + if ((iregs[0] & ST25R3911_IRQ_MASK_RXS) != 0) + { + platformLedOn( PLATFORM_LED_RX_PORT, PLATFORM_LED_RX_PIN ); + } + if (((iregs[0] & ST25R3911_IRQ_MASK_RXE) != 0) || ((iregs[1] & (ST25R3911_IRQ_MASK_NRE >> 8)) != 0)) /* In rare cases there is rxs but not rxe, then we have nre */ + { + platformLedOff( PLATFORM_LED_RX_PORT, PLATFORM_LED_RX_PIN ); + } +#endif /* PLATFORM_LED_RX_PIN */ + + irqStatus |= (uint32_t)iregs[0]; + irqStatus |= (uint32_t)iregs[1]<<8; + irqStatus |= (uint32_t)iregs[2]<<16; + } + + /* Forward all interrupts, even masked ones to application. */ + platformProtectST25R391xIrqStatus(); + st25r3911interrupt.status |= irqStatus; + platformUnprotectST25R391xIrqStatus(); +} + + +void st25r3911ModifyInterrupts(uint32_t clr_mask, uint32_t set_mask) +{ + uint8_t i; + uint32_t old_mask; + uint32_t new_mask; + + old_mask = st25r3911interrupt.mask; + new_mask = (~old_mask & set_mask) | (old_mask & clr_mask); + st25r3911interrupt.mask &= ~clr_mask; + st25r3911interrupt.mask |= set_mask; + for (i=0; i<3U ; i++) + { + if (((new_mask >> (i*8U)) & 0xffU) == 0U) { + continue; + } + st25r3911WriteRegister((ST25R3911_REG_IRQ_MASK_MAIN + i), (uint8_t)((st25r3911interrupt.mask>>(i*8U))&0xffU)); + } + return; +} + + +uint32_t st25r3911WaitForInterruptsTimed(uint32_t mask, uint16_t tmo) +{ + uint32_t tmr; + uint32_t status; + + tmr = platformTimerCreate(tmo); + do + { + status = (st25r3911interrupt.status & mask); + } while( ( !platformTimerIsExpired( tmr ) || (tmo == 0U)) && (status == 0U) ); + + status = st25r3911interrupt.status & mask; + + platformProtectST25R391xIrqStatus(); + st25r3911interrupt.status &= ~status; + platformUnprotectST25R391xIrqStatus(); + + return status; +} + +uint32_t st25r3911GetInterrupt(uint32_t mask) +{ + uint32_t irqs; + + irqs = (st25r3911interrupt.status & mask); + if (irqs != ST25R3911_IRQ_MASK_NONE) + { + platformProtectST25R391xIrqStatus(); + st25r3911interrupt.status &= ~irqs; + platformUnprotectST25R391xIrqStatus(); + } + return irqs; +} + +void st25r3911EnableInterrupts(uint32_t mask) +{ + st25r3911ModifyInterrupts(mask,0); +} + +void st25r3911DisableInterrupts(uint32_t mask) +{ + st25r3911ModifyInterrupts(0,mask); +} + +void st25r3911ClearInterrupts( void ) +{ + uint8_t iregs[3]; + + st25r3911ReadMultipleRegisters(ST25R3911_REG_IRQ_MAIN, iregs, 3); + + platformProtectST25R391xIrqStatus(); + st25r3911interrupt.status = 0; + platformUnprotectST25R391xIrqStatus(); + return; +} + +void st25r3911IRQCallbackSet( void (*cb)(void) ) +{ + st25r3911interrupt.prevCallback = st25r3911interrupt.callback; + st25r3911interrupt.callback = cb; +} + +void st25r3911IRQCallbackRestore( void ) +{ + st25r3911interrupt.callback = st25r3911interrupt.prevCallback; + st25r3911interrupt.prevCallback = NULL; +} + diff --git a/Software/fab-reader2-c/components/st25r3911/st25r3911_interrupt.h b/Software/fab-reader2-c/components/st25r3911/st25r3911_interrupt.h new file mode 100644 index 0000000..cbc9162 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st25r3911_interrupt.h @@ -0,0 +1,257 @@ + +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: ST25R3911 firmware + * Revision: + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Ulrich Herrmann + * + * \brief ST25R3911 Interrupt header file + * + * + * \addtogroup RFAL + * @{ + * + * \addtogroup RFAL-HAL + * \brief RFAL Hardware Abstraction Layer + * @{ + * + * \addtogroup ST25R3911 + * \brief RFAL ST25R3911 Driver + * @{ + * + * \addtogroup ST25R3911_Interrupt + * \brief RFAL ST25R3911 Interrupt + * @{ + * + */ + +#ifndef ST25R3911_INTERRUPT_H +#define ST25R3911_INTERRUPT_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ + +/* Main interrupt register. */ +#define ST25R3911_IRQ_MASK_ALL (uint32_t)(0xFFFFFFU) /*!< All ST25R3911 interrupt sources */ +#define ST25R3911_IRQ_MASK_NONE (uint32_t)(0U) /*!< No ST25R3911 interrupt source */ +#define ST25R3911_IRQ_MASK_OSC (uint32_t)(0x80U) /*!< ST25R3911 oscillator stable interrupt */ +#define ST25R3911_IRQ_MASK_FWL (uint32_t)(0x40U) /*!< ST25R3911 FIFO water level interrupt */ +#define ST25R3911_IRQ_MASK_RXS (uint32_t)(0x20U) /*!< ST25R3911 start of receive interrupt */ +#define ST25R3911_IRQ_MASK_RXE (uint32_t)(0x10U) /*!< ST25R3911 end of receive interrupt */ +#define ST25R3911_IRQ_MASK_TXE (uint32_t)(0x08U) /*!< ST25R3911 end of transmission interrupt */ +#define ST25R3911_IRQ_MASK_COL (uint32_t)(0x04U) /*!< ST25R3911 bit collision interrupt */ + +/* Timer and NFC interrupt register. */ +#define ST25R3911_IRQ_MASK_DCT (uint32_t)(0x8000U) /*!< ST25R3911 termination of direct command interrupt */ +#define ST25R3911_IRQ_MASK_NRE (uint32_t)(0x4000U) /*!< ST25R3911 no-response timer expired interrupt */ +#define ST25R3911_IRQ_MASK_GPE (uint32_t)(0x2000U) /*!< ST25R3911 general purpose timer expired interrupt */ +#define ST25R3911_IRQ_MASK_EON (uint32_t)(0x1000U) /*!< ST25R3911 external field on interrupt */ +#define ST25R3911_IRQ_MASK_EOF (uint32_t)(0x0800U) /*!< ST25R3911 external field off interrupt */ +#define ST25R3911_IRQ_MASK_CAC (uint32_t)(0x0400U) /*!< ST25R3911 collision during RF collision avoidance interrupt */ +#define ST25R3911_IRQ_MASK_CAT (uint32_t)(0x0200U) /*!< ST25R3911 minimum guard time expired interrupt */ +#define ST25R3911_IRQ_MASK_NFCT (uint32_t)(0x0100U) /*!< ST25R3911 initiator bit rate recognized interrupt */ + +/* Error and wake-up interrupt register. */ +#define ST25R3911_IRQ_MASK_CRC (uint32_t)(0x800000U) /*!< ST25R3911 CRC error interrupt */ +#define ST25R3911_IRQ_MASK_PAR (uint32_t)(0x400000U) /*!< ST25R3911 parity error interrupt */ +#define ST25R3911_IRQ_MASK_ERR2 (uint32_t)(0x200000U) /*!< ST25R3911 soft framing error interrupt */ +#define ST25R3911_IRQ_MASK_ERR1 (uint32_t)(0x100000U) /*!< ST25R3911 hard framing error interrupt */ +#define ST25R3911_IRQ_MASK_WT (uint32_t)(0x080000U) /*!< ST25R3911 wake-up interrupt */ +#define ST25R3911_IRQ_MASK_WAM (uint32_t)(0x040000U) /*!< ST25R3911 wake-up due to amplitude interrupt */ +#define ST25R3911_IRQ_MASK_WPH (uint32_t)(0x020000U) /*!< ST25R3911 wake-up due to phase interrupt */ +#define ST25R3911_IRQ_MASK_WCAP (uint32_t)(0x010000U) /*!< ST25R3911 wake-up due to capacitance measurement */ + + +#define ST25R3911_IRQ_MASK_TIM (0x02U) /*!< additional interrupts in ST25R3911_REG_IRQ_TIMER_NFC */ +#define ST25R3911_IRQ_MASK_ERR (0x01U) /*!< additional interrupts in ST25R3911_REG_IRQ_ERROR_WUP */ + + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + ***************************************************************************** + * \brief Wait until an ST25R3911 interrupt occurs + * + * This function is used to access the ST25R3911 interrupt flags. Use this + * to wait for max. \a tmo milliseconds for the \b first interrupt indicated + * with mask \a mask to occur. + * + * \param[in] mask : mask indicating the interrupts to wait for. + * \param[in] tmo : time in milliseconds until timeout occurs. If set to 0 + * the functions waits forever. + * + * \return : 0 if timeout occurred otherwise a mask indicating the cleared + * interrupts. + * + ***************************************************************************** + */ +extern uint32_t st25r3911WaitForInterruptsTimed(uint32_t mask, uint16_t tmo); + +/*! + ***************************************************************************** + * \brief Get status for the given interrupt + * + * This function is used to check whether the interrupt given by \a mask + * has occurred. If yes the interrupt gets cleared. This function returns + * only status bits which are inside \a mask. + * + * \param[in] mask : mask indicating the interrupt to check for. + * + * \return the mask of the interrupts occurred + * + ***************************************************************************** + */ +extern uint32_t st25r3911GetInterrupt(uint32_t mask); + + +/*! + ***************************************************************************** + * \brief Init the 3911 interrupt + * + * This function initiates the 3911 interrupts. + * + ***************************************************************************** + */ +extern void st25r3911InitInterrupts( void ); + + +/*! + ***************************************************************************** + * \brief Modifies the Interrupt + * + * This function modifies the interrupt + * + * \param[in] clr_mask : bit mask to be cleared on the interrupt mask + * \param[in] set_mask : bit mask to be set on the interrupt mask + ***************************************************************************** + */ +extern void st25r3911ModifyInterrupts(uint32_t clr_mask, uint32_t set_mask); + + +/*! + ***************************************************************************** + * \brief Checks received interrupts + * + * Checks received interrupts and saves the result into global params + ***************************************************************************** + */ +extern void st25r3911CheckForReceivedInterrupts( void ); + + +/*! + ***************************************************************************** + * \brief ISR Service routine + * + * This function modifies the interrupt + ***************************************************************************** + */ +extern void st25r3911Isr( void ); + +/*! + ***************************************************************************** + * \brief Enable a given ST25R3911 Interrupt source + * + * This function enables all interrupts given by \a mask, + * ST25R3911_IRQ_MASK_ALL enables all interrupts. + * + * \param[in] mask: mask indicating the interrupts to be enabled + * + ***************************************************************************** + */ +extern void st25r3911EnableInterrupts(uint32_t mask); + +/*! + ***************************************************************************** + * \brief Disable one or more a given ST25R3911 Interrupt sources + * + * This function disables all interrupts given by \a mask. 0xff disables all. + * + * \param[in] mask: mask indicating the interrupts to be disabled. + * + ***************************************************************************** + */ +extern void st25r3911DisableInterrupts(uint32_t mask); + +/*! + ***************************************************************************** + * \brief Clear all st25r3911 irq flags + * + ***************************************************************************** + */ +extern void st25r3911ClearInterrupts(void); + +/*! + ***************************************************************************** + * \brief Sets IRQ callback for the ST25R3911 interrupt + * + ***************************************************************************** + */ +extern void st25r3911IRQCallbackSet(void (*cb)(void)); + +/*! + ***************************************************************************** + * \brief Sets IRQ callback for the ST25R3911 interrupt + * + ***************************************************************************** + */ +extern void st25r3911IRQCallbackRestore(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ST25R3911_ISR_H */ + +/** + * @} + * + * @} + * + * @} + * + * @} + */ diff --git a/Software/fab-reader2-c/components/st25r3911/st25r3911_spi.c b/Software/fab-reader2-c/components/st25r3911/st25r3911_spi.c new file mode 100644 index 0000000..67b9dd8 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st25r3911_spi.c @@ -0,0 +1,34 @@ +// +// Created by Kai Jan Kriegel on 12.10.22. +// + +#include +#include +#include "st25r3911_spi.h" +#include "platform.h" + +spi_device_handle_t pSpi; +#define SPI_BUF_LEN 32 + +void st25r3911_spi_init(spi_device_handle_t spi) { + pSpi = spi; +} + +esp_err_t st25r3911_spiTxRx(const uint8_t *txData, uint8_t *rxData, uint16_t length) { + if (length > SPI_BUF_LEN) { + return ESP_FAIL; + } + + spi_transaction_t t; + memset(&t, 0, sizeof(t)); + t.length = length * 8; + t.rx_buffer = rxData; + t.tx_buffer = txData; + + esp_err_t ret = spi_device_polling_transmit(pSpi, &t); + ESP_ERROR_CHECK(ret); + + return ret; +} + + diff --git a/Software/fab-reader2-c/components/st25r3911/st25r3911_spi.h b/Software/fab-reader2-c/components/st25r3911/st25r3911_spi.h new file mode 100644 index 0000000..de52750 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st25r3911_spi.h @@ -0,0 +1,23 @@ +// +// Created by Kai Jan Kriegel on 12.10.22. +// + +#ifndef FAB_READER2_C_ST25R3911_SPI_H +#define FAB_READER2_C_ST25R3911_SPI_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void st25r3911_spi_init(spi_device_handle_t spi); + +esp_err_t st25r3911_spiTxRx(const uint8_t *txData, uint8_t *rxData, uint16_t length); + +#ifdef __cplusplus +} +#endif + +#endif //FAB_READER2_C_ST25R3911_SPI_H diff --git a/Software/fab-reader2-c/components/st25r3911/st_errno.h b/Software/fab-reader2-c/components/st25r3911/st_errno.h new file mode 100644 index 0000000..aa2da83 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/st_errno.h @@ -0,0 +1,164 @@ +/****************************************************************************** + * \attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: STxxxx firmware + * LANGUAGE: ISO C99 + */ + +/*! \file st_errno.h + * + * \author + * + * \brief Main error codes + * + */ + +#ifndef ST_ERRNO_H +#define ST_ERRNO_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ + + +/* +****************************************************************************** +* GLOBAL DATA TYPES +****************************************************************************** +*/ + +typedef uint16_t ReturnCode; /*!< Standard Return Code type from function. */ + +/* +****************************************************************************** +* DEFINES +****************************************************************************** +*/ + + +/* + * Error codes to be used within the application. + * They are represented by an uint8_t + */ + +#define ERR_NONE ((ReturnCode)0U) /*!< no error occurred */ +#define ERR_NOMEM ((ReturnCode)1U) /*!< not enough memory to perform the requested operation */ +#define ERR_BUSY ((ReturnCode)2U) /*!< device or resource busy */ +#define ERR_IO ((ReturnCode)3U) /*!< generic IO error */ +#define ERR_TIMEOUT ((ReturnCode)4U) /*!< error due to timeout */ +#define ERR_REQUEST ((ReturnCode)5U) /*!< invalid request or requested function can't be executed at the moment */ +#define ERR_NOMSG ((ReturnCode)6U) /*!< No message of desired type */ +#define ERR_PARAM ((ReturnCode)7U) /*!< Parameter error */ +#define ERR_SYSTEM ((ReturnCode)8U) /*!< System error */ +#define ERR_FRAMING ((ReturnCode)9U) /*!< Framing error */ +#define ERR_OVERRUN ((ReturnCode)10U) /*!< lost one or more received bytes */ +#define ERR_PROTO ((ReturnCode)11U) /*!< protocol error */ +#define ERR_INTERNAL ((ReturnCode)12U) /*!< Internal Error */ +#define ERR_AGAIN ((ReturnCode)13U) /*!< Call again */ +#define ERR_MEM_CORRUPT ((ReturnCode)14U) /*!< memory corruption */ +#define ERR_NOT_IMPLEMENTED ((ReturnCode)15U) /*!< not implemented */ +#define ERR_PC_CORRUPT ((ReturnCode)16U) /*!< Program Counter has been manipulated or spike/noise trigger illegal operation */ +#define ERR_SEND ((ReturnCode)17U) /*!< error sending*/ +#define ERR_IGNORE ((ReturnCode)18U) /*!< indicates error detected but to be ignored */ +#define ERR_SEMANTIC ((ReturnCode)19U) /*!< indicates error in state machine (unexpected cmd) */ +#define ERR_SYNTAX ((ReturnCode)20U) /*!< indicates error in state machine (unknown cmd) */ +#define ERR_CRC ((ReturnCode)21U) /*!< crc error */ +#define ERR_NOTFOUND ((ReturnCode)22U) /*!< transponder not found */ +#define ERR_NOTUNIQUE ((ReturnCode)23U) /*!< transponder not unique - more than one transponder in field */ +#define ERR_NOTSUPP ((ReturnCode)24U) /*!< requested operation not supported */ +#define ERR_WRITE ((ReturnCode)25U) /*!< write error */ +#define ERR_FIFO ((ReturnCode)26U) /*!< fifo over or underflow error */ +#define ERR_PAR ((ReturnCode)27U) /*!< parity error */ +#define ERR_DONE ((ReturnCode)28U) /*!< transfer has already finished */ +#define ERR_RF_COLLISION ((ReturnCode)29U) /*!< collision error (Bit Collision or during RF Collision avoidance ) */ +#define ERR_HW_OVERRUN ((ReturnCode)30U) /*!< lost one or more received bytes */ +#define ERR_RELEASE_REQ ((ReturnCode)31U) /*!< device requested release */ +#define ERR_SLEEP_REQ ((ReturnCode)32U) /*!< device requested sleep */ +#define ERR_WRONG_STATE ((ReturnCode)33U) /*!< incorrent state for requested operation */ +#define ERR_MAX_RERUNS ((ReturnCode)34U) /*!< blocking procedure reached maximum runs */ +#define ERR_DISABLED ((ReturnCode)35U) /*!< operation aborted due to disabled configuration */ +#define ERR_HW_MISMATCH ((ReturnCode)36U) /*!< expected hw do not match */ +#define ERR_LINK_LOSS ((ReturnCode)37U) /*!< Other device's field didn't behave as expected: turned off by Initiator in Passive mode, or AP2P did not turn on field */ +#define ERR_INVALID_HANDLE ((ReturnCode)38U) /*!< invalid or not initalized device handle */ + +#define ERR_INCOMPLETE_BYTE ((ReturnCode)40U) /*!< Incomplete byte rcvd */ +#define ERR_INCOMPLETE_BYTE_01 ((ReturnCode)41U) /*!< Incomplete byte rcvd - 1 bit */ +#define ERR_INCOMPLETE_BYTE_02 ((ReturnCode)42U) /*!< Incomplete byte rcvd - 2 bit */ +#define ERR_INCOMPLETE_BYTE_03 ((ReturnCode)43U) /*!< Incomplete byte rcvd - 3 bit */ +#define ERR_INCOMPLETE_BYTE_04 ((ReturnCode)44U) /*!< Incomplete byte rcvd - 4 bit */ +#define ERR_INCOMPLETE_BYTE_05 ((ReturnCode)45U) /*!< Incomplete byte rcvd - 5 bit */ +#define ERR_INCOMPLETE_BYTE_06 ((ReturnCode)46U) /*!< Incomplete byte rcvd - 6 bit */ +#define ERR_INCOMPLETE_BYTE_07 ((ReturnCode)47U) /*!< Incomplete byte rcvd - 7 bit */ + + + + +/* General Sub-category number */ +#define ERR_GENERIC_GRP (0x0000) /*!< Reserved value for generic error no */ +#define ERR_WARN_GRP (0x0100) /*!< Errors which are not expected in normal operation */ +#define ERR_PROCESS_GRP (0x0200) /*!< Processes management errors */ +#define ERR_SIO_GRP (0x0800) /*!< SIO errors due to logging */ +#define ERR_RINGBUF_GRP (0x0900) /*!< Ring Buffer errors */ +#define ERR_MQ_GRP (0x0A00) /*!< MQ errors */ +#define ERR_TIMER_GRP (0x0B00) /*!< Timer errors */ +#define ERR_RFAL_GRP (0x0C00) /*!< RFAL errors */ +#define ERR_UART_GRP (0x0D00) /*!< UART errors */ +#define ERR_SPI_GRP (0x0E00) /*!< SPI errors */ +#define ERR_I2C_GRP (0x0F00) /*!< I2c errors */ + + +#define ERR_INSERT_SIO_GRP(x) (ERR_SIO_GRP | (x)) /*!< Insert the SIO grp */ +#define ERR_INSERT_RINGBUF_GRP(x) (ERR_RINGBUF_GRP | (x)) /*!< Insert the Ring Buffer grp */ +#define ERR_INSERT_RFAL_GRP(x) (ERR_RFAL_GRP | (x)) /*!< Insert the RFAL grp */ +#define ERR_INSERT_SPI_GRP(x) (ERR_SPI_GRP | (x)) /*!< Insert the spi grp */ +#define ERR_INSERT_I2C_GRP(x) (ERR_I2C_GRP | (x)) /*!< Insert the i2c grp */ +#define ERR_INSERT_UART_GRP(x) (ERR_UART_GRP | (x)) /*!< Insert the uart grp */ +#define ERR_INSERT_TIMER_GRP(x) (ERR_TIMER_GRP | (x)) /*!< Insert the timer grp */ +#define ERR_INSERT_MQ_GRP(x) (ERR_MQ_GRP | (x)) /*!< Insert the mq grp */ +#define ERR_INSERT_PROCESS_GRP(x) (ERR_PROCESS_GRP | (x)) /*!< Insert the process grp */ +#define ERR_INSERT_WARN_GRP(x) (ERR_WARN_GRP | (x)) /*!< Insert the i2c grp */ +#define ERR_INSERT_GENERIC_GRP(x) (ERR_GENERIC_GRP | (x)) /*!< Insert the generic grp */ + + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ + +#define ERR_NO_MASK(x) ((uint16_t)(x) & 0x00FFU) /*!< Mask the error number */ + + + +/*! Common code to exit a function with the error if function f return error */ +#define EXIT_ON_ERR(r, f) \ + (r) = (f); \ + if (ERR_NONE != (r)) \ + { \ + return (r); \ + } + +#endif /* ST_ERRNO_H */ + diff --git a/Software/fab-reader2-c/components/st25r3911/timer.c b/Software/fab-reader2-c/components/st25r3911/timer.c new file mode 100644 index 0000000..b13c7a5 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/timer.c @@ -0,0 +1,121 @@ +/****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ +/* + * PROJECT: ST25R391x firmware + * $Revision: $ + * LANGUAGE: ANSI C + */ + +/*! \file timer.c + * + * \brief SW Timer implementation + * + * \author Gustavo Patricio + * + * This module makes use of a System Tick in millisconds and provides + * an abstraction for SW timers + * + */ + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "timer.h" + + +/* +****************************************************************************** +* LOCAL DEFINES +****************************************************************************** +*/ + +/* +****************************************************************************** +* LOCAL VARIABLES +****************************************************************************** +*/ + +static uint32_t timerStopwatchTick; + +/* +****************************************************************************** +* GLOBAL FUNCTIONS +****************************************************************************** +*/ + + +/*******************************************************************************/ +uint32_t timerCalculateTimer( uint16_t time ) +{ + return (platformGetSysTick() + time); +} + + +/*******************************************************************************/ +bool timerIsExpired( uint32_t timer ) +{ + uint32_t uDiff; + int32_t sDiff; + + uDiff = (timer - platformGetSysTick()); /* Calculate the diff between the timers */ + sDiff = uDiff; /* Convert the diff to a signed var */ + /* Having done this has two side effects: + * 1) all differences smaller than -(2^31) ms (~25d) will become positive + * Signaling not expired: acceptable! + * 2) Time roll-over case will be handled correctly: super! + */ + + /* Check if the given timer has expired already */ + if( sDiff < 0 ) + { + return true; + } + + return false; +} + + +/*******************************************************************************/ +void timerDelay( uint16_t tOut ) +{ + uint32_t t; + + /* Calculate the timer and wait blocking until is running */ + t = timerCalculateTimer( tOut ); + while( timerIsRunning(t) ); +} + + +/*******************************************************************************/ +void timerStopwatchStart( void ) +{ + timerStopwatchTick = platformGetSysTick(); +} + + +/*******************************************************************************/ +uint32_t timerStopwatchMeasure( void ) +{ + return (uint32_t)(platformGetSysTick() - timerStopwatchTick); +} + diff --git a/Software/fab-reader2-c/components/st25r3911/timer.h b/Software/fab-reader2-c/components/st25r3911/timer.h new file mode 100644 index 0000000..4446d45 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/timer.h @@ -0,0 +1,128 @@ +/****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ +/* + * PROJECT: ST25R391x firmware + * $Revision: $ + * LANGUAGE: ANSI C + */ + +/*! \file timer.h + * + * \brief SW Timer implementation header file + * + * This module makes use of a System Tick in millisconds and provides + * an abstraction for SW timers + * + */ + + + /* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include "platform.h" + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ +#define timerIsRunning(t) (!timerIsExpired(t)) + +/* +****************************************************************************** +* GLOBAL DEFINES +****************************************************************************** +*/ + + /*! + ***************************************************************************** + * \brief Calculate Timer + * + * This method calculates when the timer will be expired given the amount + * time in milliseconds /a tOut. + * Once the timer has been calculated it will then be used to check when + * it expires. + * + * \see timersIsExpired + * + * \param[in] time : time/duration in Milliseconds for the timer + * + * \return u32 : The new timer calculated based on the given time + ***************************************************************************** + */ +uint32_t timerCalculateTimer( uint16_t time ); + + +/*! + ***************************************************************************** + * \brief Checks if a Timer is Expired + * + * This method checks if a timer has already expired. + * Based on the given timer previously calculated it checks if this timer + * has already elapsed + * + * \see timersCalculateTimer + * + * \param[in] timer : the timer to check + * + * \return true : timer has already expired + * \return false : timer is still running + ***************************************************************************** + */ +bool timerIsExpired( uint32_t timer ); + + + /*! + ***************************************************************************** + * \brief Performs a Delay + * + * This method performs a delay for the given amount of time in Milliseconds + * + * \param[in] time : time/duration in Milliseconds of the delay + * + ***************************************************************************** + */ +void timerDelay( uint16_t time ); + + +/*! + ***************************************************************************** + * \brief Stopwatch start + * + * This method initiates the stopwatch to later measure the time in ms + * + ***************************************************************************** + */ +void timerStopwatchStart( void ); + + +/*! + ***************************************************************************** + * \brief Stopwatch Measure + * + * This method returns the elapsed time in ms since the stopwatch was initiated + * + * \return The time in ms since the stopwatch was started + ***************************************************************************** + */ +uint32_t timerStopwatchMeasure( void ); diff --git a/Software/fab-reader2-c/components/st25r3911/utils.c b/Software/fab-reader2-c/components/st25r3911/utils.c new file mode 100644 index 0000000..e1fb0b6 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/utils.c @@ -0,0 +1,41 @@ +// +// Created by Kai Jan Kriegel on 17.10.22. +// + +#include "utils.h" + +#define MAX_HEX_STR 4 +#define MAX_HEX_STR_LENGTH 128 +char hexStr[MAX_HEX_STR][MAX_HEX_STR_LENGTH]; +uint8_t hexStrIdx = 0; + +char *hex2Str(unsigned char *data, size_t dataLen) { + { + unsigned char *pin = data; + const char *hex = "0123456789ABCDEF"; + char *pout = hexStr[hexStrIdx]; + uint8_t i = 0; + uint8_t idx = hexStrIdx; + size_t len; + + if (dataLen == 0) { + pout[0] = 0; + } else { + /* Trim data that doesn't fit in buffer */ + len = MIN(dataLen, (MAX_HEX_STR_LENGTH / 2)); + + for (; i < (len - 1); ++i) { + *pout++ = hex[(*pin >> 4) & 0xF]; + *pout++ = hex[(*pin++) & 0xF]; + } + *pout++ = hex[(*pin >> 4) & 0xF]; + *pout++ = hex[(*pin) & 0xF]; + *pout = 0; + } + + hexStrIdx++; + hexStrIdx %= MAX_HEX_STR; + + return hexStr[idx]; + } +} \ No newline at end of file diff --git a/Software/fab-reader2-c/components/st25r3911/utils.h b/Software/fab-reader2-c/components/st25r3911/utils.h new file mode 100644 index 0000000..9df9312 --- /dev/null +++ b/Software/fab-reader2-c/components/st25r3911/utils.h @@ -0,0 +1,113 @@ + +/****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Licensed under ST MYLIBERTY SOFTWARE LICENSE AGREEMENT (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * www.st.com/myliberty + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, + * AND SPECIFICALLY DISCLAIMING THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. + * See the License for the specific language governing permissions and + * limitations under the License. + * +******************************************************************************/ + + +/* + * PROJECT: NFCC firmware + * $Revision: $ + * LANGUAGE: ISO C99 + */ + +/*! \file + * + * \author Ulrich Herrmann + * + * \brief Common and helpful macros + * + */ + +#ifndef UTILS_H +#define UTILS_H + +/* +****************************************************************************** +* INCLUDES +****************************************************************************** +*/ +#include + +/* +****************************************************************************** +* GLOBAL MACROS +****************************************************************************** +*/ +/*! + * this macro evaluates an error variable \a ERR against an error code \a EC. + * in case it is not equal it jumps to the given label \a LABEL. + */ +#define EVAL_ERR_NE_GOTO(EC, ERR, LABEL) \ + if ((EC) != (ERR)) goto LABEL; + +/*! + * this macro evaluates an error variable \a ERR against an error code \a EC. + * in case it is equal it jumps to the given label \a LABEL. + */ +#define EVAL_ERR_EQ_GOTO(EC, ERR, LABEL) \ + if ((EC) == (ERR)) goto LABEL; + +#define SIZEOF_ARRAY(a) (sizeof(a) / sizeof((a)[0])) /*!< Compute the size of an array */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) /*!< Return the maximum of the 2 values */ +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< Return the minimum of the 2 values */ +#define BITMASK_1 (0x01) /*!< Bit mask for lsb bit */ +#define BITMASK_2 (0x03) /*!< Bit mask for two lsb bits */ +#define BITMASK_3 (0x07) /*!< Bit mask for three lsb bits */ +#define BITMASK_4 (0x0F) /*!< Bit mask for four lsb bits */ +#define U16TOU8(a) ((a) & 0x00FF) /*!< Cast 16-bit unsigned to 8-bit unsigned */ +#define GETU16(a) (((uint16_t)(a)[0] << 8) | (uint16_t)(a)[1])/*!< Cast two Big Endian 8-bits byte array to 16-bits unsigned */ +#define GETU32(a) (((uint32_t)(a)[0] << 24) | ((uint32_t)(a)[1] << 16) | ((uint32_t)(a)[2] << 8) | ((uint32_t)(a)[3])) /*!< Cast four Big Endian 8-bit byte array to 32-bit unsigned */ + +#define REVERSE_BYTES(pData, nDataSize) \ + {unsigned char swap, *lo = ((unsigned char *)(pData)), *hi = ((unsigned char *)(pData)) + (nDataSize) - 1; \ + while (lo < hi) { swap = *lo; *lo++ = *hi; *hi-- = swap; }} + +#ifdef __CSMC__ +/* STM8 COSMIC */ +#define ST_MEMMOVE(s1,s2,n) memmove(s1,s2,n) /*!< map memmove to string library code */ +static inline void * ST_MEMCPY(void *s1, const void *s2, uint32_t n) { return memcpy(s1,s2,(uint16_t)n); } /* PRQA S 0431 # MISRA 1.1 - string.h from Cosmic only provides functions with low qualified parameters */ +#define ST_MEMSET(s1,c,n) memset(s1,(char)(c),n) /*!< map memset to string library code */ +static inline int32_t ST_BYTECMP(void *s1, const void *s2, uint32_t n) { return (int32_t)memcmp(s1,s2,(uint16_t)n); } /* PRQA S 0431 # MISRA 1.1 - string.h from Cosmic only provides functions with low qualified parameters */ + +#else /* __CSMC__ */ + +#define ST_MEMMOVE memmove /*!< map memmove to string library code */ +#define ST_MEMCPY memcpy /*!< map memcpy to string library code */ +#define ST_MEMSET memset /*!< map memset to string library code */ +#define ST_BYTECMP memcmp /*!< map bytecmp to string library code */ +#endif /* __CSMC__ */ + +#define NO_WARNING(v) ((void) (v)) /*!< Macro to suppress compiler warning */ + + +#ifndef NULL +#define NULL (void*)0 /*!< represents a NULL pointer */ +#endif /* !NULL */ + +/* +****************************************************************************** +* GLOBAL FUNCTION PROTOTYPES +****************************************************************************** +*/ + +char *hex2Str(unsigned char *data, size_t dataLen); + +#endif /* UTILS_H */ + diff --git a/Software/fab-reader2-c/esp32s3.svd b/Software/fab-reader2-c/esp32s3.svd new file mode 100644 index 0000000..df32749 --- /dev/null +++ b/Software/fab-reader2-c/esp32s3.svd @@ -0,0 +1,59821 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-S3 + ESP32-S3 + 10 + 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) + + Copyright 2022 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + + Xtensa LX7 + r0p0 + little + false + true + 3 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x6003A000 + + 0x0 + 0xB8 + registers + + + AES + 77 + + + + 8 + 0x4 + KEY_%s + AES key register %s + 0x0 + 0x20 + + + KEY_0 + Stores AES keys. + 0 + 32 + read-write + + + + + 4 + 0x4 + TEXT_IN_%s + Source data register %s + 0x20 + 0x20 + + + TEXT_IN_0 + Stores the source data when the AES accelerator operates in the Typical AES working mode. + 0 + 32 + read-write + + + + + 4 + 0x4 + TEXT_OUT_%s + Result data register %s + 0x30 + 0x20 + + + TEXT_OUT_0 + Stores the result data when the AES accelerator operates in the Typical AES working mode. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + Defines the key length and the encryption/decryption of the AES accelerator. + 0 + 3 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to 1 to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 16 + 0x1 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x8 + + + 16 + 0x1 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x8 + + + 16 + 0x1 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x8 + + + 16 + 0x1 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x8 + + + DMA_ENABLE + AES accelerator working mode register + 0x90 + 0x20 + + + DMA_ENABLE + Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to 1 to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to 1 to clear AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + DMA-AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation. + 0 + 1 + write-only + + + + + + + APB_CTRL + Advanced Peripheral Bus Controller + APB_CTRL + 0x60026000 + + 0x0 + 0xCC + registers + + + + SYSCLK_CONF + ******* Description *********** + 0x0 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + ******* Description *********** + 0 + 10 + read-write + + + CLK_320M_EN + ******* Description *********** + 10 + 1 + read-write + + + CLK_EN + ******* Description *********** + 11 + 1 + read-write + + + RST_TICK_CNT + ******* Description *********** + 12 + 1 + read-write + + + + + TICK_CONF + ******* Description *********** + 0x4 + 0x20 + 0x00010727 + + + XTAL_TICK_NUM + ******* Description *********** + 0 + 8 + read-write + + + CK8M_TICK_NUM + ******* Description *********** + 8 + 8 + read-write + + + TICK_ENABLE + ******* Description *********** + 16 + 1 + read-write + + + + + CLK_OUT_EN + ******* Description *********** + 0x8 + 0x20 + 0x000007FF + + + CLK20_OEN + ******* Description *********** + 0 + 1 + read-write + + + CLK22_OEN + ******* Description *********** + 1 + 1 + read-write + + + CLK44_OEN + ******* Description *********** + 2 + 1 + read-write + + + CLK_BB_OEN + ******* Description *********** + 3 + 1 + read-write + + + CLK80_OEN + ******* Description *********** + 4 + 1 + read-write + + + CLK160_OEN + ******* Description *********** + 5 + 1 + read-write + + + CLK_320M_OEN + ******* Description *********** + 6 + 1 + read-write + + + CLK_ADC_INF_OEN + ******* Description *********** + 7 + 1 + read-write + + + CLK_DAC_CPU_OEN + ******* Description *********** + 8 + 1 + read-write + + + CLK40X_BB_OEN + ******* Description *********** + 9 + 1 + read-write + + + CLK_XTAL_OEN + ******* Description *********** + 10 + 1 + read-write + + + + + WIFI_BB_CFG + ******* Description *********** + 0xC + 0x20 + + + WIFI_BB_CFG + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_BB_CFG_2 + ******* Description *********** + 0x10 + 0x20 + + + WIFI_BB_CFG_2 + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_CLK_EN + ******* Description *********** + 0x14 + 0x20 + 0xFFFCE030 + + + WIFI_CLK_EN + ******* Description *********** + 0 + 32 + read-write + + + + + WIFI_RST_EN + ******* Description *********** + 0x18 + 0x20 + + + WIFI_RST + ******* Description *********** + 0 + 32 + read-write + + + + + HOST_INF_SEL + ******* Description *********** + 0x1C + 0x20 + + + PERI_IO_SWAP + ******* Description *********** + 0 + 8 + read-write + + + + + EXT_MEM_PMS_LOCK + ******* Description *********** + 0x20 + 0x20 + + + EXT_MEM_PMS_LOCK + ******* Description *********** + 0 + 1 + read-write + + + + + EXT_MEM_WRITEBACK_BYPASS + ******* Description *********** + 0x24 + 0x20 + + + WRITEBACK_BYPASS + Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute. + 0 + 1 + read-write + + + + + FLASH_ACE0_ATTR + ******* Description *********** + 0x28 + 0x20 + 0x000000FF + + + FLASH_ACE0_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE1_ATTR + ******* Description *********** + 0x2C + 0x20 + 0x000000FF + + + FLASH_ACE1_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE2_ATTR + ******* Description *********** + 0x30 + 0x20 + 0x000000FF + + + FLASH_ACE2_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE3_ATTR + ******* Description *********** + 0x34 + 0x20 + 0x000000FF + + + FLASH_ACE3_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + FLASH_ACE0_ADDR + ******* Description *********** + 0x38 + 0x20 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE1_ADDR + ******* Description *********** + 0x3C + 0x20 + 0x10000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE2_ADDR + ******* Description *********** + 0x40 + 0x20 + 0x20000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE3_ADDR + ******* Description *********** + 0x44 + 0x20 + 0x30000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + FLASH_ACE0_SIZE + ******* Description *********** + 0x48 + 0x20 + 0x00001000 + + + FLASH_ACE0_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE1_SIZE + ******* Description *********** + 0x4C + 0x20 + 0x00001000 + + + FLASH_ACE1_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE2_SIZE + ******* Description *********** + 0x50 + 0x20 + 0x00001000 + + + FLASH_ACE2_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + FLASH_ACE3_SIZE + ******* Description *********** + 0x54 + 0x20 + 0x00001000 + + + FLASH_ACE3_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE0_ATTR + ******* Description *********** + 0x58 + 0x20 + 0x000000FF + + + SRAM_ACE0_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE1_ATTR + ******* Description *********** + 0x5C + 0x20 + 0x000000FF + + + SRAM_ACE1_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE2_ATTR + ******* Description *********** + 0x60 + 0x20 + 0x000000FF + + + SRAM_ACE2_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE3_ATTR + ******* Description *********** + 0x64 + 0x20 + 0x000000FF + + + SRAM_ACE3_ATTR + ******* Description *********** + 0 + 9 + read-write + + + + + SRAM_ACE0_ADDR + ******* Description *********** + 0x68 + 0x20 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE1_ADDR + ******* Description *********** + 0x6C + 0x20 + 0x10000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE2_ADDR + ******* Description *********** + 0x70 + 0x20 + 0x20000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE3_ADDR + ******* Description *********** + 0x74 + 0x20 + 0x30000000 + + + S + ******* Description *********** + 0 + 32 + read-write + + + + + SRAM_ACE0_SIZE + ******* Description *********** + 0x78 + 0x20 + 0x00001000 + + + SRAM_ACE0_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE1_SIZE + ******* Description *********** + 0x7C + 0x20 + 0x00001000 + + + SRAM_ACE1_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE2_SIZE + ******* Description *********** + 0x80 + 0x20 + 0x00001000 + + + SRAM_ACE2_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SRAM_ACE3_SIZE + ******* Description *********** + 0x84 + 0x20 + 0x00001000 + + + SRAM_ACE3_SIZE + ******* Description *********** + 0 + 16 + read-write + + + + + SPI_MEM_PMS_CTRL + ******* Description *********** + 0x88 + 0x20 + + + SPI_MEM_REJECT_INT + ******* Description *********** + 0 + 1 + read-only + + + SPI_MEM_REJECT_CLR + ******* Description *********** + 1 + 1 + write-only + + + SPI_MEM_REJECT_CDE + ******* Description *********** + 2 + 5 + read-only + + + + + SPI_MEM_REJECT_ADDR + ******* Description *********** + 0x8C + 0x20 + + + SPI_MEM_REJECT_ADDR + ******* Description *********** + 0 + 32 + read-only + + + + + SDIO_CTRL + ******* Description *********** + 0x90 + 0x20 + + + SDIO_WIN_ACCESS_EN + ******* Description *********** + 0 + 1 + read-write + + + + + REDCY_SIG0 + ******* Description *********** + 0x94 + 0x20 + + + REDCY_SIG0 + ******* Description *********** + 0 + 31 + read-write + + + REDCY_ANDOR + ******* Description *********** + 31 + 1 + read-only + + + + + REDCY_SIG1 + ******* Description *********** + 0x98 + 0x20 + + + REDCY_SIG1 + ******* Description *********** + 0 + 31 + read-write + + + REDCY_NANDOR + ******* Description *********** + 31 + 1 + read-only + + + + + FRONT_END_MEM_PD + ******* Description *********** + 0x9C + 0x20 + 0x00000055 + + + AGC_MEM_FORCE_PU + ******* Description *********** + 0 + 1 + read-write + + + AGC_MEM_FORCE_PD + ******* Description *********** + 1 + 1 + read-write + + + PBUS_MEM_FORCE_PU + ******* Description *********** + 2 + 1 + read-write + + + PBUS_MEM_FORCE_PD + ******* Description *********** + 3 + 1 + read-write + + + DC_MEM_FORCE_PU + ******* Description *********** + 4 + 1 + read-write + + + DC_MEM_FORCE_PD + ******* Description *********** + 5 + 1 + read-write + + + FREQ_MEM_FORCE_PU + ******* Description *********** + 6 + 1 + read-write + + + FREQ_MEM_FORCE_PD + ******* Description *********** + 7 + 1 + read-write + + + + + SPI_MEM_ECC_CTRL + ******* Description *********** + 0xA0 + 0x20 + 0x00200000 + + + FLASH_PAGE_SIZE + Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SRAM_PAGE_SIZE + Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 20 + 2 + read-write + + + + + CLKGATE_FORCE_ON + ******* Description *********** + 0xA8 + 0x20 + 0x00003FFF + + + ROM_CLKGATE_FORCE_ON + ******* Description *********** + 0 + 3 + read-write + + + SRAM_CLKGATE_FORCE_ON + ******* Description *********** + 3 + 11 + read-write + + + + + MEM_POWER_DOWN + ******* Description *********** + 0xAC + 0x20 + + + ROM_POWER_DOWN + ******* Description *********** + 0 + 3 + read-write + + + SRAM_POWER_DOWN + ******* Description *********** + 3 + 11 + read-write + + + + + MEM_POWER_UP + ******* Description *********** + 0xB0 + 0x20 + 0x00003FFF + + + ROM_POWER_UP + ******* Description *********** + 0 + 3 + read-write + + + SRAM_POWER_UP + ******* Description *********** + 3 + 11 + read-write + + + + + RETENTION_CTRL + ******* Description *********** + 0xB4 + 0x20 + + + RETENTION_CPU_LINK_ADDR + ******* Description *********** + 0 + 27 + read-write + + + NOBYPASS_CPU_ISO_RST + ******* Description *********** + 27 + 1 + read-write + + + + + RETENTION_CTRL1 + ******* Description *********** + 0xB8 + 0x20 + + + RETENTION_TAG_LINK_ADDR + ******* Description *********** + 0 + 27 + read-write + + + + + RETENTION_CTRL2 + ******* Description *********** + 0xBC + 0x20 + 0x001FEFF0 + + + RET_ICACHE_SIZE + ******* Description *********** + 4 + 8 + read-write + + + RET_ICACHE_VLD_SIZE + ******* Description *********** + 13 + 8 + read-write + + + RET_ICACHE_START_POINT + ******* Description *********** + 22 + 8 + read-write + + + RET_ICACHE_ENABLE + ******* Description *********** + 31 + 1 + read-write + + + + + RETENTION_CTRL3 + ******* Description *********** + 0xC0 + 0x20 + 0x003FFFF0 + + + RET_DCACHE_SIZE + ******* Description *********** + 4 + 9 + read-write + + + RET_DCACHE_VLD_SIZE + ******* Description *********** + 13 + 9 + read-write + + + RET_DCACHE_START_POINT + ******* Description *********** + 22 + 9 + read-write + + + RET_DCACHE_ENABLE + ******* Description *********** + 31 + 1 + read-write + + + + + RETENTION_CTRL4 + ******* Description *********** + 0xC4 + 0x20 + 0xFFFFFFFF + + + RETENTION_INV_CFG + ******* Description *********** + 0 + 32 + read-write + + + + + RETENTION_CTRL5 + ******* Description *********** + 0xC8 + 0x20 + + + RETENTION_DISABLE + ******* Description *********** + 0 + 1 + read-write + + + + + DATE + ******* Description *********** + 0x3FC + 0x20 + 0x02101150 + + + DATE + Version control + 0 + 32 + read-write + + + + + + + APB_SARADC + Successive Approximation Register Analog to Digital Converter + APB_SARADC + 0x60040000 + + 0x0 + 0x70 + registers + + + APB_ADC + 65 + + + + CTRL + configure apb saradc controller + 0x0 + 0x20 + 0x407F8240 + + + SARADC_START_FORCE + enable start saradc by sw + 0 + 1 + read-write + + + SARADC_START + start saradc by sw + 1 + 1 + read-write + + + SARADC_WORK_MODE + 0: single mode, 1: double mode, 2: alternate mode + 3 + 2 + read-write + + + SARADC_SAR_SEL + 0: SAR1, 1: SAR2, only work for single SAR mode + 5 + 1 + read-write + + + SARADC_SAR_CLK_GATED + enable SAR CLK gate when saradc idle + 6 + 1 + read-write + + + SARADC_SAR_CLK_DIV + SAR clock divider + 7 + 8 + read-write + + + SARADC_SAR1_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 15 + 4 + read-write + + + SARADC_SAR2_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 19 + 4 + read-write + + + SARADC_SAR1_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 23 + 1 + read-write + + + SARADC_SAR2_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC2 CTRL + 24 + 1 + read-write + + + SARADC_DATA_SAR_SEL + 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. + 25 + 1 + read-write + + + SARADC_DATA_TO_I2S + 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix + 26 + 1 + read-write + + + SARADC_XPD_SAR_FORCE + force option to xpd sar blocks + 27 + 2 + read-write + + + SARADC_WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + configure apb saradc controller + 0x4 + 0x20 + 0x0000A1FE + + + SARADC_MEAS_NUM_LIMIT + enable apb saradc limit the sample num + 0 + 1 + read-write + + + SARADC_MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SARADC_SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SARADC_SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + SARADC_TIMER_SEL + 1: select saradc timer 0: i2s_ws trigger + 11 + 1 + read-write + + + SARADC_TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + SARADC_TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + configure saradc filter + 0x8 + 0x20 + + + FILTER_FACTOR1 + apb saradc factor1 + 26 + 3 + read-write + + + FILTER_FACTOR0 + apb saradc factor0 + 29 + 3 + read-write + + + + + FSM_WAIT + configure apb saradc fsm + 0xC + 0x20 + 0x00FF0808 + + + SARADC_XPD_WAIT + the cycle which saradc controller in xpd state + 0 + 8 + read-write + + + SARADC_RSTB_WAIT + the cycle which saradc controller in rst state + 8 + 8 + read-write + + + SARADC_STANDBY_WAIT + the cycle which saradc controller in standby state + 16 + 8 + read-write + + + + + SAR1_STATUS + saradc1 status for debug + 0x10 + 0x20 + + + SARADC_SAR1_STATUS + saradc1 status + 0 + 32 + read-only + + + + + SAR2_STATUS + saradc2 status for debug + 0x14 + 0x20 + + + SARADC_SAR2_STATUS + saradc2 status + 0 + 32 + read-only + + + + + SAR1_PATT_TAB1 + configure apb saradc pattern table + 0x18 + 0x20 + + + SARADC_SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB2 + configure apb saradc pattern table + 0x1C + 0x20 + + + SARADC_SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB3 + configure apb saradc pattern table + 0x20 + 0x20 + + + SARADC_SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB4 + configure apb saradc pattern table + 0x24 + 0x20 + + + SARADC_SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB1 + configure apb saradc pattern table + 0x28 + 0x20 + + + SARADC_SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB2 + configure apb saradc pattern table + 0x2C + 0x20 + + + SARADC_SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB3 + configure apb saradc pattern table + 0x30 + 0x20 + + + SARADC_SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB4 + configure apb saradc pattern table + 0x34 + 0x20 + + + SARADC_SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item 6bit) + 0 + 24 + read-write + + + + + APB_ADC_ARB_CTRL + configure apb saradc arbit + 0x38 + 0x20 + 0x00000900 + + + ADC_ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ADC_ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ADC_ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ADC_ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ADC_ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ADC_ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ADC_ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ADC_ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + configure apb saradc arbit + 0x3C + 0x20 + 0x006B4000 + + + FILTER_CHANNEL1 + configure the filter1 channel + 14 + 5 + read-write + + + FILTER_CHANNEL0 + configure the filter0 channel + 19 + 5 + read-write + + + FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + APB_SARADC1_DATA_STATUS + get apb saradc sample data + 0x40 + 0x20 + + + APB_SARADC1_DATA + apbsaradc sample data + 0 + 17 + read-only + + + + + THRES0_CTRL + configure apb saradc thres monitor + 0x44 + 0x20 + 0x0003FFED + + + THRES0_CHANNEL + configure which channel thres0 monitor + 0 + 5 + read-write + + + THRES0_HIGH + thres0 monitor high thres + 5 + 13 + read-write + + + THRES0_LOW + thres0 monitor low thres + 18 + 13 + read-write + + + + + THRES1_CTRL + configure apb saradc thres monitor + 0x48 + 0x20 + 0x0003FFED + + + THRES1_CHANNEL + configure which channel thres0 monitor + 0 + 5 + read-write + + + THRES1_HIGH + thres1 monitor high thres + 5 + 13 + read-write + + + THRES1_LOW + thres1 monitor low thres + 18 + 13 + read-write + + + + + THRES_CTRL + configure thres monitor enable + 0x58 + 0x20 + + + THRES_ALL_EN + enable thres0 to monitor all channel + 27 + 1 + read-write + + + THRES3_EN + no public + 28 + 1 + read-write + + + THRES2_EN + no public + 29 + 1 + read-write + + + THRES1_EN + enable thres1 + 30 + 1 + read-write + + + THRES0_EN + enable thres0 + 31 + 1 + read-write + + + + + INT_ENA + enable interrupt + 0x5C + 0x20 + + + THRES1_LOW_INT_ENA + interrupt of thres1 low + 26 + 1 + read-write + + + THRES0_LOW_INT_ENA + interrupt of thres0 low + 27 + 1 + read-write + + + THRES1_HIGH_INT_ENA + interrupt of thres1 high + 28 + 1 + read-write + + + THRES0_HIGH_INT_ENA + interrupt of thres0 high + 29 + 1 + read-write + + + APB_SARADC2_DONE_INT_ENA + interrupt of sar2 done + 30 + 1 + read-write + + + APB_SARADC1_DONE_INT_ENA + interrupt of sar1 done + 31 + 1 + read-write + + + + + INT_RAW + raw of interrupt + 0x60 + 0x20 + + + THRES1_LOW_INT_RAW + interrupt of thres1 low + 26 + 1 + read-only + + + THRES0_LOW_INT_RAW + interrupt of thres0 low + 27 + 1 + read-only + + + THRES1_HIGH_INT_RAW + interrupt of thres1 high + 28 + 1 + read-only + + + THRES0_HIGH_INT_RAW + interrupt of thres0 high + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_RAW + interrupt of sar2 done + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_RAW + interrupt of sar1 done + 31 + 1 + read-only + + + + + INT_ST + state of interrupt + 0x64 + 0x20 + + + THRES1_LOW_INT_ST + interrupt of thres1 low + 26 + 1 + read-only + + + THRES0_LOW_INT_ST + interrupt of thres0 low + 27 + 1 + read-only + + + THRES1_HIGH_INT_ST + interrupt of thres1 high + 28 + 1 + read-only + + + THRES0_HIGH_INT_ST + interrupt of thres0 high + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + interrupt of sar2 done + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + interrupt of sar1 done + 31 + 1 + read-only + + + + + INT_CLR + clear interrupt + 0x68 + 0x20 + + + THRES1_LOW_INT_CLR + interrupt of thres1 low + 26 + 1 + write-only + + + THRES0_LOW_INT_CLR + interrupt of thres0 low + 27 + 1 + write-only + + + THRES1_HIGH_INT_CLR + interrupt of thres1 high + 28 + 1 + write-only + + + THRES0_HIGH_INT_CLR + interrupt of thres0 high + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + interrupt of sar2 done + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + interrupt of sar1 done + 31 + 1 + write-only + + + + + DMA_CONF + configure apb saradc dma + 0x6C + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + APB_ADC_CLKM_CONF + configure apb saradc clock + 0x70 + 0x20 + 0x00000004 + + + CLKM_DIV_NUM + Integral clock divider value + 0 + 8 + read-write + + + CLKM_DIV_B + Fractional clock divider numerator value + 8 + 6 + read-write + + + CLKM_DIV_A + Fractional clock divider denominator value + 14 + 6 + read-write + + + CLK_EN + no public + 20 + 1 + read-write + + + CLK_SEL + Set this bit to enable clk_apll + 21 + 2 + read-write + + + + + APB_SARADC2_DATA_STATUS + get apb saradc2 sample data + 0x78 + 0x20 + + + APB_SARADC2_DATA + apb saradc2 sample data + 0 + 17 + read-only + + + + + APB_CTRL_DATE + version + 0x3FC + 0x20 + 0x02101180 + + + APB_CTRL_DATE + version + 0 + 32 + read-write + + + + + + + DEBUG_ASSIST + Debug Assist + DEBUG_ASSIST + 0x600CE000 + + 0x0 + 0x15C + registers + + + ASSIST_DEBUG + 83 + + + + CORE_0_INTERRUPT_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint overflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint underflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTERRUPT_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint overflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint underflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTERRUPT_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint overflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint underflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTERRUPT_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint overflow monitor interrupt clr + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint underflow monitor interrupt clr + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + read-write + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x30 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_SP + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x34 + 0x20 + + + CORE_0_AREA_PC + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_UNSTABLE + core0 sp unstable configuration register + 0x38 + 0x20 + 0x0000000B + + + CORE_0_SP_UNSTABLE + unstable period when window change,during this period no check stackpointer + 0 + 8 + read-write + + + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0x3C + 0x20 + + + CORE_0_SP_MIN + stack min value + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + core0 sp region configuration regsiter + 0x40 + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + stack max value + 0 + 32 + read-write + + + + + CORE_0_SP_PC + core0 sp pc status register + 0x44 + 0x20 + + + CORE_0_SP_PC + the PC when first touch stack monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGENABLE + core0 pdebug configuration register + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGENABLE + Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC + 0 + 1 + read-write + + + + + CORE_0_RCD_RECORDING + core0 pdebug status register + 0x4C + 0x20 + + + CORE_0_RCD_RECORDING + Pdebug record enable,set 1 to record core0 pdebug interface signal + 0 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGINST + core0 pdebug status register + 0x50 + 0x20 + + + CORE_0_RCD_PDEBUGINST + core0 pdebuginst + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSTATUS + core0 pdebug status register + 0x54 + 0x20 + + + CORE_0_RCD_PDEBUGSTATUS + core0 pdebugstatus + 0 + 8 + read-only + + + + + CORE_0_RCD_PDEBUGDATA + core0 pdebug status register + 0x58 + 0x20 + + + CORE_0_RCD_PDEBUGDATA + core0_pdebugdata + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGPC + core0 pdebug status register + 0x5C + 0x20 + + + CORE_0_RCD_PDEBUGPC + core0_pdebugPC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0STAT + core0 pdebug status register + 0x60 + 0x20 + + + CORE_0_RCD_PDEBUGLS0STAT + core0_pdebug_s0stat + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0ADDR + core0 pdebug status register + 0x64 + 0x20 + + + CORE_0_RCD_PDEBUGLS0ADDR + core0_pdebug_s0addr + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGLS0DATA + core0 pdebug status register + 0x68 + 0x20 + + + CORE_0_RCD_PDEBUGLS0DATA + core0_pdebug_s0data + 0 + 32 + read-only + + + + + CORE_0_RCD_SP + core0 pdebug status register + 0x6C + 0x20 + + + CORE_0_RCD_SP + core0_stack pointer + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + core0 bus busy status regsiter + 0x70 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + The first iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + The first iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + The first iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + core0 bus busy status regsiter + 0x74 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + The second iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + The second iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + The second iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + core0 bus busy status regsiter + 0x78 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + The first dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_0_DRAM0_RECORDING_WR_0 + The first dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + core0 bus busy status regsiter + 0x7C + 0x20 + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + The first dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + core0 bus busy status regsiter + 0x80 + 0x20 + 0xFFFFFFFF + + + CORE_0_DRAM0_RECORDING_PC_0 + The first dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + core0 bus busy status regsiter + 0x84 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + The second dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_0_DRAM0_RECORDING_WR_1 + The second dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_4 + core0 bus busy configuration regsiter + 0x88 + 0x20 + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + The second dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_5 + core0 bus busy configuration regsiter + 0x8C + 0x20 + 0xFFFFFFFF + + + CORE_0_DRAM0_RECORDING_PC_1 + The second dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_1_INTERRUPT_ENA + Core1 monitor enable configuration register + 0x90 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_ENA + Core1 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_ENA + Core1 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_ENA + Core1 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_ENA + Core1 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_ENA + Core1 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_ENA + Core1 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_ENA + Core1 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_ENA + Core1 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_ENA + Core1 stackpoint overflow monitor enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_ENA + Core1 stackpoint underflow monitor enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_1_INTERRUPT_RAW + Core1 monitor interrupt status register + 0x94 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RAW + Core1 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_1_AREA_DRAM0_0_WR_RAW + Core1 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_RD_RAW + Core1 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_WR_RAW + Core1 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_1_AREA_PIF_0_RD_RAW + Core1 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_1_AREA_PIF_0_WR_RAW + Core1 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_1_AREA_PIF_1_RD_RAW + Core1 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_1_AREA_PIF_1_WR_RAW + Core1 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_1_SP_SPILL_MIN_RAW + Core1 stackpoint overflow monitor interrupt status + 8 + 1 + read-only + + + CORE_1_SP_SPILL_MAX_RAW + Core1 stackpoint underflow monitor interrupt status + 9 + 1 + read-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_1_INTERRUPT_RLS + Core1 monitor interrupt enable register + 0x98 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RLS + Core1 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_RLS + Core1 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_RLS + Core1 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_RLS + Core1 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_RLS + Core1 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_RLS + Core1 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_RLS + Core1 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_RLS + Core1 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_RLS + Core1 stackpoint overflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_RLS + Core1 stackpoint underflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_1_INTERRUPT_CLR + Core1 monitor interrupt clr register + 0x9C + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_CLR + Core1 dram0 area0 read monitor interrupt clr + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_CLR + Core1 dram0 area0 write monitor interrupt clr + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_CLR + Core1 dram0 area1 read monitor interrupt clr + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_CLR + Core1 dram0 area1 write monitor interrupt clr + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_CLR + Core1 PIF area0 read monitor interrupt clr + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_CLR + Core1 PIF area0 write monitor interrupt clr + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_CLR + Core1 PIF area1 read monitor interrupt clr + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_CLR + Core1 PIF area1 write monitor interrupt clr + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_CLR + Core1 stackpoint overflow monitor interrupt clr + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_CLR + Core1 stackpoint underflow monitor interrupt clr + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + read-write + + + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 addr configuration register + 0xA0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 addr configuration register + 0xA4 + 0x20 + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 addr configuration register + 0xA8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 addr configuration register + 0xAC + 0x20 + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 addr configuration register + 0xB0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 addr configuration register + 0xB4 + 0x20 + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 addr configuration register + 0xB8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 addr configuration register + 0xBC + 0x20 + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PC + Core1 area sp status register + 0xC0 + 0x20 + + + CORE_1_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_AREA_SP + Core1 area pc status register + 0xC4 + 0x20 + + + CORE_1_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_SP_UNSTABLE + Core1 sp unstable configuration register + 0xC8 + 0x20 + 0x0000000B + + + CORE_1_SP_UNSTABLE + unstable period when window change,during this period no check stackpointer + 0 + 8 + read-write + + + + + CORE_1_SP_MIN + Core1 sp region configuration regsiter + 0xCC + 0x20 + + + CORE_1_SP_MIN + stack min value + 0 + 32 + read-write + + + + + CORE_1_SP_MAX + Core1 sp region configuration regsiter + 0xD0 + 0x20 + 0xFFFFFFFF + + + CORE_1_SP_MAX + stack max value + 0 + 32 + read-write + + + + + CORE_1_SP_PC + Core1 sp pc status register + 0xD4 + 0x20 + + + CORE_1_SP_PC + the PC when first touch stack monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGENABLE + Core1 pdebug configuration register + 0xD8 + 0x20 + + + CORE_1_RCD_PDEBUGENABLE + Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC + 0 + 1 + read-write + + + + + CORE_1_RCD_RECORDING + Core1 pdebug status register + 0xDC + 0x20 + + + CORE_1_RCD_RECORDING + Pdebug record enable,set 1 to record Core1 pdebug interface signal + 0 + 1 + read-write + + + + + CORE_1_RCD_PDEBUGINST + Core1 pdebug status register + 0xE0 + 0x20 + + + CORE_1_RCD_PDEBUGINST + Core1 pdebuginst + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGSTATUS + Core1 pdebug status register + 0xE4 + 0x20 + + + CORE_1_RCD_PDEBUGSTATUS + Core1 pdebugstatus + 0 + 8 + read-only + + + + + CORE_1_RCD_PDEBUGDATA + Core1 pdebug status register + 0xE8 + 0x20 + + + CORE_1_RCD_PDEBUGDATA + Core1_pdebugdata + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGPC + Core1 pdebug status register + 0xEC + 0x20 + + + CORE_1_RCD_PDEBUGPC + Core1_pdebugPC + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0STAT + Core1 pdebug status register + 0xF0 + 0x20 + + + CORE_1_RCD_PDEBUGLS0STAT + Core1_pdebug_s0stat + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0ADDR + Core1 pdebug status register + 0xF4 + 0x20 + + + CORE_1_RCD_PDEBUGLS0ADDR + Core1_pdebug_s0addr + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGLS0DATA + Core1 pdebug status register + 0xF8 + 0x20 + + + CORE_1_RCD_PDEBUGLS0DATA + Core1_pdebug_s0data + 0 + 32 + read-only + + + + + CORE_1_RCD_SP + Core1 pdebug status register + 0xFC + 0x20 + + + CORE_1_RCD_SP + Core1_stack pointer + 0 + 32 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_0 + Core1 bus busy status regsiter + 0x100 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_0 + The first iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_0 + The first iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_0 + The first iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_1 + Core1 bus busy status regsiter + 0x104 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_1 + The second iram0's addr[25:2] status when trigger IRAM busy interrupt + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_1 + The second iram0's wr status when trigger IRAM busy interrupt + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_1 + The second iram0's loadstore status when trigger IRAM busy interrupt + 25 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_0 + Core1 bus busy status regsiter + 0x108 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_0 + The first dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_1_DRAM0_RECORDING_WR_0 + The first dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_1 + Core1 bus busy status regsiter + 0x10C + 0x20 + + + CORE_1_DRAM0_RECORDING_BYTEEN_0 + The first dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_2 + Core1 bus busy status regsiter + 0x110 + 0x20 + 0xFFFFFFFF + + + CORE_1_DRAM0_RECORDING_PC_0 + The first dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_3 + Core1 bus busy status regsiter + 0x114 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_1 + The second dram0's addr[25:4] status when trigger DRAM busy interrupt + 0 + 22 + read-only + + + CORE_1_DRAM0_RECORDING_WR_1 + The second dram0's wr status when trigger DRAM busy interrupt + 22 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_4 + Core1 bus busy status regsiter + 0x118 + 0x20 + + + CORE_1_DRAM0_RECORDING_BYTEEN_1 + The second dram0's byteen status when trigger DRAM busy interrupt + 0 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_5 + Core1 bus busy status regsiter + 0x11C + 0x20 + 0xFFFFFFFF + + + CORE_1_DRAM0_RECORDING_PC_1 + The second dram0's PC status when trigger DRAM busy interrupt + 0 + 32 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + bus busy configuration register + 0x120 + 0x20 + 0x000FFFFF + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + busy monitor window cycle + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + bus busy configuration register + 0x124 + 0x20 + 0x000FFFFF + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt + 0 + 20 + read-write + + + + + LOG_SETTING + log set register + 0x128 + 0x20 + 0x00000040 + + + LOG_ENA + bus moniter enable: [0]Core1,[1]core1,[2]dma + 0 + 3 + read-write + + + LOG_MODE + check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word + 3 + 3 + read-write + + + LOG_MEM_LOOP_ENABLE + mem_loop enable,1 means that loop write + 6 + 1 + read-write + + + + + LOG_DATA_0 + log check data register + 0x12C + 0x20 + + + LOG_DATA_0 + check data0 + 0 + 32 + read-write + + + + + LOG_DATA_1 + log check data register + 0x130 + 0x20 + + + LOG_DATA_1 + check data1 + 0 + 32 + read-write + + + + + LOG_DATA_2 + log check data register + 0x134 + 0x20 + + + LOG_DATA_2 + check data2 + 0 + 32 + read-write + + + + + LOG_DATA_3 + log check data register + 0x138 + 0x20 + + + LOG_DATA_3 + check data3 + 0 + 32 + read-write + + + + + LOG_DATA_MASK + log check data mask register + 0x13C + 0x20 + + + LOG_DATA_SIZE + data mask + 0 + 16 + read-write + + + + + LOG_MIN + log check region configuration register + 0x140 + 0x20 + + + LOG_MIN + check region min addr + 0 + 32 + read-write + + + + + LOG_MAX + log check region configuration register + 0x144 + 0x20 + + + LOG_MAX + check region max addr + 0 + 32 + read-write + + + + + LOG_MEM_START + log mem region configuration register + 0x148 + 0x20 + + + LOG_MEM_START + mem start addr + 0 + 32 + read-write + + + + + LOG_MEM_END + log mem region configuration register + 0x14C + 0x20 + + + LOG_MEM_END + mem end addr + 0 + 32 + read-write + + + + + LOG_MEM_WRITING_ADDR + log mem addr status register + 0x150 + 0x20 + + + LOG_MEM_WRITING_ADDR + mem current addr, it means next writing addr + 0 + 32 + read-only + + + + + LOG_MEM_FULL_FLAG + log mem status register + 0x154 + 0x20 + + + LOG_MEM_FULL_FLAG + when it's 1,show that mem write loop morte than one time. + 0 + 1 + read-write + + + + + DATE + version register + 0x1FC + 0x20 + 0x02003040 + + + DATE + version register + 0 + 28 + read-write + + + + + + + DMA + DMA (Direct Memory Access) Controller + DMA + 0x6003F000 + + 0x0 + 0x320 + registers + + + DMA_IN_CH0 + 66 + + + DMA_IN_CH1 + 67 + + + DMA_IN_CH2 + 68 + + + DMA_IN_CH3 + 69 + + + DMA_IN_CH4 + 70 + + + DMA_OUT_CH0 + 71 + + + DMA_OUT_CH1 + 72 + + + DMA_OUT_CH2 + 73 + + + DMA_OUT_CH3 + 74 + + + DMA_OUT_CH4 + 75 + + + APB_PMS_MONITOR_VIOLATE + 84 + + + DMA_EXTMEM_REJECT + 98 + + + + 5 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x0 + 0x20 + + + IN_RST_CH + This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + 4 + 1 + read-write + + + + + 5 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x4 + 0x20 + 0x0000000C + + + DMA_INFIFO_FULL_THRS_CH + This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register. + 0 + 12 + read-write + + + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + IN_EXT_MEM_BK_SIZE_CH + Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved + 13 + 2 + read-write + + + + + 5 + 0xC0 + IN_INT_RAW_CH%s + Raw status interrupt of Rx channel 0 + 0x8 + 0x20 + + + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. + 4 + 1 + read-only + + + INFIFO_FULL_WM_CH_INT_RAW + The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0. + 5 + 1 + read-only + + + INFIFO_OVF_L1_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 6 + 1 + read-only + + + INFIFO_UDF_L1_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 7 + 1 + read-only + + + INFIFO_OVF_L3_CH_INT_RAW + This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. + 8 + 1 + read-only + + + INFIFO_UDF_L3_CH_INT_RAW + This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. + 9 + 1 + read-only + + + + + 5 + 0xC0 + IN_INT_ST_CH%s + Masked interrupt of Rx channel 0 + 0xC + 0x20 + + + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_FULL_WM_CH_INT_ST + The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L1_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L1_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + read-only + + + INFIFO_OVF_L3_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_UDF_L3_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + + + 5 + 0xC0 + IN_INT_ENA_CH%s + Interrupt enable bits of Rx channel 0 + 0x10 + 0x20 + + + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_FULL_WM_CH_INT_ENA + The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L1_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L1_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + read-write + + + INFIFO_OVF_L3_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_UDF_L3_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + + + 5 + 0xC0 + IN_INT_CLR_CH%s + Interrupt clear bits of Rx channel 0 + 0x14 + 0x20 + + + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + DMA_INFIFO_FULL_WM_CH_INT_CLR + Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L1_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L1_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 7 + 1 + write-only + + + INFIFO_OVF_L3_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_UDF_L3_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + + + 5 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x18 + 0x20 + 0x0F00003A + + + INFIFO_FULL_L1_CH + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY_L1_CH + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_FULL_L2_CH + L2 Rx FIFO full signal for Rx channel 0. + 2 + 1 + read-only + + + INFIFO_EMPTY_L2_CH + L2 Rx FIFO empty signal for Rx channel 0. + 3 + 1 + read-only + + + INFIFO_FULL_L3_CH + L3 Rx FIFO full signal for Rx channel 0. + 4 + 1 + read-only + + + INFIFO_EMPTY_L3_CH + L3 Rx FIFO empty signal for Rx channel 0. + 5 + 1 + read-only + + + INFIFO_CNT_L1_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 6 + 6 + read-only + + + INFIFO_CNT_L2_CH + The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. + 12 + 7 + read-only + + + INFIFO_CNT_L3_CH + The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. + 19 + 5 + read-only + + + IN_REMAIN_UNDER_1B_L3_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_2B_L3_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_3B_L3_CH + reserved + 26 + 1 + read-only + + + IN_REMAIN_UNDER_4B_L3_CH + reserved + 27 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 28 + 1 + read-only + + + + + 5 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x1C + 0x20 + 0x00000800 + + + INFIFO_RDATA_CH + This register stores the data popping from DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP_CH + Set this bit to pop data from DMA FIFO. + 12 + 1 + read-write + + + + + 5 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x20 + 0x20 + 0x01100000 + + + INLINK_ADDR_CH + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 20 + read-write + + + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + 5 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x24 + 0x20 + + + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only + + + + + 5 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x28 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x2C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x30 + 0x20 + + + INLINK_DSCR_CH + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x34 + 0x20 + + + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x38 + 0x20 + + + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 5 + 0xC0 + IN_WIGHT_CH%s + Weight register of Rx channel 0 + 0x3C + 0x20 + 0x00000F00 + + + RX_WEIGHT_CH + The weight of Rx channel 0. + 8 + 4 + read-write + + + + + 5 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x44 + 0x20 + + + RX_PRI_CH + The priority of Rx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + 5 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0x48 + 0x20 + 0x0000003F + + + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. + 0 + 6 + read-write + + + + + 5 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 0 + 0x60 + 0x20 + 0x00000008 + + + OUT_RST_CH + This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + + + 5 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0x64 + 0x20 + + + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + OUT_EXT_MEM_BK_SIZE_CH + Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved + 13 + 2 + read-write + + + + + 5 + 0xC0 + OUT_INT_RAW_CH%s + Raw status interrupt of Tx channel 0 + 0x68 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 + 1 + read-only + + + OUTFIFO_OVF_L3_CH_INT_RAW + This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. + 6 + 1 + read-only + + + OUTFIFO_UDF_L3_CH_INT_RAW + This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. + 7 + 1 + read-only + + + + + 5 + 0xC0 + OUT_INT_ST_CH%s + Masked interrupt of Tx channel 0 + 0x6C + 0x20 + + + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L3_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L3_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + read-only + + + + + 5 + 0xC0 + OUT_INT_ENA_CH%s + Interrupt enable bits of Tx channel 0 + 0x70 + 0x20 + + + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L3_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L3_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + read-write + + + + + 5 + 0xC0 + OUT_INT_CLR_CH%s + Interrupt clear bits of Tx channel 0 + 0x74 + 0x20 + + + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L3_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L3_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + 7 + 1 + write-only + + + + + 5 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0x78 + 0x20 + 0x0780002A + + + OUTFIFO_FULL_L1_CH + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_FULL_L2_CH + L2 Tx FIFO full signal for Tx channel 0. + 2 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH + L2 Tx FIFO empty signal for Tx channel 0. + 3 + 1 + read-only + + + OUTFIFO_FULL_L3_CH + L3 Tx FIFO full signal for Tx channel 0. + 4 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH + L3 Tx FIFO empty signal for Tx channel 0. + 5 + 1 + read-only + + + OUTFIFO_CNT_L1_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 6 + 5 + read-only + + + OUTFIFO_CNT_L2_CH + The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. + 11 + 7 + read-only + + + OUTFIFO_CNT_L3_CH + The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0. + 18 + 5 + read-only + + + OUT_REMAIN_UNDER_1B_L3_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_L3_CH + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_L3_CH + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_L3_CH + reserved + 26 + 1 + read-only + + + + + 5 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0x7C + 0x20 + + + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH_CH + Set this bit to push data into DMA FIFO. + 9 + 1 + read-write + + + + + 5 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0x80 + 0x20 + 0x00800000 + + + OUTLINK_ADDR_CH + This register stores the 20 least significant bits of the first outlink descriptor's address. + 0 + 20 + read-write + + + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + 5 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0x84 + 0x20 + + + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 + read-only + + + + + 5 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0x88 + 0x20 + + + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0x8C + 0x20 + + + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0x90 + 0x20 + + + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0x94 + 0x20 + + + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0x98 + 0x20 + + + OUTLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 5 + 0xC0 + OUT_WIGHT_CH%s + Weight register of Rx channel 0 + 0x9C + 0x20 + 0x00000F00 + + + TX_WEIGHT_CH + The weight of Tx channel 0. + 8 + 4 + read-write + + + + + 5 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xA4 + 0x20 + + + TX_PRI_CH + The priority of Tx channel 0. The larger of the value, the higher of the priority. + 0 + 4 + read-write + + + + + 5 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0xA8 + 0x20 + 0x0000003F + + + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT. + 0 + 6 + read-write + + + + + AHB_TEST + reserved + 0x3C0 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + PD_CONF + reserved + 0x3C4 + 0x20 + 0x00000020 + + + DMA_RAM_FORCE_PD + Set this bit to force power down DMA internal memory. + 4 + 1 + read-write + + + DMA_RAM_FORCE_PU + Set this bit to force power up DMA internal memory + 5 + 1 + read-write + + + DMA_RAM_CLK_FO + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + MISC_CONF + MISC register + 0x3C8 + 0x20 + + + AHBM_RST_INTER + Set this bit, then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + AHBM_RST_EXTER + Set this bit, then clear this bit to reset the external ahb FSM. + 1 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + 5 + 0x8 + IN_SRAM_SIZE_CH%s + Receive L2 FIFO depth of Rx channel 0 + 0x3CC + 0x20 + 0x0000000E + + + IN_SIZE_CH + This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. + 0 + 7 + read-write + + + + + 5 + 0x8 + OUT_SRAM_SIZE_CH%s + Transmit L2 FIFO depth of Tx channel 0 + 0x3D0 + 0x20 + 0x0000000E + + + OUT_SIZE_CH + This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes. + 0 + 7 + read-write + + + + + EXTMEM_REJECT_ADDR + Reject address accessing external RAM + 0x3F4 + 0x20 + + + EXTMEM_REJECT_ADDR + This register store the first address rejected by permission control when accessing external RAM. + 0 + 32 + read-only + + + + + EXTMEM_REJECT_ST + Reject status accessing external RAM + 0x3F8 + 0x20 + + + EXTMEM_REJECT_ATRR + The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE. + 0 + 2 + read-only + + + EXTMEM_REJECT_CHANNEL_NUM + The register indicate the reject accessing from which channel. + 2 + 4 + read-only + + + EXTMEM_REJECT_PERI_NUM + This register indicate reject accessing from which peripheral. + 6 + 6 + read-only + + + + + EXTMEM_REJECT_INT_RAW + Raw interrupt status of external RAM permission + 0x3FC + 0x20 + + + EXTMEM_REJECT_INT_RAW + The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control. + 0 + 1 + read-only + + + + + EXTMEM_REJECT_INT_ST + Masked interrupt status of external RAM permission + 0x400 + 0x20 + + + EXTMEM_REJECT_INT_ST + The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt. + 0 + 1 + read-only + + + + + EXTMEM_REJECT_INT_ENA + Interrupt enable bits of external RAM permission + 0x404 + 0x20 + + + EXTMEM_REJECT_INT_ENA + The interrupt enable bit for the EXTMEM_REJECT_INT interrupt. + 0 + 1 + read-write + + + + + EXTMEM_REJECT_INT_CLR + Interrupt clear bits of external RAM permission + 0x408 + 0x20 + + + EXTMEM_REJECT_INT_CLR + Set this bit to clear the EXTMEM_REJECT_INT interrupt. + 0 + 1 + write-only + + + + + DATE + Version control register + 0x40C + 0x20 + 0x02101180 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + DS + Digital Signature + DS + 0x6003D000 + + 0x0 + 0xA5C + registers + + + + 1584 + 0x1 + C_MEM[%s] + Memory C + 0x0 + 0x8 + + + 4 + 0x4 + IV_%s + IV block data + 0x630 + 0x20 + + + IV_0 + Stores IV block data + 0 + 32 + read-write + + + + + 512 + 0x1 + X_MEM[%s] + Memory X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + Memory Z + 0xA00 + 0x8 + + + SET_START + Activates the DS peripheral + 0xE00 + 0x20 + + + SET_START + Write 1 to this register to active the DS peripheral + 0 + 1 + write-only + + + + + SET_ME + Starts DS operation + 0xE04 + 0x20 + + + SET_ME + Write 1 to this register to start DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + Ends DS operation + 0xE08 + 0x20 + + + SET_FINISH + Write 1 to this register to end DS operation. + 0 + 1 + write-only + + + + + QUERY_BUSY + Status of the DS perihperal + 0xE0C + 0x20 + + + QUERY_BUSY + Stores the status of the DS peripheral. 1: The DS peripheral is busy. 0: The DS peripheral is idle. + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + Checks the reason why DS_KEY is not ready + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + 1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY from the HMAC peripheral. (The biggest value is 15). 0: HMAC is not activated. + 0 + 4 + read-only + + + + + QUERY_CHECK + Queries DS check result + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1: The MD check fails. 0: The MD check passes. + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1: The padding check fails. 0: The padding check passes. + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20191217 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + EFUSE + eFuse Controller + EFUSE + 0x60007000 + + 0x0 + 0x1CC + registers + + + EFUSE + 36 + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + The content of the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + The content of the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + The content of the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + The content of the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + The content of the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + The content of the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + The content of the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + The content of the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + The content of the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + The content of the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + The content of the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Disable programming of individual eFuses. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Set this bit to disable reading from BlOCK4-10. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT + Set this bit to disable boot from RTC RAM. + 7 + 1 + read-only + + + DIS_ICACHE + Set this bit to disable Icache. + 8 + 1 + read-only + + + DIS_DCACHE + Set this bit to disable Dcache. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE + Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7). + 10 + 1 + read-only + + + DIS_DOWNLOAD_DCACHE + Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7). + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Set this bit to disable the function that forces chip into download mode. + 12 + 1 + read-only + + + DIS_USB + Set this bit to disable USB function. + 13 + 1 + read-only + + + DIS_CAN + Set this bit to disable CAN function. + 14 + 1 + read-only + + + DIS_APP_CPU + Disable app cpu. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Set this bit to disable flash encryption when in download boot modes. + 20 + 1 + read-only + + + USB_DREFH + Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse. + 21 + 2 + read-only + + + USB_DREFL + Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse. + 23 + 2 + read-only + + + USB_EXCHG_PINS + Set this bit to exchange USB D+ and D- pins. + 25 + 1 + read-only + + + EXT_PHY_ENABLE + Set this bit to enable external PHY. + 26 + 1 + read-only + + + BTLC_GPIO_ENABLE + Bluetooth GPIO signal output security level control. + 27 + 2 + read-only + + + VDD_SPI_MODECURLIM + SPI regulator switches current limit mode. + 29 + 1 + read-only + + + VDD_SPI_DREFH + SPI regulator high voltage reference. + 30 + 2 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + VDD_SPI_DREFM + SPI regulator medium voltage reference. + 0 + 2 + read-only + + + VDD_SPI_DREFL + SPI regulator low voltage reference. + 2 + 2 + read-only + + + VDD_SPI_XPD + SPI regulator power up signal. + 4 + 1 + read-only + + + VDD_SPI_TIEH + SPI regulator output is short connected to VDD3P3_RTC_IO. + 5 + 1 + read-only + + + VDD_SPI_FORCE + Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + 6 + 1 + read-only + + + VDD_SPI_EN_INIT + Set SPI regulator to 0 to configure init[1:0]=0. + 7 + 1 + read-only + + + VDD_SPI_ENCURLIM + Set SPI regulator to 1 to enable output current limit. + 8 + 1 + read-only + + + VDD_SPI_DCURLIM + Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). + 9 + 3 + read-only + + + VDD_SPI_INIT + Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K. + 12 + 2 + read-only + + + VDD_SPI_DCAP + Prevents SPI regulator from overshoot. + 14 + 2 + read-only + + + WDT_DELAY_SEL + Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Set this bit to enable revoking first secure boot key. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Set this bit to enable revoking second secure boot key. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Set this bit to enable revoking third secure boot key. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + + + KEY_PURPOSE_2 + Purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Purpose of Key5. + 12 + 4 + read-only + + + RPT4_RESERVED0 + Reserved (used for four backups method). + 16 + 4 + read-only + + + SECURE_BOOT_EN + Set this bit to enable secure boot. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Set this bit to enable revoking aggressive secure boot. + 21 + 1 + read-only + + + DIS_USB_JTAG + Set this bit to disable function of usb switch to jtag in module of usb device. + 22 + 1 + read-only + + + DIS_USB_DEVICE + Set this bit to disable usb device. + 23 + 1 + read-only + + + STRAP_JTAG_SEL + Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + 24 + 1 + read-only + + + USB_PHY_SEL + This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device. + 25 + 1 + read-only + + + POWER_GLITCH_DSENSE + Sample delay configuration of power glitch. + 26 + 2 + read-only + + + FLASH_TPUW + Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT + Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4). + 1 + 1 + read-only + + + UART_PRINT_CHANNEL + Selectes the default UART print channel. 0: UART0. 1: UART1. + 2 + 1 + read-only + + + FLASH_ECC_MODE + Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE + Set this bit to disable UART download mode through USB. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Set this bit to enable secure UART download mode. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled. + 6 + 2 + read-only + + + PIN_POWER_SELECTION + GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI. + 8 + 1 + read-only + + + FLASH_TYPE + Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. + 9 + 1 + read-only + + + FLASH_PAGE_SIZE + Set Flash page size. + 10 + 2 + read-only + + + FLASH_ECC_EN + Set 1 to enable ECC for flash boot. + 12 + 1 + read-only + + + FORCE_SEND_RESUME + Set this bit to force ROM code to send a resume command during SPI boot. + 13 + 1 + read-only + + + SECURE_VERSION + Secure version (used by ESP-IDF anti-rollback feature). + 14 + 16 + read-only + + + POWERGLITCH_EN + Set this bit to enable power glitch function. + 30 + 1 + read-only + + + RPT4_RESERVED1 + Reserved (used for four backups method). + 31 + 1 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + RPT4_RESERVED2 + Reserved (used for four backups method). + 0 + 24 + read-only + + + + + RD_MAC_SPI_SYS_0 + BLOCK1 data register 0. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_1 + BLOCK1 data register 1. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + SPI_PAD_CONF_0 + Stores the zeroth part of SPI_PAD_CONF. + 16 + 16 + read-only + + + + + RD_MAC_SPI_SYS_2 + BLOCK1 data register 2. + 0x4C + 0x20 + + + SPI_PAD_CONF_1 + Stores the first part of SPI_PAD_CONF. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_3 + BLOCK1 data register 3. + 0x50 + 0x20 + + + SPI_PAD_CONF_2 + Stores the second part of SPI_PAD_CONF. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the fist 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SPI_SYS_4 + BLOCK1 data register 4. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the fist 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SPI_SYS_5 + BLOCK1 data register 5. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register 0 of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register 1 of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register 2 of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register 3 of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register 4 of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register 5 of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register 6 of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register 7 of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register 0 of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register 1 of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register 2 of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register 3 of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register 4 of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register 5 of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register 6 of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register 7 of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register 0 of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register 1 of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register 2 of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register 3 of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register 4 of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register 5 of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register 6 of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register 7 of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register 0 of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register 1 of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register 2 of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register 3 of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register 4 of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register 5 of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register 6 of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register 7 of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register 0 of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register 1 of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register 2 of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register 3 of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register 4 of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register 5 of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register 6 of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register 7 of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register 0 of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register 1 of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register 2 of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register 3 of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register 4 of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register 5 of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register 6 of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register 7 of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register 0 of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register 1 of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register 2 of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register 3 of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register 4 of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register 5 of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register 6 of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register 7 of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register 0 of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register 1 of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register 2 of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register 3 of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register 4 of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register 5 of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register 6 of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register 7 of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register 0 of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register 1 of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 1st 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register 2 of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 2nd 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register 3 of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 3rd 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register 4 of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 4th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register 5 of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 5th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register 6 of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 6th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register 7 of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 7th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 7 + read-only + + + DIS_RTC_RAM_BOOT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 7 + 1 + read-only + + + DIS_ICACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + DIS_DCACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 1 + read-only + + + DIS_DOWNLOAD_ICACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 10 + 1 + read-only + + + DIS_DOWNLOAD_DCACHE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 1 + read-only + + + DIS_USB_ERR + If any bits in this filed are 1, then it indicates a programming error. + 13 + 1 + read-only + + + DIS_CAN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 1 + read-only + + + DIS_APP_CPU_ERR + If any bits in this filed are 1, then it indicates a programming error. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 20 + 1 + read-only + + + USB_DREFH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 2 + read-only + + + USB_DREFL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 2 + read-only + + + USB_EXCHG_PINS_ERR + If any bits in this filed are 1, then it indicates a programming error. + 25 + 1 + read-only + + + EXT_PHY_ENABLE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 26 + 1 + read-only + + + BTLC_GPIO_ENABLE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 27 + 2 + read-only + + + VDD_SPI_MODECURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 29 + 1 + read-only + + + VDD_SPI_DREFH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 30 + 2 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + VDD_SPI_DREFM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 2 + read-only + + + VDD_SPI_DREFL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 2 + 2 + read-only + + + VDD_SPI_XPD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 1 + read-only + + + VDD_SPI_TIEH_ERR + If any bits in this filed are 1, then it indicates a programming error. + 5 + 1 + read-only + + + VDD_SPI_FORCE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 6 + 1 + read-only + + + VDD_SPI_EN_INIT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 7 + 1 + read-only + + + VDD_SPI_ENCURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + VDD_SPI_DCURLIM_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 3 + read-only + + + VDD_SPI_INIT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 2 + read-only + + + VDD_SPI_DCAP_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 2 + read-only + + + WDT_DELAY_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + If any bits in this filed are 1, then it indicates a programming error. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + If any bits in this filed are 1, then it indicates a programming error. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 4 + read-only + + + RPT4_RESERVED0_ERR + If any bits in this filed are 1, then it indicates a programming error. + 16 + 4 + read-only + + + SECURE_BOOT_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 21 + 1 + read-only + + + DIS_USB_JTAG_ERR + If any bits in this filed are 1, then it indicates a programming error. + 22 + 1 + read-only + + + DIS_USB_DEVICE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 23 + 1 + read-only + + + STRAP_JTAG_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 24 + 1 + read-only + + + USB_PHY_SEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 25 + 1 + read-only + + + POWER_GLITCH_DSENSE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 26 + 2 + read-only + + + FLASH_TPUW_ERR + If any bits in this filed are 1, then it indicates a programming error. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 1 + read-only + + + DIS_LEGACY_SPI_BOOT_ERR + If any bits in this filed are 1, then it indicates a programming error. + 1 + 1 + read-only + + + UART_PRINT_CHANNEL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 2 + 1 + read-only + + + FLASH_ECC_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 3 + 1 + read-only + + + DIS_USB_DOWNLOAD_MODE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + If any bits in this filed are 1, then it indicates a programming error. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + If any bits in this filed are 1, then it indicates a programming error. + 6 + 2 + read-only + + + PIN_POWER_SELECTION_ERR + If any bits in this filed are 1, then it indicates a programming error. + 8 + 1 + read-only + + + FLASH_TYPE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 9 + 1 + read-only + + + FLASH_PAGE_SIZE_ERR + If any bits in this filed are 1, then it indicates a programming error. + 10 + 2 + read-only + + + FLASH_ECC_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 12 + 1 + read-only + + + FORCE_SEND_RESUME_ERR + If any bits in this filed are 1, then it indicates a programming error. + 13 + 1 + read-only + + + SECURE_VERSION_ERR + If any bits in this filed are 1, then it indicates a programming error. + 14 + 16 + read-only + + + POWERGLITCH_EN_ERR + If any bits in this filed are 1, then it indicates a programming error. + 30 + 1 + read-only + + + RPT4_RESERVED1_ERR + Reserved. + 31 + 1 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x190 + 0x20 + + + RPT4_RESERVED2_ERR + If any bits in this filed are 1, then it indicates a programming error. + 0 + 24 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SPI_8M_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SPI_8M_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + 0x00000002 + + + EFUSE_MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + EFUSE_MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit and force to enable clock signal of eFuse memory. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: Operate programming command 0x5AA5: Operate read command. + 0 + 16 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + REPEAT_ERR_CNT + Indicates the number of error bits during programming BLOCK0. + 10 + 8 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE1C + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x12000000 + + + READ_INIT_NUM + Configures the initial read time of eFuse. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00288000 + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F8 + 0x20 + 0x00000190 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02101290 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + + + EXTMEM + External Memory + EXTMEM + 0x600C4000 + + 0x0 + 0x17C + registers + + + + DCACHE_CTRL + ******* Description *********** + 0x0 + 0x20 + + + DCACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + DCACHE_SIZE_MODE + The bit is used to configure cache memory size.0: 32KB, 1: 64KB + 2 + 1 + read-write + + + DCACHE_BLOCKSIZE_MODE + The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes + 3 + 2 + read-write + + + + + DCACHE_CTRL1 + ******* Description *********** + 0x4 + 0x20 + 0x00000003 + + + DCACHE_SHUT_CORE0_BUS + The bit is used to disable core0 dbus, 0: enable, 1: disable + 0 + 1 + read-write + + + DCACHE_SHUT_CORE1_BUS + The bit is used to disable core1 dbus, 0: enable, 1: disable + 1 + 1 + read-write + + + + + DCACHE_TAG_POWER_CTRL + ******* Description *********** + 0x8 + 0x20 + 0x00000005 + + + DCACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + DCACHE_TAG_MEM_FORCE_PD + The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + DCACHE_TAG_MEM_FORCE_PU + The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + DCACHE_PRELOCK_CTRL + ******* Description *********** + 0xC + 0x20 + + + DCACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function. + 0 + 1 + read-write + + + DCACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function. + 1 + 1 + read-write + + + + + DCACHE_PRELOCK_SCT0_ADDR + ******* Description *********** + 0x10 + 0x20 + + + DCACHE_PRELOCK_SCT0_ADDR + The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + DCACHE_PRELOCK_SCT1_ADDR + ******* Description *********** + 0x14 + 0x20 + + + DCACHE_PRELOCK_SCT1_ADDR + The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + DCACHE_PRELOCK_SCT_SIZE + ******* Description *********** + 0x18 + 0x20 + + + DCACHE_PRELOCK_SCT1_SIZE + The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG + 0 + 16 + read-write + + + DCACHE_PRELOCK_SCT0_SIZE + The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG + 16 + 16 + read-write + + + + + DCACHE_LOCK_CTRL + ******* Description *********** + 0x1C + 0x20 + 0x00000004 + + + DCACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 0 + 1 + read-write + + + DCACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 1 + 1 + read-write + + + DCACHE_LOCK_DONE + The bit is used to indicate unlock/lock operation is finished. + 2 + 1 + read-only + + + + + DCACHE_LOCK_ADDR + ******* Description *********** + 0x20 + 0x20 + + + DCACHE_LOCK_ADDR + The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_LOCK_SIZE + ******* Description *********** + 0x24 + 0x20 + + + DCACHE_LOCK_SIZE + The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG. + 0 + 16 + read-write + + + + + DCACHE_SYNC_CTRL + ******* Description *********** + 0x28 + 0x20 + 0x00000001 + + + DCACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 0 + 1 + read-write + + + DCACHE_WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. + 1 + 1 + read-write + + + DCACHE_CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. + 2 + 1 + read-write + + + DCACHE_SYNC_DONE + The bit is used to indicate clean/writeback/invalidate operation is finished. + 3 + 1 + read-only + + + + + DCACHE_SYNC_ADDR + ******* Description *********** + 0x2C + 0x20 + + + DCACHE_SYNC_ADDR + The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_SYNC_SIZE + ******* Description *********** + 0x30 + 0x20 + + + DCACHE_SYNC_SIZE + The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG. + 0 + 23 + read-write + + + + + DCACHE_OCCUPY_CTRL + ******* Description *********** + 0x34 + 0x20 + 0x00000002 + + + DCACHE_OCCUPY_ENA + The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation. + 0 + 1 + read-write + + + DCACHE_OCCUPY_DONE + The bit is used to indicate occupy operation is finished. + 1 + 1 + read-only + + + + + DCACHE_OCCUPY_ADDR + ******* Description *********** + 0x38 + 0x20 + + + DCACHE_OCCUPY_ADDR + The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_OCCUPY_SIZE + ******* Description *********** + 0x3C + 0x20 + + + DCACHE_OCCUPY_SIZE + The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG. + 0 + 16 + read-write + + + + + DCACHE_PRELOAD_CTRL + ******* Description *********** + 0x40 + 0x20 + 0x00000002 + + + DCACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 0 + 1 + read-write + + + DCACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 1 + 1 + read-only + + + DCACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. + 2 + 1 + read-write + + + + + DCACHE_PRELOAD_ADDR + ******* Description *********** + 0x44 + 0x20 + + + DCACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + DCACHE_PRELOAD_SIZE + ******* Description *********** + 0x48 + 0x20 + + + DCACHE_PRELOAD_SIZE + The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.. + 0 + 16 + read-write + + + + + DCACHE_AUTOLOAD_CTRL + ******* Description *********** + 0x4C + 0x20 + 0x00000008 + + + DCACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the first section for autoload operation. + 0 + 1 + read-write + + + DCACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the second section for autoload operation. + 1 + 1 + read-write + + + DCACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. + 2 + 1 + read-write + + + DCACHE_AUTOLOAD_DONE + The bit is used to indicate autoload operation is finished. + 3 + 1 + read-only + + + DCACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of autoload. 1: descending, 0: ascending. + 4 + 1 + read-write + + + DCACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 5 + 2 + read-write + + + DCACHE_AUTOLOAD_SIZE + The bits are used to configure the numbers of the cache block for the issuing autoload operation. + 7 + 2 + read-write + + + DCACHE_AUTOLOAD_BUFFER_CLEAR + The bit is used to clear autoload buffer in dcache. + 9 + 1 + read-write + + + + + DCACHE_AUTOLOAD_SCT0_ADDR + ******* Description *********** + 0x50 + 0x20 + + + DCACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + DCACHE_AUTOLOAD_SCT0_SIZE + ******* Description *********** + 0x54 + 0x20 + + + DCACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena. + 0 + 27 + read-write + + + + + DCACHE_AUTOLOAD_SCT1_ADDR + ******* Description *********** + 0x58 + 0x20 + + + DCACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + DCACHE_AUTOLOAD_SCT1_SIZE + ******* Description *********** + 0x5C + 0x20 + + + DCACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena. + 0 + 27 + read-write + + + + + ICACHE_CTRL + ******* Description *********** + 0x60 + 0x20 + + + ICACHE_ENABLE + The bit is used to activate the data cache. 0: disable, 1: enable + 0 + 1 + read-write + + + ICACHE_WAY_MODE + The bit is used to configure cache way mode.0: 4-way, 1: 8-way + 1 + 1 + read-write + + + ICACHE_SIZE_MODE + The bit is used to configure cache memory size.0: 16KB, 1: 32KB + 2 + 1 + read-write + + + ICACHE_BLOCKSIZE_MODE + The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes + 3 + 1 + read-write + + + + + ICACHE_CTRL1 + ******* Description *********** + 0x64 + 0x20 + 0x00000003 + + + ICACHE_SHUT_CORE0_BUS + The bit is used to disable core0 ibus, 0: enable, 1: disable + 0 + 1 + read-write + + + ICACHE_SHUT_CORE1_BUS + The bit is used to disable core1 ibus, 0: enable, 1: disable + 1 + 1 + read-write + + + + + ICACHE_TAG_POWER_CTRL + ******* Description *********** + 0x68 + 0x20 + 0x00000005 + + + ICACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PD + The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + ICACHE_TAG_MEM_FORCE_PU + The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + + + ICACHE_PRELOCK_CTRL + ******* Description *********** + 0x6C + 0x20 + + + ICACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function. + 0 + 1 + read-write + + + ICACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function. + 1 + 1 + read-write + + + + + ICACHE_PRELOCK_SCT0_ADDR + ******* Description *********** + 0x70 + 0x20 + + + ICACHE_PRELOCK_SCT0_ADDR + The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + ICACHE_PRELOCK_SCT1_ADDR + ******* Description *********** + 0x74 + 0x20 + + + ICACHE_PRELOCK_SCT1_ADDR + The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + ICACHE_PRELOCK_SCT_SIZE + ******* Description *********** + 0x78 + 0x20 + + + ICACHE_PRELOCK_SCT1_SIZE + The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG + 0 + 16 + read-write + + + ICACHE_PRELOCK_SCT0_SIZE + The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG + 16 + 16 + read-write + + + + + ICACHE_LOCK_CTRL + ******* Description *********** + 0x7C + 0x20 + 0x00000004 + + + ICACHE_LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + 0 + 1 + read-write + + + ICACHE_UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + 1 + 1 + read-write + + + ICACHE_LOCK_DONE + The bit is used to indicate unlock/lock operation is finished. + 2 + 1 + read-only + + + + + ICACHE_LOCK_ADDR + ******* Description *********** + 0x80 + 0x20 + + + ICACHE_LOCK_ADDR + The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_LOCK_SIZE + ******* Description *********** + 0x84 + 0x20 + + + ICACHE_LOCK_SIZE + The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG. + 0 + 16 + read-write + + + + + ICACHE_SYNC_CTRL + ******* Description *********** + 0x88 + 0x20 + 0x00000001 + + + ICACHE_INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + 0 + 1 + read-write + + + ICACHE_SYNC_DONE + The bit is used to indicate invalidate operation is finished. + 1 + 1 + read-only + + + + + ICACHE_SYNC_ADDR + ******* Description *********** + 0x8C + 0x20 + + + ICACHE_SYNC_ADDR + The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_SYNC_SIZE + ******* Description *********** + 0x90 + 0x20 + + + ICACHE_SYNC_SIZE + The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + 0 + 23 + read-write + + + + + ICACHE_PRELOAD_CTRL + ******* Description *********** + 0x94 + 0x20 + 0x00000002 + + + ICACHE_PRELOAD_ENA + The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + 0 + 1 + read-write + + + ICACHE_PRELOAD_DONE + The bit is used to indicate preload operation is finished. + 1 + 1 + read-only + + + ICACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 1: descending, 0: ascending. + 2 + 1 + read-write + + + + + ICACHE_PRELOAD_ADDR + ******* Description *********** + 0x98 + 0x20 + + + ICACHE_PRELOAD_ADDR + The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. + 0 + 32 + read-write + + + + + ICACHE_PRELOAD_SIZE + ******* Description *********** + 0x9C + 0x20 + + + ICACHE_PRELOAD_SIZE + The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.. + 0 + 16 + read-write + + + + + ICACHE_AUTOLOAD_CTRL + ******* Description *********** + 0xA0 + 0x20 + 0x00000008 + + + ICACHE_AUTOLOAD_SCT0_ENA + The bits are used to enable the first section for autoload operation. + 0 + 1 + read-write + + + ICACHE_AUTOLOAD_SCT1_ENA + The bits are used to enable the second section for autoload operation. + 1 + 1 + read-write + + + ICACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. + 2 + 1 + read-write + + + ICACHE_AUTOLOAD_DONE + The bit is used to indicate autoload operation is finished. + 3 + 1 + read-only + + + ICACHE_AUTOLOAD_ORDER + The bits are used to configure the direction of autoload. 1: descending, 0: ascending. + 4 + 1 + read-write + + + ICACHE_AUTOLOAD_RQST + The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + 5 + 2 + read-write + + + ICACHE_AUTOLOAD_SIZE + The bits are used to configure the numbers of the cache block for the issuing autoload operation. + 7 + 2 + read-write + + + ICACHE_AUTOLOAD_BUFFER_CLEAR + The bit is used to clear autoload buffer in icache. + 9 + 1 + read-write + + + + + ICACHE_AUTOLOAD_SCT0_ADDR + ******* Description *********** + 0xA4 + 0x20 + + + ICACHE_AUTOLOAD_SCT0_ADDR + The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + 0 + 32 + read-write + + + + + ICACHE_AUTOLOAD_SCT0_SIZE + ******* Description *********** + 0xA8 + 0x20 + + + ICACHE_AUTOLOAD_SCT0_SIZE + The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + 0 + 27 + read-write + + + + + ICACHE_AUTOLOAD_SCT1_ADDR + ******* Description *********** + 0xAC + 0x20 + + + ICACHE_AUTOLOAD_SCT1_ADDR + The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + 0 + 32 + read-write + + + + + ICACHE_AUTOLOAD_SCT1_SIZE + ******* Description *********** + 0xB0 + 0x20 + + + ICACHE_AUTOLOAD_SCT1_SIZE + The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + 0 + 27 + read-write + + + + + IBUS_TO_FLASH_START_VADDR + ******* Description *********** + 0xB4 + 0x20 + 0x44000000 + + + IBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + IBUS_TO_FLASH_END_VADDR + ******* Description *********** + 0xB8 + 0x20 + 0x47FFFFFF + + + IBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_START_VADDR + ******* Description *********** + 0xBC + 0x20 + + + DBUS_TO_FLASH_START_VADDR + The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + DBUS_TO_FLASH_END_VADDR + ******* Description *********** + 0xC0 + 0x20 + + + DBUS_TO_FLASH_END_VADDR + The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + 0 + 32 + read-write + + + + + CACHE_ACS_CNT_CLR + ******* Description *********** + 0xC4 + 0x20 + + + DCACHE_ACS_CNT_CLR + The bit is used to clear dcache counter. + 0 + 1 + write-only + + + ICACHE_ACS_CNT_CLR + The bit is used to clear icache counter. + 1 + 1 + write-only + + + + + IBUS_ACS_MISS_CNT + ******* Description *********** + 0xC8 + 0x20 + + + IBUS_ACS_MISS_CNT + The bits are used to count the number of the cache miss caused by ibus access flash/spiram. + 0 + 32 + read-only + + + + + IBUS_ACS_CNT + ******* Description *********** + 0xCC + 0x20 + + + IBUS_ACS_CNT + The bits are used to count the number of ibus access flash/spiram through icache. + 0 + 32 + read-only + + + + + DBUS_ACS_FLASH_MISS_CNT + ******* Description *********** + 0xD0 + 0x20 + + + DBUS_ACS_FLASH_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus access flash. + 0 + 32 + read-only + + + + + DBUS_ACS_SPIRAM_MISS_CNT + ******* Description *********** + 0xD4 + 0x20 + + + DBUS_ACS_SPIRAM_MISS_CNT + The bits are used to count the number of the cache miss caused by dbus access spiram. + 0 + 32 + read-only + + + + + DBUS_ACS_CNT + ******* Description *********** + 0xD8 + 0x20 + + + DBUS_ACS_CNT + The bits are used to count the number of dbus access flash/spiram through dcache. + 0 + 32 + read-only + + + + + CACHE_ILG_INT_ENA + ******* Description *********** + 0xDC + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_ENA + The bit is used to enable interrupt by sync configurations fault. + 0 + 1 + read-write + + + ICACHE_PRELOAD_OP_FAULT_INT_ENA + The bit is used to enable interrupt by preload configurations fault. + 1 + 1 + read-write + + + DCACHE_SYNC_OP_FAULT_INT_ENA + The bit is used to enable interrupt by sync configurations fault. + 2 + 1 + read-write + + + DCACHE_PRELOAD_OP_FAULT_INT_ENA + The bit is used to enable interrupt by preload configurations fault. + 3 + 1 + read-write + + + DCACHE_WRITE_FLASH_INT_ENA + The bit is used to enable interrupt by dcache trying to write flash. + 4 + 1 + read-write + + + MMU_ENTRY_FAULT_INT_ENA + The bit is used to enable interrupt by mmu entry fault. + 5 + 1 + read-write + + + DCACHE_OCCUPY_EXC_INT_ENA + The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + read-write + + + IBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by ibus counter overflow. + 7 + 1 + read-write + + + DBUS_CNT_OVF_INT_ENA + The bit is used to enable interrupt by dbus counter overflow. + 8 + 1 + read-write + + + + + CACHE_ILG_INT_CLR + ******* Description *********** + 0xE0 + 0x20 + + + ICACHE_SYNC_OP_FAULT_INT_CLR + The bit is used to clear interrupt by sync configurations fault. + 0 + 1 + write-only + + + ICACHE_PRELOAD_OP_FAULT_INT_CLR + The bit is used to clear interrupt by preload configurations fault. + 1 + 1 + write-only + + + DCACHE_SYNC_OP_FAULT_INT_CLR + The bit is used to clear interrupt by sync configurations fault. + 2 + 1 + write-only + + + DCACHE_PRELOAD_OP_FAULT_INT_CLR + The bit is used to clear interrupt by preload configurations fault. + 3 + 1 + write-only + + + DCACHE_WRITE_FLASH_INT_CLR + The bit is used to clear interrupt by dcache trying to write flash. + 4 + 1 + write-only + + + MMU_ENTRY_FAULT_INT_CLR + The bit is used to clear interrupt by mmu entry fault. + 5 + 1 + write-only + + + DCACHE_OCCUPY_EXC_INT_CLR + The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + write-only + + + IBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by ibus counter overflow. + 7 + 1 + write-only + + + DBUS_CNT_OVF_INT_CLR + The bit is used to clear interrupt by dbus counter overflow. + 8 + 1 + write-only + + + + + CACHE_ILG_INT_ST + ******* Description *********** + 0xE4 + 0x20 + + + ICACHE_SYNC_OP_FAULT_ST + The bit is used to indicate interrupt by sync configurations fault. + 0 + 1 + read-only + + + ICACHE_PRELOAD_OP_FAULT_ST + The bit is used to indicate interrupt by preload configurations fault. + 1 + 1 + read-only + + + DCACHE_SYNC_OP_FAULT_ST + The bit is used to indicate interrupt by sync configurations fault. + 2 + 1 + read-only + + + DCACHE_PRELOAD_OP_FAULT_ST + The bit is used to indicate interrupt by preload configurations fault. + 3 + 1 + read-only + + + DCACHE_WRITE_FLASH_ST + The bit is used to indicate interrupt by dcache trying to write flash. + 4 + 1 + read-only + + + MMU_ENTRY_FAULT_ST + The bit is used to indicate interrupt by mmu entry fault. + 5 + 1 + read-only + + + DCACHE_OCCUPY_EXC_ST + The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + 6 + 1 + read-only + + + IBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + 7 + 1 + read-only + + + IBUS_ACS_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. + 8 + 1 + read-only + + + DBUS_ACS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + 9 + 1 + read-only + + + DBUS_ACS_FLASH_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access flash miss counter overflow. + 10 + 1 + read-only + + + DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST + The bit is used to indicate interrupt by dbus access spiram miss counter overflow. + 11 + 1 + read-only + + + + + CORE0_ACS_CACHE_INT_ENA + ******* Description *********** + 0xE8 + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 0 + 1 + read-write + + + CORE0_IBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by ibus trying to write icache + 1 + 1 + read-write + + + CORE0_IBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 2 + 1 + read-write + + + CORE0_DBUS_ACS_MSK_DC_INT_ENA + The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + 3 + 1 + read-write + + + CORE0_DBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 4 + 1 + read-write + + + + + CORE0_ACS_CACHE_INT_CLR + ******* Description *********** + 0xEC + 0x20 + + + CORE0_IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + CORE0_IBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by ibus trying to write icache + 1 + 1 + write-only + + + CORE0_IBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 2 + 1 + write-only + + + CORE0_DBUS_ACS_MSK_DC_INT_CLR + The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + write-only + + + CORE0_DBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + + + CORE0_ACS_CACHE_INT_ST + ******* Description *********** + 0xF0 + 0x20 + + + CORE0_IBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + CORE0_IBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by ibus trying to write icache + 1 + 1 + read-only + + + CORE0_IBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 2 + 1 + read-only + + + CORE0_DBUS_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + read-only + + + CORE0_DBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 4 + 1 + read-only + + + + + CORE1_ACS_CACHE_INT_ENA + ******* Description *********** + 0xF4 + 0x20 + + + CORE1_IBUS_ACS_MSK_IC_INT_ENA + The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + 0 + 1 + read-write + + + CORE1_IBUS_WR_IC_INT_ENA + The bit is used to enable interrupt by ibus trying to write icache + 1 + 1 + read-write + + + CORE1_IBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 2 + 1 + read-write + + + CORE1_DBUS_ACS_MSK_DC_INT_ENA + The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + 3 + 1 + read-write + + + CORE1_DBUS_REJECT_INT_ENA + The bit is used to enable interrupt by authentication fail. + 4 + 1 + read-write + + + + + CORE1_ACS_CACHE_INT_CLR + ******* Description *********** + 0xF8 + 0x20 + + + CORE1_IBUS_ACS_MSK_IC_INT_CLR + The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + write-only + + + CORE1_IBUS_WR_IC_INT_CLR + The bit is used to clear interrupt by ibus trying to write icache + 1 + 1 + write-only + + + CORE1_IBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 2 + 1 + write-only + + + CORE1_DBUS_ACS_MSK_DC_INT_CLR + The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + write-only + + + CORE1_DBUS_REJECT_INT_CLR + The bit is used to clear interrupt by authentication fail. + 4 + 1 + write-only + + + + + CORE1_ACS_CACHE_INT_ST + ******* Description *********** + 0xFC + 0x20 + + + CORE1_IBUS_ACS_MSK_ICACHE_ST + The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access. + 0 + 1 + read-only + + + CORE1_IBUS_WR_ICACHE_ST + The bit is used to indicate interrupt by ibus trying to write icache + 1 + 1 + read-only + + + CORE1_IBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 2 + 1 + read-only + + + CORE1_DBUS_ACS_MSK_DCACHE_ST + The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access. + 3 + 1 + read-only + + + CORE1_DBUS_REJECT_ST + The bit is used to indicate interrupt by authentication fail. + 4 + 1 + read-only + + + + + CORE0_DBUS_REJECT_ST + ******* Description *********** + 0x100 + 0x20 + + + CORE0_DBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE0_DBUS_ATTR + The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 3 + 3 + read-only + + + CORE0_DBUS_WORLD + The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE0_DBUS_REJECT_VADDR + ******* Description *********** + 0x104 + 0x20 + 0xFFFFFFFF + + + CORE0_DBUS_VADDR + The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + 0 + 32 + read-only + + + + + CORE0_IBUS_REJECT_ST + ******* Description *********** + 0x108 + 0x20 + + + CORE0_IBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE0_IBUS_ATTR + The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 3 + 3 + read-only + + + CORE0_IBUS_WORLD + The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE0_IBUS_REJECT_VADDR + ******* Description *********** + 0x10C + 0x20 + 0xFFFFFFFF + + + CORE0_IBUS_VADDR + The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + 0 + 32 + read-only + + + + + CORE1_DBUS_REJECT_ST + ******* Description *********** + 0x110 + 0x20 + + + CORE1_DBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE1_DBUS_ATTR + The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 3 + 3 + read-only + + + CORE1_DBUS_WORLD + The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE1_DBUS_REJECT_VADDR + ******* Description *********** + 0x114 + 0x20 + 0xFFFFFFFF + + + CORE1_DBUS_VADDR + The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + 0 + 32 + read-only + + + + + CORE1_IBUS_REJECT_ST + ******* Description *********** + 0x118 + 0x20 + + + CORE1_IBUS_TAG_ATTR + The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able. + 0 + 3 + read-only + + + CORE1_IBUS_ATTR + The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able + 3 + 3 + read-only + + + CORE1_IBUS_WORLD + The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1 + 6 + 1 + read-only + + + + + CORE1_IBUS_REJECT_VADDR + ******* Description *********** + 0x11C + 0x20 + 0xFFFFFFFF + + + CORE1_IBUS_VADDR + The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + 0 + 32 + read-only + + + + + CACHE_MMU_FAULT_CONTENT + ******* Description *********** + 0x120 + 0x20 + + + CACHE_MMU_FAULT_CONTENT + The bits are used to indicate the content of mmu entry which cause mmu fault.. + 0 + 16 + read-only + + + CACHE_MMU_FAULT_CODE + The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. + 16 + 4 + read-only + + + + + CACHE_MMU_FAULT_VADDR + ******* Description *********** + 0x124 + 0x20 + + + CACHE_MMU_FAULT_VADDR + The bits are used to indicate the virtual address which cause mmu fault.. + 0 + 32 + read-only + + + + + CACHE_WRAP_AROUND_CTRL + ******* Description *********** + 0x128 + 0x20 + + + CACHE_FLASH_WRAP_AROUND + The bit is used to enable wrap around mode when read data from flash. + 0 + 1 + read-write + + + CACHE_SRAM_RD_WRAP_AROUND + The bit is used to enable wrap around mode when read data from spiram. + 1 + 1 + read-write + + + + + CACHE_MMU_POWER_CTRL + ******* Description *********** + 0x12C + 0x20 + 0x00000005 + + + CACHE_MMU_MEM_FORCE_ON + The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable + 0 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PD + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down + 1 + 1 + read-write + + + CACHE_MMU_MEM_FORCE_PU + The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up + 2 + 1 + read-write + + + + + CACHE_STATE + ******* Description *********** + 0x130 + 0x20 + + + ICACHE_STATE + The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 0 + 12 + read-only + + + DCACHE_STATE + The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state + 12 + 12 + read-only + + + + + CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + ******* Description *********** + 0x134 + 0x20 + + + RECORD_DISABLE_DB_ENCRYPT + Reserved + 0 + 1 + read-write + + + RECORD_DISABLE_G0CB_DECRYPT + Reserved + 1 + 1 + read-write + + + + + CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + ******* Description *********** + 0x138 + 0x20 + 0x00000007 + + + CLK_FORCE_ON_MANUAL_CRYPT + The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + CLK_FORCE_ON_AUTO_CRYPT + The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating. + 1 + 1 + read-write + + + CLK_FORCE_ON_CRYPT + The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating. + 2 + 1 + read-write + + + + + CACHE_BRIDGE_ARBITER_CTRL + ******* Description *********** + 0x13C + 0x20 + + + ALLOC_WB_HOLD_ARBITER + Reserved + 0 + 1 + read-write + + + + + CACHE_PRELOAD_INT_CTRL + ******* Description *********** + 0x140 + 0x20 + + + ICACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by icache pre-load done. + 0 + 1 + read-only + + + ICACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by icache pre-load done. + 1 + 1 + read-write + + + ICACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by icache pre-load done. + 2 + 1 + write-only + + + DCACHE_PRELOAD_INT_ST + The bit is used to indicate the interrupt by dcache pre-load done. + 3 + 1 + read-only + + + DCACHE_PRELOAD_INT_ENA + The bit is used to enable the interrupt by dcache pre-load done. + 4 + 1 + read-write + + + DCACHE_PRELOAD_INT_CLR + The bit is used to clear the interrupt by dcache pre-load done. + 5 + 1 + write-only + + + + + CACHE_SYNC_INT_CTRL + ******* Description *********** + 0x144 + 0x20 + + + ICACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by icache sync done. + 0 + 1 + read-only + + + ICACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by icache sync done. + 1 + 1 + read-write + + + ICACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by icache sync done. + 2 + 1 + write-only + + + DCACHE_SYNC_INT_ST + The bit is used to indicate the interrupt by dcache sync done. + 3 + 1 + read-only + + + DCACHE_SYNC_INT_ENA + The bit is used to enable the interrupt by dcache sync done. + 4 + 1 + read-write + + + DCACHE_SYNC_INT_CLR + The bit is used to clear the interrupt by dcache sync done. + 5 + 1 + write-only + + + + + CACHE_MMU_OWNER + ******* Description *********** + 0x148 + 0x20 + + + CACHE_MMU_OWNER + The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved. + 0 + 24 + read-write + + + + + CACHE_CONF_MISC + ******* Description *********** + 0x14C + 0x20 + 0x00000007 + + + CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by preload operation. + 0 + 1 + read-write + + + CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + The bit is used to disable checking mmu entry fault by sync operation. + 1 + 1 + read-write + + + CACHE_TRACE_ENA + The bit is used to enable cache trace function. + 2 + 1 + read-write + + + + + DCACHE_FREEZE + ******* Description *********** + 0x150 + 0x20 + 0x00000004 + + + ENA + The bit is used to enable dcache freeze mode + 0 + 1 + read-write + + + MODE + The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + 1 + 1 + read-write + + + DONE + The bit is used to indicate dcache freeze success + 2 + 1 + read-only + + + + + ICACHE_FREEZE + ******* Description *********** + 0x154 + 0x20 + 0x00000004 + + + ENA + The bit is used to enable icache freeze mode + 0 + 1 + read-write + + + MODE + The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss + 1 + 1 + read-write + + + DONE + The bit is used to indicate icache freeze success + 2 + 1 + read-only + + + + + ICACHE_ATOMIC_OPERATE_ENA + ******* Description *********** + 0x158 + 0x20 + 0x00000001 + + + ICACHE_ATOMIC_OPERATE_ENA + The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation. + 0 + 1 + read-write + + + + + DCACHE_ATOMIC_OPERATE_ENA + ******* Description *********** + 0x15C + 0x20 + 0x00000001 + + + DCACHE_ATOMIC_OPERATE_ENA + The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation. + 0 + 1 + read-write + + + + + CACHE_REQUEST + ******* Description *********** + 0x160 + 0x20 + + + BYPASS + The bit is used to disable request recording which could cause performance issue + 0 + 1 + read-write + + + + + CLOCK_GATE + ******* Description *********** + 0x164 + 0x20 + 0x00000001 + + + CLK_EN + Reserved + 0 + 1 + read-write + + + + + CACHE_TAG_OBJECT_CTRL + ******* Description *********** + 0x180 + 0x20 + + + ICACHE_TAG_OBJECT + Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register. + 0 + 1 + read-write + + + DCACHE_TAG_OBJECT + Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-write + + + + + CACHE_TAG_WAY_OBJECT + ******* Description *********** + 0x184 + 0x20 + + + CACHE_TAG_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7. + 0 + 3 + read-write + + + + + CACHE_VADDR + ******* Description *********** + 0x188 + 0x20 + + + CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + CACHE_TAG_CONTENT + ******* Description *********** + 0x18C + 0x20 + + + CACHE_TAG_CONTENT + This is a constant place where we can write data to or read data from the tag memory on the specified cache. + 0 + 32 + read-write + + + + + DATE + ******* Description *********** + 0x3FC + 0x20 + 0x02012310 + + + DATE + version information. + 0 + 28 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x60004000 + + 0x0 + 0x634 + registers + + + GPIO + 16 + + + GPIO_NMI + 17 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT1 + GPIO output register for GPIO32-53 + 0x10 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO32-53 + 0 + 22 + + + + + OUT1_W1TS + GPIO output set register for GPIO32-53 + 0x14 + 0x20 + + + OUT1_W1TS + GPIO output set register for GPIO32-53 + 0 + 22 + write-only + + + + + OUT1_W1TC + GPIO output clear register for GPIO32-53 + 0x18 + 0x20 + + + OUT1_W1TC + GPIO output clear register for GPIO32-53 + 0 + 22 + write-only + + + + + SDIO_SELECT + GPIO sdio select register + 0x1C + 0x20 + + + SDIO_SEL + GPIO sdio select register + 0 + 8 + read-write + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE1 + GPIO output enable register for GPIO32-53 + 0x2C + 0x20 + + + DATA + GPIO output enable register for GPIO32-53 + 0 + 22 + read-write + + + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-53 + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-53 + 0 + 22 + write-only + + + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-53 + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-53 + 0 + 22 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-write + + + + + IN1 + GPIO input register for GPIO32-53 + 0x40 + 0x20 + + + DATA_NEXT + GPIO input register for GPIO32-53 + 0 + 22 + read-write + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS1 + GPIO interrupt status register for GPIO32-53 + 0x50 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO32-53 + 0 + 22 + read-write + + + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-53 + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-53 + 0 + 22 + write-only + + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-53 + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-53 + 0 + 22 + write-only + + + + + PCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0x5C + 0x20 + + + PROCPU_INT + GPIO PRO_CPU interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0x60 + 0x20 + + + PROCPU_NMI_INT + GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + CPUSDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0x64 + 0x20 + + + SDIO_INT + GPIO CPUSDIO interrupt status register for GPIO0-31 + 0 + 32 + read-only + + + + + PCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-53 + 0x68 + 0x20 + + + PROCPU_INT1 + GPIO PRO_CPU interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + PCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + 0x6C + 0x20 + + + PROCPU_NMI_INT1 + GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + CPUSDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-53 + 0x70 + 0x20 + + + SDIO_INT1 + GPIO CPUSDIO interrupt status register for GPIO32-53 + 0 + 22 + read-only + + + + + 54 + 0x4 + 0-53 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x14C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-53 + 0x150 + 0x20 + + + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-53 + 0 + 22 + read-only + + + + + 256 + 0x4 + 0-255 + FUNC%s_IN_SEL_CFG + GPIO input function configuration register + 0x154 + 0x20 + + + IN_SEL + set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. + 0 + 6 + read-write + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + 54 + 0x4 + 0-53 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x554 + 0x20 + 0x00000100 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 9 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 9 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 10 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 11 + 1 + read-write + + + + + CLOCK_GATE + GPIO clock gate register + 0x62C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + REG_DATE + GPIO version register + 0x6FC + 0x20 + 0x01907040 + + + REG_DATE + version register + 0 + 28 + read-write + + + + + + + GPIOSD + Sigma-Delta Modulation + GPIOSD + 0x60004F00 + + 0x0 + 0x2C + registers + + + + 8 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + SIGMADELTA_CG + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 31 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + SIGMADELTA_VERSION + Version Control Register + 0x28 + 0x20 + 0x01802260 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x6003E000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUREY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x02101070 + + + DATE + Hmac date information/ hmac version information. + 0 + 28 + read-write + + + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller + I2C + 0x60013000 + + 0x0 + 0x90 + registers + + + I2C_MST + 11 + + + I2C_EXT0 + 42 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x0000020B + + + SDA_FORCE_OUT + 0: direct output; 1: open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + 0: direct output; 1: open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + This register is used to select the sample mode. +1: sample SDA data on the SCL low level. +0: sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Set this bit to configure the module as an I2C Master. Clear this bit to configure the +module as an I2C Slave. + 4 + 1 + read-write + + + TRANS_START + Set this bit to start sending the data in txfifo. + 5 + 1 + write-only + + + TX_LSB_FIRST + This bit is used to control the sending mode for data needing to be sent. +1: send data from the least significant bit; +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + This bit is used to control the storage mode for received data. +1: receive data from the least significant bit; +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Reserved + 8 + 1 + read-write + + + ARBITRATION_EN + This is the enable bit for arbitration_lost. + 9 + 1 + read-write + + + FSM_RST + This register is used to reset the scl FMS. + 10 + 1 + write-only + + + CONF_UPGATE + synchronization bit + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + This is the enable bit for slave to send data automatically + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + This is the enable bit to support the 7bit general call function. + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + When in slave mode, 1: master reads from slave; 0: master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + When the I2C controller loses control of SCL line, this register changes to 1. + 3 + 1 + read-only + + + BUS_BUSY + 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + When configured as an I2C Slave, and the address sent by the master is +equal to the address of the slave, then this bit will be of high level. + 5 + 1 + read-only + + + RXFIFO_CNT + This field represents the amount of data needed to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + This field stores the amount of received data in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + This field indicates the states of the I2C module state machine. +0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + This field indicates the states of the state machine used to produce SCL. +0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + This register is used to configure the timeout for receiving a data bit in APB +clock cycles. + 0 + 5 + read-write + + + TIME_OUT_EN + This is the enable bit for time out control. + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + When configured as an I2C Slave, this field is used to configure the slave address. + 0 + 15 + read-write + + + ADDR_10BIT_EN + This field is used to enable the slave 10-bit addressing mode in master mode. + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + This is the offset address of the APB reading from rxfifo + 0 + 5 + read-only + + + RXFIFO_WADDR + This is the offset address of i2c module receiving data and writing to rxfifo. + 5 + 5 + read-only + + + TXFIFO_RADDR + This is the offset address of i2c module reading from txfifo. + 10 + 5 + read-only + + + TXFIFO_WADDR + This is the offset address of APB bus writing to txfifo. + 15 + 5 + read-only + + + SLAVE_RW_POINT + The received data in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Set this bit to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. + 11 + 1 + read-write + + + RX_FIFO_RST + Set this bit to reset rx-fifo. + 12 + 1 + read-write + + + TX_FIFO_RST + Set this bit to reset tx-fifo. + 13 + 1 + read-write + + + FIFO_PRT_EN + The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + The value of rx FIFO read data. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Set this bit to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Set this bit to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Set this bit to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Set this bit to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Set this bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + The interrupt enable bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status bit for I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + This register is used to configure the time to hold the data after the negative +edge of SCL, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + This register is used to configure for how long SDA is sampled, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the negative edge +of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive +edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + This register is used to configure the delay after the STOP condition, +in I2C module clock cycles. + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + This register is used to configure the time between the positive edge +of SCL and the positive edge of SDA, in I2C module clock cycles. + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + When a pulse on the SCL input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 0 + 4 + read-write + + + SDA_FILTER_THRES + When a pulse on the SDA input has smaller width than this register value +in I2C module clock cycles, the I2C controller will ignore that pulse. + 4 + 4 + read-write + + + SCL_FILTER_EN + This is the filter enable bit for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + This is the filter enable bit for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL;1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + 8 + 0x4 + 0-7 + COMD%s + I2C command register %s + 0x58 + 0x20 + + + COMMAND + This is the content of command 0. It consists of three parts: +op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more +Information. + 0 + 14 + read-write + + + COMMAND_DONE + When command 0 is done in I2C Master mode, this bit changes to high +level. + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + 1 + 5 + read-write + + + SCL_PD_EN + The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + 6 + 1 + read-write + + + SDA_PD_EN + The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configure the period of I2C slave stretching SCL line. + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Set this bit to clear the I2C slave SCL stretch function. + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + The enable bit for slave to control ACK level function. + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x20070201 + + + DATE + This is the the version register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + This is the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + This is the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller + 0x60027000 + + I2C_EXT1 + 43 + + + + I2S0 + I2S (Inter-IC Sound) Controller + I2S + 0x6000F000 + + 0x0 + 0x5C + registers + + + I2S0 + 25 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 21 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 22 + 1 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_SD1_IN_DM + The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + RX_SD2_IN_DM + The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 8 + 2 + read-write + + + RX_SD3_IN_DM + The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 12 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02009070 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + I2S1 + I2S (Inter-IC Sound) Controller + I2S1 + 0x6002D000 + + 0x0 + 0x54 + registers + + + I2S1 + 26 + + + + I2S_INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + I2S_RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + I2S_TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + I2S_RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + I2S_TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + I2S_INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + I2S_RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + I2S_TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + I2S_RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + I2S_TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + I2S_INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + I2S_RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + I2S_TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + I2S_RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + I2S_TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + I2S_INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + I2S_RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + I2S_TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + I2S_RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + I2S_TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + I2S_RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + I2S_RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + I2S_RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + I2S_RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + I2S_RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + I2S_RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + I2S_RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + I2S_RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + I2S_RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + I2S_RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + I2S_RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + I2S_RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + I2S_RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + I2S_RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + I2S_RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + I2S_RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + I2S_RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + I2S_RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + I2S_TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x0000B200 + + + I2S_TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + I2S_TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + I2S_TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + I2S_TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + I2S_TX_MONO + Set this bit to enable transmitter in mono mode + 5 + 1 + read-write + + + I2S_TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 6 + 1 + read-write + + + I2S_TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + I2S_TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + I2S_TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + I2S_TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + I2S_TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + I2S_TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 13 + 1 + read-write + + + I2S_TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + I2S_TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + I2S_TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + I2S_TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + I2S_TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + I2S_TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + I2S_TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 24 + 3 + read-write + + + I2S_SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 27 + 1 + read-write + + + + + I2S_RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + I2S_RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + I2S_RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + I2S_RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + I2S_RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + I2S_RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + I2S_RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + I2S_TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x6F3DE300 + + + I2S_TX_TDM_WS_WIDTH + The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + I2S_TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 7 + 6 + read-write + + + I2S_TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + I2S_TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 18 + 6 + read-write + + + I2S_TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + I2S_TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 29 + 1 + read-write + + + I2S_TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 30 + 1 + read-write + + + + + I2S_RX_CLKM_CONF + I2S RX clock configure register + 0x30 + 0x20 + 0x00000002 + + + I2S_RX_CLKM_DIV_NUM + Integral I2S clock divider value + 0 + 8 + read-write + + + I2S_RX_CLK_ACTIVE + I2S Rx module clock enable signal. + 26 + 1 + read-write + + + I2S_RX_CLK_SEL + Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + I2S_MCLK_SEL + 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. + 29 + 1 + read-write + + + + + I2S_TX_CLKM_CONF + I2S TX clock configure register + 0x34 + 0x20 + 0x00000002 + + + I2S_TX_CLKM_DIV_NUM + Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. + 0 + 8 + read-write + + + I2S_TX_CLK_ACTIVE + I2S Tx module clock enable signal. + 26 + 1 + read-write + + + I2S_TX_CLK_SEL + Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. + 27 + 2 + read-write + + + I2S_CLK_EN + Set this bit to enable clk gate + 29 + 1 + read-write + + + + + I2S_RX_CLKM_DIV_CONF + I2S RX module clock divider configure register + 0x38 + 0x20 + 0x00000200 + + + I2S_RX_CLKM_DIV_Z + For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_RX_CLKM_DIV_Y + For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_RX_CLKM_DIV_X + For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_RX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + I2S_TX_CLKM_DIV_CONF + I2S TX module clock divider configure register + 0x3C + 0x20 + 0x00000200 + + + I2S_TX_CLKM_DIV_Z + For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). + 0 + 9 + read-write + + + I2S_TX_CLKM_DIV_Y + For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). + 9 + 9 + read-write + + + I2S_TX_CLKM_DIV_X + For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. + 18 + 9 + read-write + + + I2S_TX_CLKM_DIV_YN1 + For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. + 27 + 1 + read-write + + + + + I2S_RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + I2S_RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + I2S_RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + I2S_RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + I2S_RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + I2S_RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + I2S_RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + I2S_RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + I2S_RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + I2S_RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + I2S_RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + I2S_RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + I2S_TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + I2S_TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + I2S_TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + I2S_TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + I2S_TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + I2S_TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + I2S_TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + I2S_TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + I2S_TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + I2S_TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + I2S_TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + I2S_TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + I2S_TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + I2S_TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + I2S_TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + I2S_TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + I2S_TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + I2S_TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + I2S_TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + I2S_RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + I2S_RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + I2S_RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + I2S_RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + I2S_RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + I2S_RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + I2S_TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + I2S_TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + I2S_TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + I2S_TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + I2S_TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + I2S_TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + I2S_TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + I2S_LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + I2S_LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + I2S_LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + I2S_LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + I2S_RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + I2S_RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + I2S_CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + I2S_SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + I2S_STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + I2S_TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + I2S_DATE + Version control register + 0x80 + 0x20 + 0x02009070 + + + I2S_DATE + I2S version control register + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Core + INTERRUPT_CORE0 + 0x600C2000 + + 0x0 + 0x1A4 + registers + + + WIFI_MAC + 0 + + + WIFI_NMI + 1 + + + WIFI_BB + 2 + + + BT_MAC + 3 + + + BT_BB + 4 + + + BT_BB_NMI + 5 + + + RWBT + 6 + + + RWBLE + 7 + + + RWBT_NMI + 8 + + + RWBLE_NMI + 9 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE + 85 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE + 86 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE + 87 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE + 88 + + + CACHE_CORE0_ACS + 94 + + + + PRO_MAC_INTR_MAP + mac interrupt configuration register + 0x0 + 0x20 + 0x00000010 + + + MAC_INTR_MAP + this register used to map mac interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + MAC_NMI_MAP + mac_nmi interrupt configuration register + 0x4 + 0x20 + 0x00000010 + + + MAC_NMI_MAP + this register used to map_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWR_INTR_MAP + pwr interrupt configuration register + 0x8 + 0x20 + 0x00000010 + + + PWR_INTR_MAP + this register used to map pwr interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BB_INT_MAP + bb interrupt configuration register + 0xC + 0x20 + 0x00000010 + + + BB_INT_MAP + this register used to map bb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_MAC_INT_MAP + bb_mac interrupt configuration register + 0x10 + 0x20 + 0x00000010 + + + BT_MAC_INT_MAP + this register used to map bb_mac interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_BB_INT_MAP + bt_bb interrupt configuration register + 0x14 + 0x20 + 0x00000010 + + + BT_BB_INT_MAP + this register used to map bt_bb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + bt_bb_nmi interrupt configuration register + 0x18 + 0x20 + 0x00000010 + + + BT_BB_NMI_MAP + this register used to map bb_bt_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBT_IRQ_MAP + rwbt_irq interrupt configuration register + 0x1C + 0x20 + 0x00000010 + + + RWBT_IRQ_MAP + this register used to map rwbt_irq interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBLE_IRQ_MAP + rwble_irq interrupt configuration register + 0x20 + 0x20 + 0x00000010 + + + RWBLE_IRQ_MAP + this register used to map rwble_irq interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBT_NMI_MAP + rwbt_nmi interrupt configuration register + 0x24 + 0x20 + 0x00000010 + + + RWBT_NMI_MAP + this register used to map mac rwbt_nmi to one of core0's external interrupt + 0 + 5 + read-write + + + + + RWBLE_NMI_MAP + rwble_nmi interrupt configuration register + 0x28 + 0x20 + 0x00000010 + + + RWBLE_NMI_MAP + this register used to map rwble_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_MST_INT_MAP + i2c_mst interrupt configuration register + 0x2C + 0x20 + 0x00000010 + + + I2C_MST_INT_MAP + this register used to map i2c_mst interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + slc0 interrupt configuration register + 0x30 + 0x20 + 0x00000010 + + + SLC0_INTR_MAP + this register used to map slc0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + slc1 interrupt configuration register + 0x34 + 0x20 + 0x00000010 + + + SLC1_INTR_MAP + this register used to map slc1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + uhci0 interrupt configuration register + 0x38 + 0x20 + 0x00000010 + + + UHCI0_INTR_MAP + this register used to map uhci0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UHCI1_INTR_MAP + uhci1 interrupt configuration register + 0x3C + 0x20 + 0x00000010 + + + UHCI1_INTR_MAP + this register used to map uhci1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + gpio_interrupt_pro interrupt configuration register + 0x40 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_MAP + this register used to map gpio_interrupt_pro interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + gpio_interrupt_pro_nmi interrupt configuration register + 0x44 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_NMI_MAP + this register used to map gpio_interrupt_pro_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_MAP + gpio_interrupt_app interrupt configuration register + 0x48 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_MAP + this register used to map gpio_interrupt_app interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_NMI_MAP + gpio_interrupt_app_nmi interrupt configuration register + 0x4C + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_NMI_MAP + this register used to map gpio_interrupt_app_nmi interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_1_MAP + spi_intr_1 interrupt configuration register + 0x50 + 0x20 + 0x00000010 + + + SPI_INTR_1_MAP + this register used to map spi_intr_1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_2_MAP + spi_intr_2 interrupt configuration register + 0x54 + 0x20 + 0x00000010 + + + SPI_INTR_2_MAP + this register used to map spi_intr_2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_3_MAP + spi_intr_3 interrupt configuration register + 0x58 + 0x20 + 0x00000010 + + + SPI_INTR_3_MAP + this register used to map spi_intr_3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_4_MAP + spi_intr_4 interrupt configuration register + 0x5C + 0x20 + 0x00000010 + + + SPI_INTR_4_MAP + this register used to map spi_intr_4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + LCD_CAM_INT_MAP + lcd_cam interrupt configuration register + 0x60 + 0x20 + 0x00000010 + + + LCD_CAM_INT_MAP + this register used to map lcd_cam interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2S0_INT_MAP + i2s0 interrupt configuration register + 0x64 + 0x20 + 0x00000010 + + + I2S0_INT_MAP + this register used to map i2s0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2S1_INT_MAP + i2s1 interrupt configuration register + 0x68 + 0x20 + 0x00000010 + + + I2S1_INT_MAP + this register used to map i2s1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART_INTR_MAP + uart interrupt configuration register + 0x6C + 0x20 + 0x00000010 + + + UART_INTR_MAP + this register used to map uart interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART1_INTR_MAP + uart1 interrupt configuration register + 0x70 + 0x20 + 0x00000010 + + + UART1_INTR_MAP + this register used to map uart1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + UART2_INTR_MAP + uart2 interrupt configuration register + 0x74 + 0x20 + 0x00000010 + + + UART2_INTR_MAP + this register used to map uart2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SDIO_HOST_INTERRUPT_MAP + sdio_host interrupt configuration register + 0x78 + 0x20 + 0x00000010 + + + SDIO_HOST_INTERRUPT_MAP + this register used to map sdio_host interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM0_INTR_MAP + pwm0 interrupt configuration register + 0x7C + 0x20 + 0x00000010 + + + PWM0_INTR_MAP + this register used to map pwm0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM1_INTR_MAP + pwm1 interrupt configuration register + 0x80 + 0x20 + 0x00000010 + + + PWM1_INTR_MAP + this register used to map pwm1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM2_INTR_MAP + pwm2 interrupt configuration register + 0x84 + 0x20 + 0x00000010 + + + PWM2_INTR_MAP + this register used to map pwm2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PWM3_INTR_MAP + pwm3 interrupt configuration register + 0x88 + 0x20 + 0x00000010 + + + PWM3_INTR_MAP + this register used to map pwm3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + LEDC_INT_MAP + ledc interrupt configuration register + 0x8C + 0x20 + 0x00000010 + + + LEDC_INT_MAP + this register used to map ledc interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + EFUSE_INT_MAP + efuse interrupt configuration register + 0x90 + 0x20 + 0x00000010 + + + EFUSE_INT_MAP + this register used to map efuse interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CAN_INT_MAP + can interrupt configuration register + 0x94 + 0x20 + 0x00000010 + + + CAN_INT_MAP + this register used to map can interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + USB_INTR_MAP + usb interrupt configuration register + 0x98 + 0x20 + 0x00000010 + + + USB_INTR_MAP + this register used to map usb interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RTC_CORE_INTR_MAP + rtc_core interrupt configuration register + 0x9C + 0x20 + 0x00000010 + + + RTC_CORE_INTR_MAP + this register used to map rtc_core interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RMT_INTR_MAP + rmt interrupt configuration register + 0xA0 + 0x20 + 0x00000010 + + + RMT_INTR_MAP + this register used to map rmt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PCNT_INTR_MAP + pcnt interrupt configuration register + 0xA4 + 0x20 + 0x00000010 + + + PCNT_INTR_MAP + this register used to map pcnt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + i2c_ext0 interrupt configuration register + 0xA8 + 0x20 + 0x00000010 + + + I2C_EXT0_INTR_MAP + this register used to map i2c_ext0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT1_INTR_MAP + i2c_ext1 interrupt configuration register + 0xAC + 0x20 + 0x00000010 + + + I2C_EXT1_INTR_MAP + this register used to map i2c_ext1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI2_DMA_INT_MAP + spi2_dma interrupt configuration register + 0xB0 + 0x20 + 0x00000010 + + + SPI2_DMA_INT_MAP + this register used to map spi2_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI3_DMA_INT_MAP + spi3_dma interrupt configuration register + 0xB4 + 0x20 + 0x00000010 + + + SPI3_DMA_INT_MAP + this register used to map spi3_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI4_DMA_INT_MAP + spi4_dma interrupt configuration register + 0xB8 + 0x20 + 0x00000010 + + + SPI4_DMA_INT_MAP + this register used to map spi4_dma interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + WDG_INT_MAP + wdg interrupt configuration register + 0xBC + 0x20 + 0x00000010 + + + WDG_INT_MAP + this register used to map wdg interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT1_MAP + timer_int1 interrupt configuration register + 0xC0 + 0x20 + 0x00000010 + + + TIMER_INT1_MAP + this register used to map timer_int1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT2_MAP + timer_int2 interrupt configuration register + 0xC4 + 0x20 + 0x00000010 + + + TIMER_INT2_MAP + this register used to map timer_int2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_T0_INT_MAP + tg_t0 interrupt configuration register + 0xC8 + 0x20 + 0x00000010 + + + TG_T0_INT_MAP + this register used to map tg_t0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_T1_INT_MAP + tg_t1 interrupt configuration register + 0xCC + 0x20 + 0x00000010 + + + TG_T1_INT_MAP + this register used to map tg_t1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG_WDT_INT_MAP + tg_wdt interrupt configuration register + 0xD0 + 0x20 + 0x00000010 + + + TG_WDT_INT_MAP + this register used to map rg_wdt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_T0_INT_MAP + tg1_t0 interrupt configuration register + 0xD4 + 0x20 + 0x00000010 + + + TG1_T0_INT_MAP + this register used to map tg1_t0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_T1_INT_MAP + tg1_t1 interrupt configuration register + 0xD8 + 0x20 + 0x00000010 + + + TG1_T1_INT_MAP + this register used to map tg1_t1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + TG1_WDT_INT_MAP + tg1_wdt interrupt configuration register + 0xDC + 0x20 + 0x00000010 + + + TG1_WDT_INT_MAP + this register used to map tg1_wdt interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_IA_INT_MAP + cache_ia interrupt configuration register + 0xE0 + 0x20 + 0x00000010 + + + CACHE_IA_INT_MAP + this register used to map cache_ia interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + systimer_target0 interrupt configuration register + 0xE4 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET0_INT_MAP + this register used to map systimer_target0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + systimer_target1 interrupt configuration register + 0xE8 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET1_INT_MAP + this register used to map systimer_target1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + systimer_target2 interrupt configuration register + 0xEC + 0x20 + 0x00000010 + + + SYSTIMER_TARGET2_INT_MAP + this register used to map systimer_target2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SPI_MEM_REJECT_INTR_MAP + spi_mem_reject interrupt configuration register + 0xF0 + 0x20 + 0x00000010 + + + SPI_MEM_REJECT_INTR_MAP + this register used to map spi_mem_reject interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DCACHE_PRELOAD_INT_MAP + dcache_prelaod interrupt configuration register + 0xF4 + 0x20 + 0x00000010 + + + DCACHE_PRELOAD_INT_MAP + this register used to map dcache_prelaod interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ICACHE_PRELOAD_INT_MAP + icache_preload interrupt configuration register + 0xF8 + 0x20 + 0x00000010 + + + ICACHE_PRELOAD_INT_MAP + this register used to map icache_preload interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DCACHE_SYNC_INT_MAP + dcache_sync interrupt configuration register + 0xFC + 0x20 + 0x00000010 + + + DCACHE_SYNC_INT_MAP + this register used to map dcache_sync interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ICACHE_SYNC_INT_MAP + icache_sync interrupt configuration register + 0x100 + 0x20 + 0x00000010 + + + ICACHE_SYNC_INT_MAP + this register used to map icache_sync interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + APB_ADC_INT_MAP + apb_adc interrupt configuration register + 0x104 + 0x20 + 0x00000010 + + + APB_ADC_INT_MAP + this register used to map apb_adc interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH0_INT_MAP + dma_in_ch0 interrupt configuration register + 0x108 + 0x20 + 0x00000010 + + + DMA_IN_CH0_INT_MAP + this register used to map dma_in_ch0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH1_INT_MAP + dma_in_ch1 interrupt configuration register + 0x10C + 0x20 + 0x00000010 + + + DMA_IN_CH1_INT_MAP + this register used to map dma_in_ch1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH2_INT_MAP + dma_in_ch2 interrupt configuration register + 0x110 + 0x20 + 0x00000010 + + + DMA_IN_CH2_INT_MAP + this register used to map dma_in_ch2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH3_INT_MAP + dma_in_ch3 interrupt configuration register + 0x114 + 0x20 + 0x00000010 + + + DMA_IN_CH3_INT_MAP + this register used to map dma_in_ch3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH4_INT_MAP + dma_in_ch4 interrupt configuration register + 0x118 + 0x20 + 0x00000010 + + + DMA_IN_CH4_INT_MAP + this register used to map dma_in_ch4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH0_INT_MAP + dma_out_ch0 interrupt configuration register + 0x11C + 0x20 + 0x00000010 + + + DMA_OUT_CH0_INT_MAP + this register used to map dma_out_ch0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH1_INT_MAP + dma_out_ch1 interrupt configuration register + 0x120 + 0x20 + 0x00000010 + + + DMA_OUT_CH1_INT_MAP + this register used to map dma_out_ch1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INT_MAP + dma_out_ch2 interrupt configuration register + 0x124 + 0x20 + 0x00000010 + + + DMA_OUT_CH2_INT_MAP + this register used to map dma_out_ch2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH3_INT_MAP + dma_out_ch3 interrupt configuration register + 0x128 + 0x20 + 0x00000010 + + + DMA_OUT_CH3_INT_MAP + this register used to map dma_out_ch3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH4_INT_MAP + dma_out_ch4 interrupt configuration register + 0x12C + 0x20 + 0x00000010 + + + DMA_OUT_CH4_INT_MAP + this register used to map dma_out_ch4 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + RSA_INT_MAP + rsa interrupt configuration register + 0x130 + 0x20 + 0x00000010 + + + RSA_INT_MAP + this register used to map rsa interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + AES_INT_MAP + aes interrupt configuration register + 0x134 + 0x20 + 0x00000010 + + + AES_INT_MAP + this register used to map aes interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + SHA_INT_MAP + sha interrupt configuration register + 0x138 + 0x20 + 0x00000010 + + + SHA_INT_MAP + this register used to map sha interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + cpu_intr_from_cpu_0 interrupt configuration register + 0x13C + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_0_MAP + this register used to map cpu_intr_from_cpu_0 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + cpu_intr_from_cpu_1 interrupt configuration register + 0x140 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_1_MAP + this register used to map cpu_intr_from_cpu_1 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + cpu_intr_from_cpu_2 interrupt configuration register + 0x144 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_2_MAP + this register used to map cpu_intr_from_cpu_2 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + cpu_intr_from_cpu_3 interrupt configuration register + 0x148 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_3_MAP + this register used to map cpu_intr_from_cpu_3 interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + assist_debug interrupt configuration register + 0x14C + 0x20 + 0x00000010 + + + ASSIST_DEBUG_INTR_MAP + this register used to map assist_debug interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + dma_pms_monitor_violatile interrupt configuration register + 0x150 + 0x20 + 0x00000010 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map dma_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_IRam0_pms_monitor_violatile interrupt configuration register + 0x154 + 0x20 + 0x00000010 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_DRam0_pms_monitor_violatile interrupt configuration register + 0x158 + 0x20 + 0x00000010 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core0_PIF_pms_monitor_violatile interrupt configuration register + 0x15C + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core0_PIF_pms_monitor_violatile_size interrupt configuration register + 0x160 + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_IRam0_pms_monitor_violatile interrupt configuration register + 0x164 + 0x20 + 0x00000010 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_DRam0_pms_monitor_violatile interrupt configuration register + 0x168 + 0x20 + 0x00000010 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core1_PIF_pms_monitor_violatile interrupt configuration register + 0x16C + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core1_PIF_pms_monitor_violatile_size interrupt configuration register + 0x170 + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + BACKUP_PMS_VIOLATE_INTR_MAP + backup_pms_monitor_violatile interrupt configuration register + 0x174 + 0x20 + 0x00000010 + + + BACKUP_PMS_VIOLATE_INTR_MAP + this register used to map backup_pms_monitor_violatile interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE0_ACS_INT_MAP + cache_core0_acs interrupt configuration register + 0x178 + 0x20 + 0x00000010 + + + CACHE_CORE0_ACS_INT_MAP + this register used to map cache_core0_acs interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE1_ACS_INT_MAP + cache_core1_acs interrupt configuration register + 0x17C + 0x20 + 0x00000010 + + + CACHE_CORE1_ACS_INT_MAP + this register used to map cache_core1_acs interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + USB_DEVICE_INT_MAP + usb_device interrupt configuration register + 0x180 + 0x20 + 0x00000010 + + + USB_DEVICE_INT_MAP + this register used to map usb_device interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PERI_BACKUP_INT_MAP + peri_backup interrupt configuration register + 0x184 + 0x20 + 0x00000010 + + + PERI_BACKUP_INT_MAP + this register used to map peri_backup interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + DMA_EXTMEM_REJECT_INT_MAP + dma_extmem_reject interrupt configuration register + 0x188 + 0x20 + 0x00000010 + + + DMA_EXTMEM_REJECT_INT_MAP + this register used to map dma_extmem_reject interrupt to one of core0's external interrupt + 0 + 5 + read-write + + + + + PRO_INTR_STATUS_0 + interrupt status register + 0x18C + 0x20 + + + INTR_STATUS_0 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_1 + interrupt status register + 0x190 + 0x20 + + + INTR_STATUS_1 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_2 + interrupt status register + 0x194 + 0x20 + + + INTR_STATUS_2 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + PRO_INTR_STATUS_3 + interrupt status register + 0x198 + 0x20 + + + INTR_STATUS_3 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + CLOCK_GATE + clock gate register + 0x19C + 0x20 + 0x00000001 + + + REG_CLK_EN + this register uesd to control clock-gating interupt martrix + 0 + 1 + read-write + + + + + DATE + version register + 0x7FC + 0x20 + 0x02012300 + + + INTERRUPT_REG_DATE + version register + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE1 + Interrupt Core + INTERRUPT_CORE1 + 0x600C2800 + + 0x0 + 0x1A4 + registers + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE + 89 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE + 90 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE + 91 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE + 92 + + + CACHE_CORE1_ACS + 95 + + + + APP_MAC_INTR_MAP + mac interrupt configuration register + 0x800 + 0x20 + 0x00000010 + + + MAC_INTR_MAP + this register used to map mac interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + MAC_NMI_MAP + mac_nmi interrupt configuration register + 0x804 + 0x20 + 0x00000010 + + + MAC_NMI_MAP + this register used to map_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWR_INTR_MAP + pwr interrupt configuration register + 0x808 + 0x20 + 0x00000010 + + + PWR_INTR_MAP + this register used to map pwr interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BB_INT_MAP + bb interrupt configuration register + 0x80C + 0x20 + 0x00000010 + + + BB_INT_MAP + this register used to map bb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_MAC_INT_MAP + bb_mac interrupt configuration register + 0x810 + 0x20 + 0x00000010 + + + BT_MAC_INT_MAP + this register used to map bb_mac interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_BB_INT_MAP + bt_bb interrupt configuration register + 0x814 + 0x20 + 0x00000010 + + + BT_BB_INT_MAP + this register used to map bt_bb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BT_BB_NMI_MAP + bt_bb_nmi interrupt configuration register + 0x818 + 0x20 + 0x00000010 + + + BT_BB_NMI_MAP + this register used to map bb_bt_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBT_IRQ_MAP + rwbt_irq interrupt configuration register + 0x81C + 0x20 + 0x00000010 + + + RWBT_IRQ_MAP + this register used to map rwbt_irq interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBLE_IRQ_MAP + rwble_irq interrupt configuration register + 0x820 + 0x20 + 0x00000010 + + + RWBLE_IRQ_MAP + this register used to map rwble_irq interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBT_NMI_MAP + rwbt_nmi interrupt configuration register + 0x824 + 0x20 + 0x00000010 + + + RWBT_NMI_MAP + this register used to map rwbt_nmi interupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RWBLE_NMI_MAP + rwble_nmi interrupt configuration register + 0x828 + 0x20 + 0x00000010 + + + RWBLE_NMI_MAP + this register used to map rwble_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_MST_INT_MAP + i2c_mst interrupt configuration register + 0x82C + 0x20 + 0x00000010 + + + I2C_MST_INT_MAP + this register used to map i2c_mst interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SLC0_INTR_MAP + slc0 interrupt configuration register + 0x830 + 0x20 + 0x00000010 + + + SLC0_INTR_MAP + this register used to map slc0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SLC1_INTR_MAP + slc1 interrupt configuration register + 0x834 + 0x20 + 0x00000010 + + + SLC1_INTR_MAP + this register used to map slc1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UHCI0_INTR_MAP + uhci0 interrupt configuration register + 0x838 + 0x20 + 0x00000010 + + + UHCI0_INTR_MAP + this register used to map uhci0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UHCI1_INTR_MAP + uhci1 interrupt configuration register + 0x83C + 0x20 + 0x00000010 + + + UHCI1_INTR_MAP + this register used to map uhci1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_MAP + gpio_interrupt_pro interrupt configuration register + 0x840 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_MAP + this register used to map gpio_interrupt_pro interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_PRO_NMI_MAP + gpio_interrupt_pro_nmi interrupt configuration register + 0x844 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_PRO_NMI_MAP + this register used to map gpio_interrupt_pro_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_MAP + gpio_interrupt_app interrupt configuration register + 0x848 + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_MAP + this register used to map gpio_interrupt_app interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + GPIO_INTERRUPT_APP_NMI_MAP + gpio_interrupt_app_nmi interrupt configuration register + 0x84C + 0x20 + 0x00000010 + + + GPIO_INTERRUPT_APP_NMI_MAP + this register used to map gpio_interrupt_app_nmi interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_1_MAP + spi_intr_1 interrupt configuration register + 0x850 + 0x20 + 0x00000010 + + + SPI_INTR_1_MAP + this register used to map spi_intr_1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_2_MAP + spi_intr_2 interrupt configuration register + 0x854 + 0x20 + 0x00000010 + + + SPI_INTR_2_MAP + this register used to map spi_intr_2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_3_MAP + spi_intr_3 interrupt configuration register + 0x858 + 0x20 + 0x00000010 + + + SPI_INTR_3_MAP + this register used to map spi_intr_3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_INTR_4_MAP + spi_intr_4 interrupt configuration register + 0x85C + 0x20 + 0x00000010 + + + SPI_INTR_4_MAP + this register used to map spi_intr_4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + LCD_CAM_INT_MAP + lcd_cam interrupt configuration register + 0x860 + 0x20 + 0x00000010 + + + LCD_CAM_INT_MAP + this register used to map lcd_cam interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2S0_INT_MAP + i2s0 interrupt configuration register + 0x864 + 0x20 + 0x00000010 + + + I2S0_INT_MAP + this register used to map i2s0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2S1_INT_MAP + i2s1 interrupt configuration register + 0x868 + 0x20 + 0x00000010 + + + I2S1_INT_MAP + this register used to map i2s1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART_INTR_MAP + uart interrupt configuration register + 0x86C + 0x20 + 0x00000010 + + + UART_INTR_MAP + this register used to map uart interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART1_INTR_MAP + uart1 interrupt configuration register + 0x870 + 0x20 + 0x00000010 + + + UART1_INTR_MAP + this register used to map uart1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + UART2_INTR_MAP + uart2 interrupt configuration register + 0x874 + 0x20 + 0x00000010 + + + UART2_INTR_MAP + this register used to map uart2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SDIO_HOST_INTERRUPT_MAP + sdio_host interrupt configuration register + 0x878 + 0x20 + 0x00000010 + + + SDIO_HOST_INTERRUPT_MAP + this register used to map sdio_host interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM0_INTR_MAP + pwm0 interrupt configuration register + 0x87C + 0x20 + 0x00000010 + + + PWM0_INTR_MAP + this register used to map pwm0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM1_INTR_MAP + pwm1 interrupt configuration register + 0x880 + 0x20 + 0x00000010 + + + PWM1_INTR_MAP + this register used to map pwm1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM2_INTR_MAP + pwm2 interrupt configuration register + 0x884 + 0x20 + 0x00000010 + + + PWM2_INTR_MAP + this register used to map pwm2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PWM3_INTR_MAP + pwm3 interrupt configuration register + 0x888 + 0x20 + 0x00000010 + + + PWM3_INTR_MAP + this register used to map pwm3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + LEDC_INT_MAP + ledc interrupt configuration register + 0x88C + 0x20 + 0x00000010 + + + LEDC_INT_MAP + this register used to map ledc interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + EFUSE_INT_MAP + efuse interrupt configuration register + 0x890 + 0x20 + 0x00000010 + + + EFUSE_INT_MAP + this register used to map efuse interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CAN_INT_MAP + can interrupt configuration register + 0x894 + 0x20 + 0x00000010 + + + CAN_INT_MAP + this register used to map can interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + USB_INTR_MAP + usb interrupt configuration register + 0x898 + 0x20 + 0x00000010 + + + USB_INTR_MAP + this register used to map usb interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RTC_CORE_INTR_MAP + rtc_core interrupt configuration register + 0x89C + 0x20 + 0x00000010 + + + RTC_CORE_INTR_MAP + this register used to map rtc_core interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RMT_INTR_MAP + rmt interrupt configuration register + 0x8A0 + 0x20 + 0x00000010 + + + RMT_INTR_MAP + this register used to map rmt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PCNT_INTR_MAP + pcnt interrupt configuration register + 0x8A4 + 0x20 + 0x00000010 + + + PCNT_INTR_MAP + this register used to map pcnt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT0_INTR_MAP + i2c_ext0 interrupt configuration register + 0x8A8 + 0x20 + 0x00000010 + + + I2C_EXT0_INTR_MAP + this register used to map i2c_ext0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + I2C_EXT1_INTR_MAP + i2c_ext1 interrupt configuration register + 0x8AC + 0x20 + 0x00000010 + + + I2C_EXT1_INTR_MAP + this register used to map i2c_ext1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI2_DMA_INT_MAP + spi2_dma interrupt configuration register + 0x8B0 + 0x20 + 0x00000010 + + + SPI2_DMA_INT_MAP + this register used to map spi2_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI3_DMA_INT_MAP + spi3_dma interrupt configuration register + 0x8B4 + 0x20 + 0x00000010 + + + SPI3_DMA_INT_MAP + this register used to map spi3_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI4_DMA_INT_MAP + spi4_dma interrupt configuration register + 0x8B8 + 0x20 + 0x00000010 + + + SPI4_DMA_INT_MAP + this register used to map spi4_dma interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + WDG_INT_MAP + wdg interrupt configuration register + 0x8BC + 0x20 + 0x00000010 + + + WDG_INT_MAP + this register used to map wdg interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT1_MAP + timer_int1 interrupt configuration register + 0x8C0 + 0x20 + 0x00000010 + + + TIMER_INT1_MAP + this register used to map timer_int1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TIMER_INT2_MAP + timer_int2 interrupt configuration register + 0x8C4 + 0x20 + 0x00000010 + + + TIMER_INT2_MAP + this register used to map timer_int2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_T0_INT_MAP + tg_t0 interrupt configuration register + 0x8C8 + 0x20 + 0x00000010 + + + TG_T0_INT_MAP + this register used to map tg_t0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_T1_INT_MAP + tg_t1 interrupt configuration register + 0x8CC + 0x20 + 0x00000010 + + + TG_T1_INT_MAP + this register used to map tg_t1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG_WDT_INT_MAP + tg_wdt interrupt configuration register + 0x8D0 + 0x20 + 0x00000010 + + + TG_WDT_INT_MAP + this register used to map rg_wdt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_T0_INT_MAP + tg1_t0 interrupt configuration register + 0x8D4 + 0x20 + 0x00000010 + + + TG1_T0_INT_MAP + this register used to map tg1_t0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_T1_INT_MAP + tg1_t1 interrupt configuration register + 0x8D8 + 0x20 + 0x00000010 + + + TG1_T1_INT_MAP + this register used to map tg1_t1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + TG1_WDT_INT_MAP + tg1_wdt interrupt configuration register + 0x8DC + 0x20 + 0x00000010 + + + TG1_WDT_INT_MAP + this register used to map tg1_wdt interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_IA_INT_MAP + cache_ia interrupt configuration register + 0x8E0 + 0x20 + 0x00000010 + + + CACHE_IA_INT_MAP + this register used to map cache_ia interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + systimer_target0 interrupt configuration register + 0x8E4 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET0_INT_MAP + this register used to map systimer_target0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + systimer_target1 interrupt configuration register + 0x8E8 + 0x20 + 0x00000010 + + + SYSTIMER_TARGET1_INT_MAP + this register used to map systimer_target1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + systimer_target2 interrupt configuration register + 0x8EC + 0x20 + 0x00000010 + + + SYSTIMER_TARGET2_INT_MAP + this register used to map systimer_target2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SPI_MEM_REJECT_INTR_MAP + spi_mem_reject interrupt configuration register + 0x8F0 + 0x20 + 0x00000010 + + + SPI_MEM_REJECT_INTR_MAP + this register used to map spi_mem_reject interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DCACHE_PRELOAD_INT_MAP + dcache_prelaod interrupt configuration register + 0x8F4 + 0x20 + 0x00000010 + + + DCACHE_PRELOAD_INT_MAP + this register used to map dcache_prelaod interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ICACHE_PRELOAD_INT_MAP + icache_preload interrupt configuration register + 0x8F8 + 0x20 + 0x00000010 + + + ICACHE_PRELOAD_INT_MAP + this register used to map icache_preload interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DCACHE_SYNC_INT_MAP + dcache_sync interrupt configuration register + 0x8FC + 0x20 + 0x00000010 + + + DCACHE_SYNC_INT_MAP + this register used to map dcache_sync interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ICACHE_SYNC_INT_MAP + icache_sync interrupt configuration register + 0x900 + 0x20 + 0x00000010 + + + ICACHE_SYNC_INT_MAP + this register used to map icache_sync interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + APB_ADC_INT_MAP + apb_adc interrupt configuration register + 0x904 + 0x20 + 0x00000010 + + + APB_ADC_INT_MAP + this register used to map apb_adc interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH0_INT_MAP + dma_in_ch0 interrupt configuration register + 0x908 + 0x20 + 0x00000010 + + + DMA_IN_CH0_INT_MAP + this register used to map dma_in_ch0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH1_INT_MAP + dma_in_ch1 interrupt configuration register + 0x90C + 0x20 + 0x00000010 + + + DMA_IN_CH1_INT_MAP + this register used to map dma_in_ch1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH2_INT_MAP + dma_in_ch2 interrupt configuration register + 0x910 + 0x20 + 0x00000010 + + + DMA_IN_CH2_INT_MAP + this register used to map dma_in_ch2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH3_INT_MAP + dma_in_ch3 interrupt configuration register + 0x914 + 0x20 + 0x00000010 + + + DMA_IN_CH3_INT_MAP + this register used to map dma_in_ch3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_IN_CH4_INT_MAP + dma_in_ch4 interrupt configuration register + 0x918 + 0x20 + 0x00000010 + + + DMA_IN_CH4_INT_MAP + this register used to map dma_in_ch4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH0_INT_MAP + dma_out_ch0 interrupt configuration register + 0x91C + 0x20 + 0x00000010 + + + DMA_OUT_CH0_INT_MAP + this register used to map dma_out_ch0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH1_INT_MAP + dma_out_ch1 interrupt configuration register + 0x920 + 0x20 + 0x00000010 + + + DMA_OUT_CH1_INT_MAP + this register used to map dma_out_ch1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH2_INT_MAP + dma_out_ch2 interrupt configuration register + 0x924 + 0x20 + 0x00000010 + + + DMA_OUT_CH2_INT_MAP + this register used to map dma_out_ch2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH3_INT_MAP + dma_out_ch3 interrupt configuration register + 0x928 + 0x20 + 0x00000010 + + + DMA_OUT_CH3_INT_MAP + this register used to map dma_out_ch3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_OUT_CH4_INT_MAP + dma_out_ch4 interrupt configuration register + 0x92C + 0x20 + 0x00000010 + + + DMA_OUT_CH4_INT_MAP + this register used to map dma_out_ch4 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + RSA_INT_MAP + rsa interrupt configuration register + 0x930 + 0x20 + 0x00000010 + + + RSA_INT_MAP + this register used to map rsa interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + AES_INT_MAP + aes interrupt configuration register + 0x934 + 0x20 + 0x00000010 + + + AES_INT_MAP + this register used to map aes interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + SHA_INT_MAP + sha interrupt configuration register + 0x938 + 0x20 + 0x00000010 + + + SHA_INT_MAP + this register used to map sha interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_0_MAP + cpu_intr_from_cpu_0 interrupt configuration register + 0x93C + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_0_MAP + this register used to map cpu_intr_from_cpu_0 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_1_MAP + cpu_intr_from_cpu_1 interrupt configuration register + 0x940 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_1_MAP + this register used to map cpu_intr_from_cpu_1 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_2_MAP + cpu_intr_from_cpu_2 interrupt configuration register + 0x944 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_2_MAP + this register used to map cpu_intr_from_cpu_2 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CPU_INTR_FROM_CPU_3_MAP + cpu_intr_from_cpu_3 interrupt configuration register + 0x948 + 0x20 + 0x00000010 + + + CPU_INTR_FROM_CPU_3_MAP + this register used to map cpu_intr_from_cpu_3 interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + ASSIST_DEBUG_INTR_MAP + assist_debug interrupt configuration register + 0x94C + 0x20 + 0x00000010 + + + ASSIST_DEBUG_INTR_MAP + this register used to map assist_debug interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + dma_pms_monitor_violatile interrupt configuration register + 0x950 + 0x20 + 0x00000010 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map dma_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_IRam0_pms_monitor_violatile interrupt configuration register + 0x954 + 0x20 + 0x00000010 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core0_DRam0_pms_monitor_violatile interrupt configuration register + 0x958 + 0x20 + 0x00000010 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core0_PIF_pms_monitor_violatile interrupt configuration register + 0x95C + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core0_PIF_pms_monitor_violatile_size interrupt configuration register + 0x960 + 0x20 + 0x00000010 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_IRam0_pms_monitor_violatile interrupt configuration register + 0x964 + 0x20 + 0x00000010 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + core1_DRam0_pms_monitor_violatile interrupt configuration register + 0x968 + 0x20 + 0x00000010 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + core1_PIF_pms_monitor_violatile interrupt configuration register + 0x96C + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + core1_PIF_pms_monitor_violatile_size interrupt configuration register + 0x970 + 0x20 + 0x00000010 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + BACKUP_PMS_VIOLATE_INTR_MAP + backup_pms_monitor_violatile interrupt configuration register + 0x974 + 0x20 + 0x00000010 + + + BACKUP_PMS_VIOLATE_INTR_MAP + this register used to map backup_pms_monitor_violatile interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE0_ACS_INT_MAP + cache_core0_acs interrupt configuration register + 0x978 + 0x20 + 0x00000010 + + + CACHE_CORE0_ACS_INT_MAP + this register used to map cache_core0_acs interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + CACHE_CORE1_ACS_INT_MAP + cache_core1_acs interrupt configuration register + 0x97C + 0x20 + 0x00000010 + + + CACHE_CORE1_ACS_INT_MAP + this register used to map cache_core1_acs interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + USB_DEVICE_INT_MAP + usb_device interrupt configuration register + 0x980 + 0x20 + 0x00000010 + + + USB_DEVICE_INT_MAP + this register used to map usb_device interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + PERI_BACKUP_INT_MAP + peri_backup interrupt configuration register + 0x984 + 0x20 + 0x00000010 + + + PERI_BACKUP_INT_MAP + this register used to map peri_backup interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + DMA_EXTMEM_REJECT_INT_MAP + dma_extmem_reject interrupt configuration register + 0x988 + 0x20 + 0x00000010 + + + DMA_EXTMEM_REJECT_INT_MAP + this register used to map dma_extmem_reject interrupt to one of core1's external interrupt + 0 + 5 + read-write + + + + + APP_INTR_STATUS_0 + interrupt status register + 0x98C + 0x20 + + + INTR_STATUS_0 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_1 + interrupt status register + 0x990 + 0x20 + + + INTR_STATUS_1 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_2 + interrupt status register + 0x994 + 0x20 + + + INTR_STATUS_2 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + APP_INTR_STATUS_3 + interrupt status register + 0x998 + 0x20 + + + INTR_STATUS_3 + this register store the status of the first 32 interrupt source + 0 + 32 + read-only + + + + + CLOCK_GATE + clock gate register + 0x99C + 0x20 + 0x00000001 + + + REG_CLK_EN + this register uesd to control clock-gating interupt martrix + 0 + 1 + read-write + + + + + DATE + version register + 0xFFC + 0x20 + 0x02012300 + + + INTERRUPT_DATE + version register + 0 + 28 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x60009000 + + 0x0 + 0xCC + registers + + + + PIN_CTRL + Clock Output Configuration Register + 0x0 + 0x20 + 0x000007FF + + + CLK_OUT1 + If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. + 0 + 4 + read-write + + + CLK_OUT2 + If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. + 4 + 4 + read-write + + + CLK_OUT3 + If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. + 8 + 4 + read-write + + + + + 49 + 0x4 + GPIO%s + IO MUX Configure Register for pad GPIO0 + 0x4 + 0x20 + 0x00000B00 + + + MCU_OE + Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled. + 0 + 1 + read-write + + + SLP_SEL + Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + 1 + 1 + read-write + + + MCU_WPD + Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. + 2 + 1 + read-write + + + MCU_WPU + Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. + 3 + 1 + read-write + + + MCU_IE + Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. + 4 + 1 + read-write + + + FUN_WPD + Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled. + 7 + 1 + read-write + + + FUN_WPU + Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. + 8 + 1 + read-write + + + FUN_IE + Input enable of the pad. 1: input enabled; 0: input disabled. + 9 + 1 + read-write + + + FUN_DRV + Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA. + 10 + 2 + read-write + + + MCU_SEL + Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc. + 12 + 3 + read-write + + + FILTER_EN + Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled. + 15 + 1 + read-write + + + + + DATE + IO MUX Version Control Register + 0xFC + 0x20 + 0x01907160 + + + REG_DATE + Version control register + 0 + 28 + read-write + + + + + + + LCD_CAM + Peripheral LCD_CAM + LCD_CAM + 0x60041000 + + 0x0 + 0x48 + registers + + + + LCD_CLOCK + LCD clock register + 0x0 + 0x20 + 0x00000843 + + + LCD_CLKCNT_N + f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + 0 + 6 + read-write + + + LCD_CLK_EQU_SYSCLK + 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + 6 + 1 + read-write + + + LCD_CK_IDLE_EDGE + 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + 7 + 1 + read-write + + + LCD_CK_OUT_EDGE + 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle. + 8 + 1 + read-write + + + LCD_CLKM_DIV_NUM + Integral LCD clock divider value + 9 + 8 + read-write + + + LCD_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + LCD_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + LCD_CLK_SEL + Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 31 + 1 + read-write + + + + + CAM_CTRL + Camera configuration register + 0x4 + 0x20 + 0x00000800 + + + CAM_STOP_EN + Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + 0 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + Filter threshold value for CAM_VSYNC signal. + 1 + 3 + read-write + + + CAM_UPDATE + 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + 4 + 1 + read-write + + + CAM_BYTE_ORDER + 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 5 + 1 + read-write + + + CAM_BIT_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 6 + 1 + read-write + + + CAM_LINE_INT_EN + 1: Enable to generate CAM_HS_INT. 0: Disable. + 7 + 1 + read-write + + + CAM_VS_EOF_EN + 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. + 8 + 1 + read-write + + + CAM_CLKM_DIV_NUM + Integral Camera clock divider value + 9 + 8 + read-write + + + CAM_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + CAM_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + CAM_CLK_SEL + Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + + + CAM_CTRL1 + Camera configuration register + 0x8 + 0x20 + + + CAM_REC_DATA_BYTELEN + Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + 0 + 16 + read-write + + + CAM_LINE_INT_NUM + The line number minus 1 to generate cam_hs_int. + 16 + 6 + read-write + + + CAM_CLK_INV + 1: Invert the input signal CAM_PCLK. 0: Not invert. + 22 + 1 + read-write + + + CAM_VSYNC_FILTER_EN + 1: Enable CAM_VSYNC filter function. 0: bypass. + 23 + 1 + read-write + + + CAM_2BYTE_EN + 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + 24 + 1 + read-write + + + CAM_DE_INV + CAM_DE invert enable signal, valid in high level. + 25 + 1 + read-write + + + CAM_HSYNC_INV + CAM_HSYNC invert enable signal, valid in high level. + 26 + 1 + read-write + + + CAM_VSYNC_INV + CAM_VSYNC invert enable signal, valid in high level. + 27 + 1 + read-write + + + CAM_VH_DE_MODE_EN + 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time. + 28 + 1 + read-write + + + CAM_START + Camera module start signal. + 29 + 1 + read-write + + + CAM_RESET + Camera module reset signal. + 30 + 1 + write-only + + + CAM_AFIFO_RESET + Camera AFIFO reset signal. + 31 + 1 + write-only + + + + + CAM_RGB_YUV + Camera configuration register + 0xC + 0x20 + 0x00C00000 + + + CAM_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 21 + 1 + read-write + + + CAM_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + CAM_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + CAM_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + CAM_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + CAM_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + CAM_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + CAM_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + CAM_CONV_BYPASS + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_RGB_YUV + LCD configuration register + 0x10 + 0x20 + 0x00C00000 + + + LCD_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 20 + 1 + read-write + + + LCD_CONV_TXTORX + 0: txtorx mode off. 1: txtorx mode on. + 21 + 1 + read-write + + + LCD_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + LCD_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + LCD_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + LCD_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + LCD_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + LCD_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + LCD_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + LCD_CONV_BYPASS + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_USER + LCD configuration register + 0x14 + 0x20 + 0x00000001 + + + LCD_DOUT_CYCLELEN + The output data cycles minus 1 of LCD module. + 0 + 13 + read-write + + + LCD_ALWAYS_OUT_EN + LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. + 13 + 1 + read-write + + + LCD_8BITS_ORDER + 1: invert every two data byte, valid in 1 byte mode. 0: Not change. + 19 + 1 + read-write + + + LCD_UPDATE + 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + 20 + 1 + read-write + + + LCD_BIT_ORDER + 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 21 + 1 + read-write + + + LCD_BYTE_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 22 + 1 + read-write + + + LCD_2BYTE_EN + 1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8. + 23 + 1 + read-write + + + LCD_DOUT + 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + 24 + 1 + read-write + + + LCD_DUMMY + 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + 25 + 1 + read-write + + + LCD_CMD + 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + 26 + 1 + read-write + + + LCD_START + LCD start sending data enable signal, valid in high level. + 27 + 1 + read-write + + + LCD_RESET + The value of command. + 28 + 1 + write-only + + + LCD_DUMMY_CYCLELEN + The dummy cycle length minus 1. + 29 + 2 + read-write + + + LCD_CMD_2_CYCLE_EN + The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + 31 + 1 + read-write + + + + + LCD_MISC + LCD configuration register + 0x18 + 0x20 + 0x000000D6 + + + LCD_AFIFO_THRESHOLD_NUM + The awfull threshold number of lcd_afifo. + 1 + 5 + read-write + + + LCD_VFK_CYCLELEN + The setup cycle length minus 1 in LCD non-RGB mode. + 6 + 6 + read-write + + + LCD_VBK_CYCLELEN + The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode. + 12 + 13 + read-write + + + LCD_NEXT_FRAME_EN + 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out. + 25 + 1 + read-write + + + LCD_BK_EN + 1: Enable blank region when LCD sends data out. 0: No blank region. + 26 + 1 + read-write + + + LCD_AFIFO_RESET + LCD AFIFO reset signal. + 27 + 1 + write-only + + + LCD_CD_DATA_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. + 28 + 1 + read-write + + + LCD_CD_DUMMY_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. + 29 + 1 + read-write + + + LCD_CD_CMD_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. + 30 + 1 + read-write + + + LCD_CD_IDLE_EDGE + The default value of LCD_CD. + 31 + 1 + read-write + + + + + LCD_CTRL + LCD configuration register + 0x1C + 0x20 + + + LCD_HB_FRONT + It is the horizontal blank front porch of a frame. + 0 + 11 + read-write + + + LCD_VA_HEIGHT + It is the vertical active height of a frame. + 11 + 10 + read-write + + + LCD_VT_HEIGHT + It is the vertical total height of a frame. + 21 + 10 + read-write + + + LCD_RGB_MODE_EN + 1: Enable reg mode input vsync, hsync, de. 0: Disable. + 31 + 1 + read-write + + + + + LCD_CTRL1 + LCD configuration register + 0x20 + 0x20 + + + LCD_VB_FRONT + It is the vertical blank front porch of a frame. + 0 + 8 + read-write + + + LCD_HA_WIDTH + It is the horizontal active width of a frame. + 8 + 12 + read-write + + + LCD_HT_WIDTH + It is the horizontal total width of a frame. + 20 + 12 + read-write + + + + + LCD_CTRL2 + LCD configuration register + 0x24 + 0x20 + 0x00010001 + + + LCD_VSYNC_WIDTH + It is the position of LCD_VSYNC active pulse in a line. + 0 + 7 + read-write + + + LCD_VSYNC_IDLE_POL + It is the idle value of LCD_VSYNC. + 7 + 1 + read-write + + + LCD_DE_IDLE_POL + It is the idle value of LCD_DE. + 8 + 1 + read-write + + + LCD_HS_BLANK_EN + 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. + 9 + 1 + read-write + + + LCD_HSYNC_WIDTH + It is the position of LCD_HSYNC active pulse in a line. + 16 + 7 + read-write + + + LCD_HSYNC_IDLE_POL + It is the idle value of LCD_HSYNC. + 23 + 1 + read-write + + + LCD_HSYNC_POSITION + It is the position of LCD_HSYNC active pulse in a line. + 24 + 8 + read-write + + + + + LCD_CMD_VAL + LCD configuration register + 0x28 + 0x20 + + + LCD_CMD_VALUE + The LCD write command value. + 0 + 32 + read-write + + + + + LCD_DLY_MODE + LCD configuration register + 0x30 + 0x20 + + + LCD_CD_MODE + The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + LCD_DE_MODE + The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + LCD_HSYNC_MODE + The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + LCD_VSYNC_MODE + The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + + + LCD_DATA_DOUT_MODE + LCD configuration register + 0x38 + 0x20 + + + DOUT0_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT1_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT2_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT3_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT4_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT5_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT6_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT7_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + DOUT8_MODE + The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + DOUT9_MODE + The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + DOUT10_MODE + The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + DOUT11_MODE + The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + DOUT12_MODE + The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 24 + 2 + read-write + + + DOUT13_MODE + The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 26 + 2 + read-write + + + DOUT14_MODE + The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 28 + 2 + read-write + + + DOUT15_MODE + The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 30 + 2 + read-write + + + + + LC_DMA_INT_ENA + LCD_camera DMA inturrupt enable register + 0x64 + 0x20 + + + LCD_VSYNC_INT_ENA + The enable bit for LCD frame end interrupt. + 0 + 1 + read-write + + + LCD_TRANS_DONE_INT_ENA + The enable bit for lcd transfer end interrupt. + 1 + 1 + read-write + + + CAM_VSYNC_INT_ENA + The enable bit for Camera frame end interrupt. + 2 + 1 + read-write + + + CAM_HS_INT_ENA + The enable bit for Camera line interrupt. + 3 + 1 + read-write + + + + + LC_DMA_INT_RAW + LCD_camera DMA raw inturrupt status register + 0x68 + 0x20 + + + LCD_VSYNC_INT_RAW + The raw bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_RAW + The raw bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_RAW + The raw bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_RAW + The raw bit for Camera line interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_ST + LCD_camera DMA masked inturrupt status register + 0x6C + 0x20 + + + LCD_VSYNC_INT_ST + The status bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_ST + The status bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_ST + The status bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_ST + The status bit for Camera transfer end interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_CLR + LCD_camera DMA inturrupt clear register + 0x70 + 0x20 + + + LCD_VSYNC_INT_CLR + The clear bit for LCD frame end interrupt. + 0 + 1 + write-only + + + LCD_TRANS_DONE_INT_CLR + The clear bit for lcd transfer end interrupt. + 1 + 1 + write-only + + + CAM_VSYNC_INT_CLR + The clear bit for Camera frame end interrupt. + 2 + 1 + write-only + + + CAM_HS_INT_CLR + The clear bit for Camera line interrupt. + 3 + 1 + write-only + + + + + LC_REG_DATE + Version register + 0xFC + 0x20 + 0x02003020 + + + LC_DATE + LCD_CAM version control register + 0 + 28 + read-write + + + + + + + LEDC + LED PWM (Pulse Width Modulation) Controller + LEDC + 0x60019000 + + 0x0 + 0xD8 + registers + + + LEDC + 35 + + + + 8 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL + This field is used to select one of timers for channel %s. + +0: select timer0 + +1: select timer1 + +2: select timer2 + +3: select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN + Set this bit to enable signal output on channel %s. + 2 + 1 + read-write + + + IDLE_LV + This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + 3 + 1 + read-write + + + PARA_UP + This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. + 4 + 1 + write-only + + + OVF_NUM + This register is used to configure the maximum times of overflow minus 1. + +The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN + This bit is used to enable the ovf_cnt of channel %s. + 15 + 1 + read-write + + + OVF_CNT_RESET + Set this bit to reset the ovf_cnt of channel %s. + 16 + 1 + write-only + + + OVF_CNT_RESET_ST + This is the status bit of LEDC_OVF_CNT_RESET_CH%s. + 17 + 1 + read-only + + + + + 8 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT + The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 14 + read-write + + + + + 8 + 0x14 + CH%s_DUTY + Initial duty cycle for channel %s + 0x8 + 0x20 + + + DUTY + This register is used to change the output duty by controlling the Lpoint. + +The output value turns to low when the selected timers has reached the Lpoint. + 0 + 19 + read-write + + + + + 8 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + 0x40000000 + + + DUTY_SCALE + This register is used to configure the changing step scale of duty on channel %s. + 0 + 10 + read-write + + + DUTY_CYCLE + The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. + 10 + 10 + read-write + + + DUTY_NUM + This register is used to control the number of times the duty cycle will be changed. + 20 + 10 + read-write + + + DUTY_INC + This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease. + 30 + 1 + read-write + + + DUTY_START + Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + 31 + 1 + read-write + + + + + 8 + 0x14 + CH%s_DUTY_R + Current duty cycle for channel %s + 0x10 + 0x20 + + + DUTY_R + This register stores the current duty of output signal on channel %s. + 0 + 19 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration + 0xA0 + 0x20 + 0x00800000 + + + DUTY_RES + This register is used to control the range of the counter in timer %s. + 0 + 4 + read-write + + + CLK_DIV + This register is used to configure the divisor for the divider in timer %s. + +The least significant eight bits represent the fractional part. + 4 + 18 + read-write + + + PAUSE + This bit is used to suspend the counter in timer %s. + 22 + 1 + read-write + + + RST + This bit is used to reset timer %s. The counter will show 0 after reset. + 23 + 1 + read-write + + + TICK_SEL + This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. + +1'h0: SLOW_CLK 1'h1: REF_TICK + 24 + 1 + read-write + + + PARA_UP + Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + 25 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value + 0xA4 + 0x20 + + + CNT + This register stores the current counter value of timer %s. + 0 + 14 + read-only + + + + + INT_RAW + Raw interrupt status + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-only + + + TIMER1_OVF_INT_RAW + Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-only + + + TIMER2_OVF_INT_RAW + Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-only + + + TIMER3_OVF_INT_RAW + Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_RAW + Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_RAW + Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_RAW + Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_RAW + Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_RAW + Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_RAW + Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_RAW + Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_RAW + Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_RAW + Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_RAW + Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_ST + This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_ST + This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_ENA + The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_ENA + The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + 9 + 1 + write-only + + + DUTY_CHNG_END_CH6_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + 10 + 1 + write-only + + + DUTY_CHNG_END_CH7_INT_CLR + Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + 11 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + 17 + 1 + write-only + + + OVF_CNT_CH6_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. + 18 + 1 + write-only + + + OVF_CNT_CH7_INT_CLR + Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. + 19 + 1 + write-only + + + + + CONF + Global ledc configuration register + 0xD0 + 0x20 + + + APB_CLK_SEL + This bit is used to select clock source for the 4 timers . + +2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + 0 + 2 + read-write + + + CLK_EN + This bit is used to control clock. + +1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 31 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x19040200 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x60017000 + + 0x0 + 0x68 + registers + + + PCNT + 41 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U + This is the enable bit for unit %s's thr_h_lim comparator. + 12 + 1 + read-write + + + THR_L_LIM_EN_U + This is the enable bit for unit %s's thr_l_lim comparator. + 13 + 1 + read-write + + + THR_THRES0_EN_U + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE_U + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE_U + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE_U + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U + This register is used to configure the thr_h_lim value for unit %s. + 0 + 16 + read-write + + + CNT_L_LIM_U + This register is used to configure the thr_l_lim value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x19072601 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PERI_BACKUP + Peripheral PERI_BACKUP + PERI_BACKUP + 0x6002A000 + + 0x0 + 0x30 + registers + + + PERI_BACKUP + 97 + + + + CONFIG + x + 0x0 + 0x20 + 0x00006480 + + + FLOW_ERR + x + 0 + 3 + read-only + + + ADDR_MAP_MODE + x + 3 + 1 + read-write + + + BURST_LIMIT + x + 4 + 5 + read-write + + + TOUT_THRES + x + 9 + 10 + read-write + + + SIZE + x + 19 + 10 + read-write + + + START + x + 29 + 1 + write-only + + + TO_MEM + x + 30 + 1 + read-write + + + ENA + x + 31 + 1 + read-write + + + + + APB_ADDR + x + 0x4 + 0x20 + + + APB_START_ADDR + x + 0 + 32 + read-write + + + + + MEM_ADDR + x + 0x8 + 0x20 + + + MEM_START_ADDR + x + 0 + 32 + read-write + + + + + REG_MAP0 + x + 0xC + 0x20 + + + MAP0 + x + 0 + 32 + read-write + + + + + REG_MAP1 + x + 0x10 + 0x20 + + + MAP1 + x + 0 + 32 + read-write + + + + + REG_MAP2 + x + 0x14 + 0x20 + + + MAP2 + x + 0 + 32 + read-write + + + + + REG_MAP3 + x + 0x18 + 0x20 + + + MAP3 + x + 0 + 32 + read-write + + + + + INT_RAW + x + 0x1C + 0x20 + + + DONE_INT_RAW + x + 0 + 1 + read-only + + + ERR_INT_RAW + x + 1 + 1 + read-only + + + + + INT_ST + x + 0x20 + 0x20 + + + DONE_INT_ST + x + 0 + 1 + read-only + + + ERR_INT_ST + x + 1 + 1 + read-only + + + + + INT_ENA + x + 0x24 + 0x20 + + + DONE_INT_ENA + x + 0 + 1 + read-write + + + ERR_INT_ENA + x + 1 + 1 + read-write + + + + + INT_CLR + x + 0x28 + 0x20 + + + DONE_INT_CLR + x + 0 + 1 + write-only + + + ERR_INT_CLR + x + 1 + 1 + write-only + + + + + DATE + x + 0xFC + 0x20 + 0x02012300 + + + DATE + x + 0 + 28 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + + + PWM0 + Peripheral PWM0 + PWM + 0x6001E000 + + 0x0 + 0x128 + registers + + + PWM0 + 31 + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + 0 + 8 + read-write + + + + + TIMER0_CFG0 + PWM timer0 period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER0_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER0_PERIOD + period shadow register of PWM timer0 + 8 + 16 + read-write + + + TIMER0_PERIOD_UPMETHOD + Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER0_CFG1 + PWM timer0 working mode and start/stop control configuration register. + 0x8 + 0x20 + + + TIMER0_START + PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER0_MOD + PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER0_SYNC + PWM timer0 sync function configuration register. + 0xC + 0x20 + + + TIMER0_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER0_SYNCO_SEL + PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER0_PHASE + phase for timer reload on sync event + 4 + 17 + read-write + + + + + TIMER0_STATUS + PWM timer0 status register. + 0x10 + 0x20 + + + TIMER0_VALUE + current PWM timer0 counter value + 0 + 16 + read-only + + + TIMER0_DIRECTION + current PWM timer0 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER1_CFG0 + PWM timer1 period and update method configuration register. + 0x14 + 0x20 + 0x0000FF00 + + + TIMER1_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER1_PERIOD + period shadow register of PWM timer1 + 8 + 16 + read-write + + + TIMER1_PERIOD_UPMETHOD + Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER1_CFG1 + PWM timer1 working mode and start/stop control configuration register. + 0x18 + 0x20 + + + TIMER1_START + PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER1_MOD + PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER1_SYNC + PWM timer1 sync function configuration register. + 0x1C + 0x20 + + + TIMER1_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER1_SYNCO_SEL + PWM timer1 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER1_PHASE + phase for timer reload on sync event + 4 + 17 + read-write + + + + + TIMER1_STATUS + PWM timer1 status register. + 0x20 + 0x20 + + + TIMER1_VALUE + current PWM timer1 counter value + 0 + 16 + read-only + + + TIMER1_DIRECTION + current PWM timer1 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER2_CFG0 + PWM timer2 period and update method configuration register. + 0x24 + 0x20 + 0x0000FF00 + + + TIMER2_PRESCALE + period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER2_PERIOD + period shadow register of PWM timer2 + 8 + 16 + read-write + + + TIMER2_PERIOD_UPMETHOD + Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + TIMER2_CFG1 + PWM timer2 working mode and start/stop control configuration register. + 0x28 + 0x20 + + + TIMER2_START + PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER2_MOD + PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode + 3 + 2 + read-write + + + + + TIMER2_SYNC + PWM timer2 sync function configuration register. + 0x2C + 0x20 + + + TIMER2_SYNCI_EN + When set, timer reloading with phase on sync input event is enabled. + 0 + 1 + read-write + + + SW + Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER2_SYNCO_SEL + PWM timer2 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync + 2 + 2 + read-write + + + TIMER2_PHASE + phase for timer reload on sync event + 4 + 17 + read-write + + + + + TIMER2_STATUS + PWM timer2 status register. + 0x30 + 0x20 + + + TIMER2_VALUE + current PWM timer2 counter value + 0 + 16 + read-only + + + TIMER2_DIRECTION + current PWM timer2 counter direction, 0: increment 1: decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection for three PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + invert SYNC0 from GPIO matrix + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + invert SYNC1 from GPIO matrix + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + invert SYNC2 from GPIO matrix + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + Select specific timer for PWM operators. + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2 + 4 + 2 + read-write + + + + + CMPR0_CFG + Transfer status and update method for time stamp registers A and B + 0x3C + 0x20 + + + CMPR0_A_UPMETHOD + Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR0_B_UPMETHOD + Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR0_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-only + + + CMPR0_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-only + + + + + CMPR0_VALUE0 + Shadow register for register A. + 0x40 + 0x20 + + + CMPR0_A + PWM generator 0 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR0_VALUE1 + Shadow register for register B. + 0x44 + 0x20 + + + CMPR0_B + PWM generator 0 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN0_CFG0 + Fault event T0 and T1 handling + 0x48 + 0x20 + + + GEN0_CFG_UPMETHOD + Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN0_T0_SEL + Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN0_T1_SEL + Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN0_FORCE + Permissives to force PWM0A and PWM0B outputs by software + 0x4C + 0x20 + 0x00000020 + + + GEN0_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN0_A_CNTUFORCE_MODE + Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN0_B_CNTUFORCE_MODE + Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN0_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN0_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN0_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN0_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN0_A + Actions triggered by events on PWM0A + 0x50 + 0x20 + + + UTEZ + Action on PWM0A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN0_B + Actions triggered by events on PWM0B + 0x54 + 0x20 + + + UTEZ + Action on PWM0B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM0B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM0B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM0B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM0B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM0B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM0B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM0B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM0B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM0B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM0B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB0_CFG + dead time type selection and configuration + 0x58 + 0x20 + 0x00018000 + + + DB0_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB0_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB0_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB0_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB0_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB0_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB0_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB0_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB0_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB0_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB0_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB0_CLK_SEL + Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB0_FED_CFG + Shadow register for falling edge delay (FED). + 0x5C + 0x20 + + + DB0_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB0_RED_CFG + Shadow register for rising edge delay (RED). + 0x60 + 0x20 + + + DB0_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER0_CFG + Carrier enable and configuratoin + 0x64 + 0x20 + + + CHOPPER0_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER0_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER0_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER0_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER0_OUT_INVERT + when set, invert the output of PWM0A and PWM0B for this submodule + 12 + 1 + read-write + + + CHOPPER0_IN_INVERT + when set, invert the input of PWM0A and PWM0B for this submodule + 13 + 1 + read-write + + + + + TZ0_CFG0 + Actions on PWM0A and PWM0B trip events + 0x68 + 0x20 + + + TZ0_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ0_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ0_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ0_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ0_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ0_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ0_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ0_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ0_A_CBC_D + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ0_A_CBC_U + Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ0_A_OST_D + One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ0_A_OST_U + One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ0_B_CBC_D + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ0_B_CBC_U + Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ0_B_OST_D + One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ0_B_OST_U + One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ0_CFG1 + Software triggers for fault handler actions + 0x6C + 0x20 + + + TZ0_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ0_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ0_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ0_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ0_STATUS + Status of fault events. + 0x70 + 0x20 + + + TZ0_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ0_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + CMPR1_CFG + Transfer status and update method for time stamp registers A and B + 0x74 + 0x20 + + + CMPR1_A_UPMETHOD + Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR1_B_UPMETHOD + Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR1_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-only + + + CMPR1_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-only + + + + + CMPR1_VALUE0 + Shadow register for register A. + 0x78 + 0x20 + + + CMPR1_A + PWM generator 1 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR1_VALUE1 + Shadow register for register B. + 0x7C + 0x20 + + + CMPR1_B + PWM generator 1 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN1_CFG0 + Fault event T0 and T1 handling + 0x80 + 0x20 + + + GEN1_CFG_UPMETHOD + Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN1_T0_SEL + Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN1_T1_SEL + Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN1_FORCE + Permissives to force PWM1A and PWM1B outputs by software + 0x84 + 0x20 + 0x00000020 + + + GEN1_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN1_A_CNTUFORCE_MODE + Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN1_B_CNTUFORCE_MODE + Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN1_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN1_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN1_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN1_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN1_A + Actions triggered by events on PWM1A + 0x88 + 0x20 + + + UTEZ + Action on PWM1A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN1_B + Actions triggered by events on PWM1B + 0x8C + 0x20 + + + UTEZ + Action on PWM1B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM1B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM1B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM1B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM1B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM1B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM1B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM1B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM1B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM1B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM1B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB1_CFG + dead time type selection and configuration + 0x90 + 0x20 + 0x00018000 + + + DB1_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB1_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB1_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB1_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB1_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB1_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB1_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB1_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB1_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB1_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB1_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB1_CLK_SEL + Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB1_FED_CFG + Shadow register for falling edge delay (FED). + 0x94 + 0x20 + + + DB1_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB1_RED_CFG + Shadow register for rising edge delay (RED). + 0x98 + 0x20 + + + DB1_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER1_CFG + Carrier enable and configuratoin + 0x9C + 0x20 + + + CHOPPER1_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER1_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER1_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER1_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER1_OUT_INVERT + when set, invert the output of PWM1A and PWM1B for this submodule + 12 + 1 + read-write + + + CHOPPER1_IN_INVERT + when set, invert the input of PWM1A and PWM1B for this submodule + 13 + 1 + read-write + + + + + TZ1_CFG0 + Actions on PWM1A and PWM1B trip events + 0xA0 + 0x20 + + + TZ1_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ1_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ1_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ1_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ1_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ1_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ1_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ1_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ1_A_CBC_D + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ1_A_CBC_U + Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ1_A_OST_D + One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ1_A_OST_U + One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ1_B_CBC_D + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ1_B_CBC_U + Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ1_B_OST_D + One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ1_B_OST_U + One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ1_CFG1 + Software triggers for fault handler actions + 0xA4 + 0x20 + + + TZ1_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ1_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ1_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ1_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ1_STATUS + Status of fault events. + 0xA8 + 0x20 + + + TZ1_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ1_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + CMPR2_CFG + Transfer status and update method for time stamp registers A and B + 0xAC + 0x20 + + + CMPR2_A_UPMETHOD + Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 0 + 4 + read-write + + + CMPR2_B_UPMETHOD + Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update. + 4 + 4 + read-write + + + CMPR2_A_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value + 8 + 1 + read-only + + + CMPR2_B_SHDW_FULL + Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value + 9 + 1 + read-only + + + + + CMPR2_VALUE0 + Shadow register for register A. + 0xB0 + 0x20 + + + CMPR2_A + PWM generator 2 time stamp A's shadow register + 0 + 16 + read-write + + + + + CMPR2_VALUE1 + Shadow register for register B. + 0xB4 + 0x20 + + + CMPR2_B + PWM generator 2 time stamp B's shadow register + 0 + 16 + read-write + + + + + GEN2_CFG0 + Fault event T0 and T1 handling + 0xB8 + 0x20 + + + GEN2_CFG_UPMETHOD + Update method for PWM generator 2's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: + 0 + 4 + read-write + + + GEN2_T0_SEL + Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 4 + 3 + read-write + + + GEN2_T1_SEL + Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none + 7 + 3 + read-write + + + + + GEN2_FORCE + Permissives to force PWM2A and PWM2B outputs by software + 0xBC + 0x20 + 0x00000020 + + + GEN2_CNTUFORCE_UPMETHOD + Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.) + 0 + 6 + read-write + + + GEN2_A_CNTUFORCE_MODE + Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled + 6 + 2 + read-write + + + GEN2_B_CNTUFORCE_MODE + Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled + 8 + 2 + read-write + + + GEN2_A_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN2_A_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled + 11 + 2 + read-write + + + GEN2_B_NCIFORCE + Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN2_B_NCIFORCE_MODE + non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled + 14 + 2 + read-write + + + + + GEN2_A + Actions triggered by events on PWM2A + 0xC0 + 0x20 + + + UTEZ + Action on PWM2A triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2A triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2A triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2A triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2A triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2A triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2A triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2A triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2A triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2A triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2A triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + GEN2_B + Actions triggered by events on PWM2B + 0xC4 + 0x20 + + + UTEZ + Action on PWM2B triggered by event TEZ when timer increasing + 0 + 2 + read-write + + + UTEP + Action on PWM2B triggered by event TEP when timer increasing + 2 + 2 + read-write + + + UTEA + Action on PWM2B triggered by event TEA when timer increasing + 4 + 2 + read-write + + + UTEB + Action on PWM2B triggered by event TEB when timer increasing + 6 + 2 + read-write + + + UT0 + Action on PWM2B triggered by event_t0 when timer increasing + 8 + 2 + read-write + + + UT1 + Action on PWM2B triggered by event_t1 when timer increasing + 10 + 2 + read-write + + + DTEZ + Action on PWM2B triggered by event TEZ when timer decreasing + 12 + 2 + read-write + + + DTEP + Action on PWM2B triggered by event TEP when timer decreasing + 14 + 2 + read-write + + + DTEA + Action on PWM2B triggered by event TEA when timer decreasing + 16 + 2 + read-write + + + DTEB + Action on PWM2B triggered by event TEB when timer decreasing + 18 + 2 + read-write + + + DT0 + Action on PWM2B triggered by event_t0 when timer decreasing + 20 + 2 + read-write + + + DT1 + Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle + 22 + 2 + read-write + + + + + DB2_CFG + dead time type selection and configuration + 0xC8 + 0x20 + 0x00018000 + + + DB2_FED_UPMETHOD + Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 0 + 4 + read-write + + + DB2_RED_UPMETHOD + Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze + 4 + 4 + read-write + + + DB2_DEB_MODE + S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB2_A_OUTSWAP + S6 in documentation + 9 + 1 + read-write + + + DB2_B_OUTSWAP + S7 in documentation + 10 + 1 + read-write + + + DB2_RED_INSEL + S4 in documentation + 11 + 1 + read-write + + + DB2_FED_INSEL + S5 in documentation + 12 + 1 + read-write + + + DB2_RED_OUTINVERT + S2 in documentation + 13 + 1 + read-write + + + DB2_FED_OUTINVERT + S3 in documentation + 14 + 1 + read-write + + + DB2_A_OUTBYPASS + S1 in documentation + 15 + 1 + read-write + + + DB2_B_OUTBYPASS + S0 in documentation + 16 + 1 + read-write + + + DB2_CLK_SEL + Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk + 17 + 1 + read-write + + + + + DB2_FED_CFG + Shadow register for falling edge delay (FED). + 0xCC + 0x20 + + + DB2_FED + Shadow register for FED + 0 + 16 + read-write + + + + + DB2_RED_CFG + Shadow register for rising edge delay (RED). + 0xD0 + 0x20 + + + DB2_RED + Shadow register for RED + 0 + 16 + read-write + + + + + CHOPPER2_CFG + Carrier enable and configuratoin + 0xD4 + 0x20 + + + CHOPPER2_EN + When set, carrier0 function is enabled. When cleared, carrier0 is bypassed + 0 + 1 + read-write + + + CHOPPER2_PRESCALE + PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER2_DUTY + carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER2_OSHTWTH + width of the fist pulse in number of periods of the carrier + 8 + 4 + read-write + + + CHOPPER2_OUT_INVERT + when set, invert the output of PWM2A and PWM2B for this submodule + 12 + 1 + read-write + + + CHOPPER2_IN_INVERT + when set, invert the input of PWM2A and PWM2B for this submodule + 13 + 1 + read-write + + + + + TZ2_CFG0 + Actions on PWM2A and PWM2B trip events + 0xD8 + 0x20 + + + TZ2_SW_CBC + Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable + 0 + 1 + read-write + + + TZ2_F2_CBC + event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 1 + 1 + read-write + + + TZ2_F1_CBC + event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 2 + 1 + read-write + + + TZ2_F0_CBC + event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable + 3 + 1 + read-write + + + TZ2_SW_OST + Enable register for software force one-shot mode action. 0: disable, 1: enable + 4 + 1 + read-write + + + TZ2_F2_OST + event_f2 will trigger one-shot mode action. 0: disable, 1: enable + 5 + 1 + read-write + + + TZ2_F1_OST + event_f1 will trigger one-shot mode action. 0: disable, 1: enable + 6 + 1 + read-write + + + TZ2_F0_OST + event_f0 will trigger one-shot mode action. 0: disable, 1: enable + 7 + 1 + read-write + + + TZ2_A_CBC_D + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 8 + 2 + read-write + + + TZ2_A_CBC_U + Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 10 + 2 + read-write + + + TZ2_A_OST_D + One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 12 + 2 + read-write + + + TZ2_A_OST_U + One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 14 + 2 + read-write + + + TZ2_B_CBC_D + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 16 + 2 + read-write + + + TZ2_B_CBC_U + Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 18 + 2 + read-write + + + TZ2_B_OST_D + One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 20 + 2 + read-write + + + TZ2_B_OST_U + One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle + 22 + 2 + read-write + + + + + TZ2_CFG1 + Software triggers for fault handler actions + 0xDC + 0x20 + + + TZ2_CLR_OST + a rising edge will clear on going one-shot mode action + 0 + 1 + read-write + + + TZ2_CBCPULSE + cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP + 1 + 2 + read-write + + + TZ2_FORCE_CBC + a toggle trigger a cycle-by-cycle mode action + 3 + 1 + read-write + + + TZ2_FORCE_OST + a toggle (software negate its value) triggers a one-shot mode action + 4 + 1 + read-write + + + + + TZ2_STATUS + Status of fault events. + 0xE0 + 0x20 + + + TZ2_CBC_ON + Set and reset by hardware. If set, a cycle-by-cycle mode action is on going + 0 + 1 + read-only + + + TZ2_OST_ON + Set and reset by hardware. If set, an one-shot mode action is on going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status + 0xE4 + 0x20 + + + F0_EN + When set, event_f0 generation is enabled + 0 + 1 + read-write + + + F1_EN + When set, event_f1 generation is enabled + 1 + 1 + read-write + + + F2_EN + When set, event_f2 generation is enabled + 2 + 1 + read-write + + + F0_POLE + Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 3 + 1 + read-write + + + F1_POLE + Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 4 + 1 + read-write + + + F2_POLE + Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high + 5 + 1 + read-write + + + EVENT_F0 + Set and reset by hardware. If set, event_f0 is on going + 6 + 1 + read-only + + + EVENT_F1 + Set and reset by hardware. If set, event_f1 is on going + 7 + 1 + read-only + + + EVENT_F2 + Set and reset by hardware. If set, event_f2 is on going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Configure capture timer + 0xE8 + 0x20 + + + CAP_TIMER_EN + When set, capture timer incrementing under APB_clk is enabled. + 0 + 1 + read-write + + + CAP_SYNCI_EN + When set, capture timer sync is enabled. + 1 + 1 + read-write + + + CAP_SYNCI_SEL + capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix + 2 + 3 + read-write + + + CAP_SYNC_SW + Write 1 will force a capture timer sync, capture timer is loaded with value in phase register. + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Phase for capture timer sync + 0xEC + 0x20 + + + CAP_PHASE + Phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + CAP_CH0_CFG + Capture channel 0 configuration and enable + 0xF0 + 0x20 + + + CAP0_EN + When set, capture on channel 0 is enabled + 0 + 1 + read-write + + + CAP0_MODE + Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP0_PRESCALE + Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + 3 + 8 + read-write + + + CAP0_IN_INVERT + when set, CAP0 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP0_SW + Write 1 will trigger a software forced capture on channel 0 + 12 + 1 + write-only + + + + + CAP_CH1_CFG + Capture channel 1 configuration and enable + 0xF4 + 0x20 + + + CAP1_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP1_MODE + Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP1_PRESCALE + Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + 3 + 8 + read-write + + + CAP1_IN_INVERT + when set, CAP1 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP1_SW + Write 1 will trigger a software forced capture on channel 1 + 12 + 1 + write-only + + + + + CAP_CH2_CFG + Capture channel 2 configuration and enable + 0xF8 + 0x20 + + + CAP2_EN + When set, capture on channel 2 is enabled + 0 + 1 + read-write + + + CAP2_MODE + Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge. + 1 + 2 + read-write + + + CAP2_PRESCALE + Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + 3 + 8 + read-write + + + CAP2_IN_INVERT + when set, CAP2 form GPIO matrix is inverted before prescale + 11 + 1 + read-write + + + CAP2_SW + Write 1 will trigger a software forced capture on channel 2 + 12 + 1 + write-only + + + + + CAP_CH0 + Value of last capture on channel 0 + 0xFC + 0x20 + + + CAP0_VALUE + Value of last capture on channel 0 + 0 + 32 + read-only + + + + + CAP_CH1 + Value of last capture on channel 1 + 0x100 + 0x20 + + + CAP1_VALUE + Value of last capture on channel 1 + 0 + 32 + read-only + + + + + CAP_CH2 + Value of last capture on channel 2 + 0x104 + 0x20 + + + CAP2_VALUE + Value of last capture on channel 2 + 0 + 32 + read-only + + + + + CAP_STATUS + Edge of last capture trigger + 0x108 + 0x20 + + + CAP0_EDGE + Edge of last capture trigger on channel 0, 0: posedge, 1: negedge + 0 + 1 + read-only + + + CAP1_EDGE + Edge of last capture trigger on channel 1, 0: posedge, 1: negedge + 1 + 1 + read-only + + + CAP2_EDGE + Edge of last capture trigger on channel 2, 0: posedge, 1: negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Enable update. + 0x10C + 0x20 + 0x00000055 + + + GLOBAL_UP_EN + The global enable of update of all active registers in MCPWM module + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + 1 + 1 + read-write + + + OP0_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled + 2 + 1 + read-write + + + OP0_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + 3 + 1 + read-write + + + OP1_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled + 4 + 1 + read-write + + + OP1_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + 5 + 1 + read-write + + + OP2_UP_EN + When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled + 6 + 1 + read-write + + + OP2_FORCE_UP + a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable bits + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + The enable bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + The enable bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + The enable bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + The enable bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + The enable bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + The enable bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + The enable bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-write + + + CAP1_INT_ENA + The enable bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-write + + + CAP2_INT_ENA + The enable bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_RAW + The raw status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_RAW + The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_RAW + The raw status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_RAW + The raw status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_RAW + The raw status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_RAW + The raw status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_RAW + The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_RAW + The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_RAW + The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_RAW + The raw status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + The masked status bit for the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + The masked status bit for the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + The masked status bit for the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + The masked status bit for the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f0 ends. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f1 ends. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + The masked status bit for the interrupt triggered when event_f2 ends. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + The masked status bit for the interrupt triggered by capture on channel 0. + 27 + 1 + read-only + + + CAP1_INT_ST + The masked status bit for the interrupt triggered by capture on channel 1. + 28 + 1 + read-only + + + CAP2_INT_ST + The masked status bit for the interrupt triggered by capture on channel 2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Set this bit to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f0 ends. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f1 ends. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Set this bit to clear the interrupt triggered when event_f2 ends. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Set this bit to clear the interrupt triggered by capture on channel 2. + 29 + 1 + write-only + + + + + CLK + MCPWM APB configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x124 + 0x20 + 0x01509110 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + PWM1 + 0x6002C000 + + PWM1 + 32 + + + + RMT + Remote control + RMT + 0x60016000 + + 0x0 + 0xD0 + registers + + + RMT + 40 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + RX_CH%sDATA + The read and write data register for CHANNEL$n by apb fifo access. + 0x10 + 0x20 + + + CHDATA + Read and write data for channel 0 via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + CH%s_TX_CONF0 + Channel %s configure register 0 + 0x20 + 0x20 + 0x00710200 + + + TX_START + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 4 + read-write + + + CARRIER_EFF_EN + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST + Reserved + 23 + 1 + write-only + + + CONF_UPDATE + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 4 + 0x8 + CH%s_RX_CONF0 + Channel %s configure register 0 + 0x30 + 0x20 + 0x317FFF02 + + + DIV_CNT + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 24 + 4 + read-write + + + CARRIER_EN + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV + This bit is used to configure the position of carrier wave for CHANNEL%s. + +1'h0: add carrier wave on low level. + +1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 4 + 0x8 + CH%s_RX_CONF1 + Channel %s configure register 1 + 0x34 + 0x20 + 0x000001E8 + + + RX_EN + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER + This register marks the ownership of CHANNEL%s's ram block. + +1'h1: Receiver is using the ram. + +1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST + Reserved + 14 + 1 + write-only + + + CONF_UPDATE + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 4 + 0x4 + CH%s_TX_STATUS + Channel %s status register + 0x50 + 0x20 + + + MEM_RADDR_EX + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_WADDR + This register records the memory address offset when writes RAM over APB bus. + 11 + 10 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_EMPTY + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 25 + 1 + read-only + + + APB_MEM_WR_ERR + This status bit will be set if the offset address out of memory size when writes via APB bus. + 26 + 1 + read-only + + + + + 4 + 0x4 + CH%s_RX_STATUS + Channel %s status register + 0x60 + 0x20 + 0x000600C0 + + + MEM_WADDR_EX + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_RADDR + This register records the memory address offset when reads RAM over APB bus. + 11 + 10 + read-only + + + STATE + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x70 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + 0 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when error occurs. + 4 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when reception done. + 16 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 20 + 1 + read-only + + + CH4_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. + 24 + 1 + read-only + + + CH5_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. + 25 + 1 + read-only + + + CH6_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. + 26 + 1 + read-only + + + CH7_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. + 27 + 1 + read-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + 28 + 1 + read-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + 29 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x74 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_ST + The masked interrupt status bit for CH%s_TX_END_INT. + 0 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_ST + The masked interrupt status bit for CH%s_ERR_INT. + 4 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_ST + The masked interrupt status bit for CH%s_TX_LOOP_INT. + 12 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_ST + The masked interrupt status bit for CH4_RX_END_INT. + 16 + 1 + read-only + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 20 + 1 + read-only + + + CH4_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-only + + + CH5_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-only + + + CH6_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-only + + + CH7_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x78 + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_ENA + The interrupt enable bit for CH%s_TX_END_INT. + 0 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_ENA + The interrupt enable bit for CH%s_ERR_INT. + 4 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH%s_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_ENA + The interrupt enable bit for CH%s_TX_LOOP_INT. + 12 + 1 + read-write + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_ENA + The interrupt enable bit for CH4_RX_END_INT. + 16 + 1 + read-write + + + 4 + 0x1 + 4-7 + CH%s_RX_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 20 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x7C + 0x20 + + + 4 + 0x1 + 0-3 + CH%s_TX_END_INT_CLR + Set this bit to clear theCH%s_TX_END_INT interrupt. + 0 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_ERR_INT_CLR + Set this bit to clear theCH%s_ERR_INT interrupt. + 4 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + 4 + 0x1 + 0-3 + CH%s_TX_LOOP_INT_CLR + Set this bit to clear theCH%s_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + 4 + 0x1 + 4-7 + CH%s_RX_END_INT_CLR + Set this bit to clear theCH4_RX_END_INT interrupt. + 16 + 1 + write-only + + + 4 + 0x1 + RX_CH4,RX_CH5,RX_CH6,RX_CH7 + CH%s_RX_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 20 + 1 + write-only + + + CH4_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + 24 + 1 + write-only + + + CH5_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + 25 + 1 + write-only + + + CH6_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + 26 + 1 + write-only + + + CH7_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + 27 + 1 + write-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + 28 + 1 + write-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + 29 + 1 + write-only + + + + + 4 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x80 + 0x20 + 0x00400040 + + + CARRIER_LOW + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x90 + 0x20 + + + CARRIER_LOW_THRES + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0xA0 + 0x20 + 0x00000080 + + + TX_LIM + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 4 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0xB0 + 0x20 + 0x00000080 + + + RX_LIM + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0xC0 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL + 24 + 2 + read-write + + + SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0xC4 + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + CH2 + Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + 2 + 1 + read-write + + + CH3 + Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + 3 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 4 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0xC8 + 0x20 + + + 8 + 0x1 + TX_REF_CNT_RST_CH0,TX_REF_CNT_RST_CH1,TX_REF_CNT_RST_CH2,TX_REF_CNT_RST_CH3,RX_REF_CNT_RST_CH4,RX_REF_CNT_RST_CH5,RX_REF_CNT_RST_CH6,RX_REF_CNT_RST_CH7 + CH%s + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02101181 + + + DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RNG + Hardware random number generator + RNG + 0x60034F6C + + 0x0 + 0x4 + registers + + + + DATA + Random number data + 0x110 + 0x20 + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x6003C000 + + 0x0 + 0x834 + registers + + + RSA + 76 + + + + 512 + 0x1 + M_MEM[%s] + Memory M + 0x0 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + Memory Z + 0x200 + 0x8 + + + 512 + 0x1 + Y_MEM[%s] + Memory Y + 0x400 + 0x8 + + + 512 + 0x1 + X_MEM[%s] + Memory X + 0x600 + 0x8 + + + M_PRIME + RSA M' register + 0x800 + 0x20 + + + M_PRIME + Stores M' + 0 + 32 + read-write + + + + + MODE + RSA length mode register + 0x804 + 0x20 + + + MODE + Stores the RSA length mode + 0 + 7 + read-write + + + + + CLEAN + RSA clean register + 0x808 + 0x20 + + + CLEAN + The content of this bit is 1 when memories complete initialization. + 0 + 1 + read-only + + + + + MODEXP_START + Modular exponentiation trigger register. + 0x80C + 0x20 + + + MODEXP_START + Set this bit to 1 to start the modular exponentiation. + 0 + 1 + write-only + + + + + MODMULT_START + Modular multiplication trigger register. + 0x810 + 0x20 + + + MODMULT_START + Set this bit to 1 to start the modular multiplication + 0 + 1 + write-only + + + + + MULT_START + Normal multiplication trigger register. + 0x814 + 0x20 + + + MULT_START + Set this bit to 1 to start the multiplicaiton. + 0 + 1 + write-only + + + + + IDLE + RSA idle register + 0x818 + 0x20 + + + IDLE + The content of this bit is 1 when the RSA accelerator is idle. + 0 + 1 + read-only + + + + + CLEAR_INTERRUPT + RSA interrupt clear register + 0x81C + 0x20 + + + CLEAR_INTERRUPT + set this bit to 1 to clear the RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + CONSTANT_TIME option control register + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Controls the CONSTANT_TIME option. 0: acceleration. 1: no acceleration(by default). + 0 + 1 + read-write + + + + + SEARCH_ENABLE + SEARCH option enable register + 0x824 + 0x20 + + + SEARCH_ENABLE + Controls the SEARCH option. 0: no acceleration(by default). 1: acceleration. + 0 + 1 + read-write + + + + + SEARCH_POS + RSA search position configure register + 0x828 + 0x20 + + + SEARCH_POS + This field is used to configure the starting search position when the acceleration option of SEARCH is used. + 0 + 12 + read-write + + + + + INTERRUPT_ENA + RSA interrupt enable register + 0x82C + 0x20 + + + INTERRUPT_ENA + Set this bit to 1 to enable the RSA interrupt. This option is enabled by default. + 0 + 1 + read-write + + + + + DATE + RSA version control register + 0x830 + 0x20 + 0x20191231 + + + DATE + rsa version information + 0 + 30 + read-write + + + + + + + RTC_CNTL + Real Time Controller + RTC_CNTL + 0x60008000 + + 0x0 + 0x15C + registers + + + RTC_CORE + 39 + + + + OPTIONS0 + RTC common configure register + 0x0 + 0x20 + 0x1C00A000 + + + SW_STALL_APPCPU_C0 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 0 + 2 + read-write + + + SW_STALL_PROCPU_C0 + {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU + 2 + 2 + read-write + + + SW_APPCPU_RST + APP CPU SW reset + 4 + 1 + write-only + + + SW_PROCPU_RST + PRO CPU SW reset + 5 + 1 + write-only + + + BB_I2C_FORCE_PD + BB_I2C force power down + 6 + 1 + read-write + + + BB_I2C_FORCE_PU + BB_I2C force power up + 7 + 1 + read-write + + + BBPLL_I2C_FORCE_PD + BB_PLL _I2C force power down + 8 + 1 + read-write + + + BBPLL_I2C_FORCE_PU + BB_PLL_I2C force power up + 9 + 1 + read-write + + + BBPLL_FORCE_PD + BB_PLL force power down + 10 + 1 + read-write + + + BBPLL_FORCE_PU + BB_PLL force power up + 11 + 1 + read-write + + + XTL_FORCE_PD + crystall force power down + 12 + 1 + read-write + + + XTL_FORCE_PU + crystall force power up + 13 + 1 + read-write + + + XTL_EN_WAIT + wait bias_sleep and current source wakeup + 14 + 4 + read-write + + + XTL_FORCE_ISO + No public + 23 + 1 + read-write + + + PLL_FORCE_ISO + No public + 24 + 1 + read-write + + + ANALOG_FORCE_ISO + No public + 25 + 1 + read-write + + + XTL_FORCE_NOISO + No public + 26 + 1 + read-write + + + PLL_FORCE_NOISO + No public + 27 + 1 + read-write + + + ANALOG_FORCE_NOISO + No public + 28 + 1 + read-write + + + DG_WRAP_FORCE_RST + digital wrap force reset in deep sleep + 29 + 1 + read-write + + + DG_WRAP_FORCE_NORST + digital core force no reset in deep sleep + 30 + 1 + read-write + + + SW_SYS_RST + SW system reset + 31 + 1 + write-only + + + + + SLP_TIMER0 + configure min sleep time + 0x4 + 0x20 + + + SLP_VAL_LO + RTC sleep timer low 32 bits + 0 + 32 + read-write + + + + + SLP_TIMER1 + configure sleep time hi + 0x8 + 0x20 + + + SLP_VAL_HI + RTC sleep timer high 16 bits + 0 + 16 + read-write + + + MAIN_TIMER_ALARM_EN + timer alarm enable bit + 16 + 1 + write-only + + + + + TIME_UPDATE + update rtc main timer + 0xC + 0x20 + + + TIMER_SYS_STALL + Enable to record system stall time + 27 + 1 + read-write + + + TIMER_XTL_OFF + Enable to record 40M XTAL OFF time + 28 + 1 + read-write + + + TIMER_SYS_RST + enable to record system reset time + 29 + 1 + read-write + + + TIME_UPDATE + Set 1: to update register with RTC timer + 31 + 1 + write-only + + + + + TIME_LOW0 + read rtc_main timer low bits + 0x10 + 0x20 + + + TIMER_VALUE0_LOW + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME_HIGH0 + read rtc_main timer high bits + 0x14 + 0x20 + + + TIMER_VALUE0_HIGH + RTC timer high 16 bits + 0 + 16 + read-only + + + + + STATE0 + configure chip sleep + 0x18 + 0x20 + + + SW_CPU_INT + rtc software interrupt to main cpu + 0 + 1 + write-only + + + SLP_REJECT_CAUSE_CLR + clear rtc sleep reject cause + 1 + 1 + write-only + + + APB2RTC_BRIDGE_SEL + 1: APB to RTC using bridge, 0: APB to RTC using sync + 22 + 1 + read-write + + + SDIO_ACTIVE_IND + SDIO active indication + 28 + 1 + read-only + + + SLP_WAKEUP + leep wakeup bit + 29 + 1 + read-write + + + SLP_REJECT + leep reject bit + 30 + 1 + read-write + + + SLEEP_EN + sleep enable bit + 31 + 1 + read-write + + + + + TIMER1 + rtc state wait time + 0x1C + 0x20 + 0x28140403 + + + CPU_STALL_EN + CPU stall enable bit + 0 + 1 + read-write + + + CPU_STALL_WAIT + CPU stall wait cycles in fast_clk_rtc + 1 + 5 + read-write + + + CK8M_WAIT + CK8M wait cycles in slow_clk_rtc + 6 + 8 + read-write + + + XTL_BUF_WAIT + XTAL wait cycles in slow_clk_rtc + 14 + 10 + read-write + + + PLL_BUF_WAIT + PLL wait cycles in slow_clk_rtc + 24 + 8 + read-write + + + + + TIMER2 + rtc monitor state delay time + 0x20 + 0x20 + 0x01080000 + + + ULPCP_TOUCH_START_WAIT + wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work + 15 + 9 + read-write + + + MIN_TIME_CK8M_OFF + minimal cycles in slow_clk_rtc for CK8M in power down state + 24 + 8 + read-write + + + + + TIMER3 + No public + 0x24 + 0x20 + 0x14160A08 + + + WIFI_WAIT_TIMER + No public + 0 + 9 + read-write + + + WIFI_POWERUP_TIMER + No public + 9 + 7 + read-write + + + BT_WAIT_TIMER + No public + 16 + 9 + read-write + + + BT_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + TIMER4 + No public + 0x28 + 0x20 + 0x10200A08 + + + WAIT_TIMER + No public + 0 + 9 + read-write + + + POWERUP_TIMER + No public + 9 + 7 + read-write + + + DG_WRAP_WAIT_TIMER + No public + 16 + 9 + read-write + + + DG_WRAP_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + TIMER5 + configure min sleep time + 0x2C + 0x20 + 0x00008000 + + + MIN_SLP_VAL + minimal sleep cycles in slow_clk_rtc + 8 + 8 + read-write + + + + + TIMER6 + No public + 0x30 + 0x20 + 0x10200A08 + + + CPU_TOP_WAIT_TIMER + No public + 0 + 9 + read-write + + + CPU_TOP_POWERUP_TIMER + No public + 9 + 7 + read-write + + + DG_PERI_WAIT_TIMER + No public + 16 + 9 + read-write + + + DG_PERI_POWERUP_TIMER + No public + 25 + 7 + read-write + + + + + ANA_CONF + analog configure register + 0x34 + 0x20 + 0x00440000 + + + I2C_RESET_POR_FORCE_PD + force down I2C_RESET_POR + 18 + 1 + read-write + + + I2C_RESET_POR_FORCE_PU + force on I2C_RESET_POR + 19 + 1 + read-write + + + GLITCH_RST_EN + enable clk glitch + 20 + 1 + read-write + + + SAR_I2C_PU + PLLA force power up + 22 + 1 + read-write + + + ANALOG_TOP_ISO_SLEEP + PLLA force power down + 23 + 1 + read-write + + + ANALOG_TOP_ISO_MONITOR + PLLA force power up + 24 + 1 + read-write + + + BBPLL_CAL_SLP_START + start BBPLL calibration during sleep + 25 + 1 + read-write + + + PVTMON_PU + 1: PVTMON power up, otherwise power down + 26 + 1 + read-write + + + TXRF_I2C_PU + 1: TXRF_I2C power up, otherwise power down + 27 + 1 + read-write + + + RFRX_PBUS_PU + 1: RFRX_PBUS power up, otherwise power down + 28 + 1 + read-write + + + CKGEN_I2C_PU + 1: CKGEN_I2C power up, otherwise power down + 30 + 1 + read-write + + + PLL_I2C_PU + power on pll i2c + 31 + 1 + read-write + + + + + RESET_STATE + get reset state + 0x38 + 0x20 + 0x00003000 + + + RESET_CAUSE_PROCPU + reset cause of PRO CPU + 0 + 6 + read-only + + + RESET_CAUSE_APPCPU + reset cause of APP CPU + 6 + 6 + read-only + + + APPCPU_STAT_VECTOR_SEL + APP CPU state vector sel + 12 + 1 + read-write + + + PROCPU_STAT_VECTOR_SEL + PRO CPU state vector sel + 13 + 1 + read-write + + + RESET_FLAG_PROCPU + PRO CPU reset_flag + 14 + 1 + read-only + + + RESET_FLAG_APPCPU + APP CPU reset flag + 15 + 1 + read-only + + + RESET_FLAG_PROCPU_CLR + clear PRO CPU reset_flag + 16 + 1 + write-only + + + RESET_FLAG_APPCPU_CLR + clear APP CPU reset flag + 17 + 1 + write-only + + + APPCPU_OCD_HALT_ON_RESET + APPCPU OcdHaltOnReset + 18 + 1 + read-write + + + PROCPU_OCD_HALT_ON_RESET + PROCPU OcdHaltOnReset + 19 + 1 + read-write + + + RESET_FLAG_JTAG_PROCPU + jtag reset flag + 20 + 1 + read-only + + + RESET_FLAG_JTAG_APPCPU + jtag reset flag + 21 + 1 + read-only + + + RESET_FLAG_JTAG_PROCPU_CLR + clear jtag reset flag + 22 + 1 + write-only + + + RESET_FLAG_JTAG_APPCPU_CLR + clear jtag reset flag + 23 + 1 + write-only + + + APP_DRESET_MASK + bypass cpu1 dreset + 24 + 1 + read-write + + + PRO_DRESET_MASK + bypass cpu0 dreset + 25 + 1 + read-write + + + + + WAKEUP_STATE + configure wakeup state + 0x3C + 0x20 + 0x00060000 + + + WAKEUP_ENA + wakeup enable bitmap + 15 + 17 + read-write + + + + + INT_ENA_RTC + configure rtc interrupt register + 0x40 + 0x20 + + + SLP_WAKEUP_INT_ENA + enable sleep wakeup interrupt + 0 + 1 + read-write + + + SLP_REJECT_INT_ENA + enable sleep reject interrupt + 1 + 1 + read-write + + + SDIO_IDLE_INT_ENA + enable SDIO idle interrupt + 2 + 1 + read-write + + + WDT_INT_ENA + enable RTC WDT interrupt + 3 + 1 + read-write + + + TOUCH_SCAN_DONE_INT_ENA + enable touch scan done interrupt + 4 + 1 + read-write + + + ULP_CP_INT_ENA + enable ULP-coprocessor interrupt + 5 + 1 + read-write + + + TOUCH_DONE_INT_ENA + enable touch done interrupt + 6 + 1 + read-write + + + TOUCH_ACTIVE_INT_ENA + enable touch active interrupt + 7 + 1 + read-write + + + TOUCH_INACTIVE_INT_ENA + enable touch inactive interrupt + 8 + 1 + read-write + + + BROWN_OUT_INT_ENA + enable brown out interrupt + 9 + 1 + read-write + + + MAIN_TIMER_INT_ENA + enable RTC main timer interrupt + 10 + 1 + read-write + + + SARADC1_INT_ENA + enable saradc1 interrupt + 11 + 1 + read-write + + + TSENS_INT_ENA + enable tsens interrupt + 12 + 1 + read-write + + + COCPU_INT_ENA + enable riscV cocpu interrupt + 13 + 1 + read-write + + + SARADC2_INT_ENA + enable saradc2 interrupt + 14 + 1 + read-write + + + SWD_INT_ENA + enable super watch dog interrupt + 15 + 1 + read-write + + + XTAL32K_DEAD_INT_ENA + enable xtal32k_dead interrupt + 16 + 1 + read-write + + + COCPU_TRAP_INT_ENA + enable cocpu trap interrupt + 17 + 1 + read-write + + + TOUCH_TIMEOUT_INT_ENA + enable touch timeout interrupt + 18 + 1 + read-write + + + GLITCH_DET_INT_ENA + enbale gitch det interrupt + 19 + 1 + read-write + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA + touch approach mode loop interrupt + 20 + 1 + read-write + + + + + INT_RAW_RTC + rtc interrupt register + 0x44 + 0x20 + + + SLP_WAKEUP_INT_RAW + sleep wakeup interrupt raw + 0 + 1 + read-only + + + SLP_REJECT_INT_RAW + sleep reject interrupt raw + 1 + 1 + read-only + + + SDIO_IDLE_INT_RAW + SDIO idle interrupt raw + 2 + 1 + read-only + + + WDT_INT_RAW + RTC WDT interrupt raw + 3 + 1 + read-only + + + TOUCH_SCAN_DONE_INT_RAW + enable touch scan done interrupt raw + 4 + 1 + read-only + + + ULP_CP_INT_RAW + ULP-coprocessor interrupt raw + 5 + 1 + read-only + + + TOUCH_DONE_INT_RAW + touch interrupt raw + 6 + 1 + read-only + + + TOUCH_ACTIVE_INT_RAW + touch active interrupt raw + 7 + 1 + read-only + + + TOUCH_INACTIVE_INT_RAW + touch inactive interrupt raw + 8 + 1 + read-only + + + BROWN_OUT_INT_RAW + brown out interrupt raw + 9 + 1 + read-only + + + MAIN_TIMER_INT_RAW + RTC main timer interrupt raw + 10 + 1 + read-only + + + SARADC1_INT_RAW + saradc1 interrupt raw + 11 + 1 + read-only + + + TSENS_INT_RAW + tsens interrupt raw + 12 + 1 + read-only + + + COCPU_INT_RAW + riscV cocpu interrupt raw + 13 + 1 + read-only + + + SARADC2_INT_RAW + saradc2 interrupt raw + 14 + 1 + read-only + + + SWD_INT_RAW + super watch dog interrupt raw + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_RAW + xtal32k dead detection interrupt raw + 16 + 1 + read-only + + + COCPU_TRAP_INT_RAW + cocpu trap interrupt raw + 17 + 1 + read-only + + + TOUCH_TIMEOUT_INT_RAW + touch timeout interrupt raw + 18 + 1 + read-only + + + GLITCH_DET_INT_RAW + glitch_det_interrupt_raw + 19 + 1 + read-only + + + TOUCH_APPROACH_LOOP_DONE_INT_RAW + touch approach mode loop interrupt raw + 20 + 1 + read-write + + + + + INT_ST_RTC + rtc interrupt register + 0x48 + 0x20 + + + SLP_WAKEUP_INT_ST + sleep wakeup interrupt state + 0 + 1 + read-only + + + SLP_REJECT_INT_ST + sleep reject interrupt state + 1 + 1 + read-only + + + SDIO_IDLE_INT_ST + SDIO idle interrupt state + 2 + 1 + read-only + + + WDT_INT_ST + RTC WDT interrupt state + 3 + 1 + read-only + + + TOUCH_SCAN_DONE_INT_ST + enable touch scan done interrupt raw + 4 + 1 + read-only + + + ULP_CP_INT_ST + ULP-coprocessor interrupt state + 5 + 1 + read-only + + + TOUCH_DONE_INT_ST + touch done interrupt state + 6 + 1 + read-only + + + TOUCH_ACTIVE_INT_ST + touch active interrupt state + 7 + 1 + read-only + + + TOUCH_INACTIVE_INT_ST + touch inactive interrupt state + 8 + 1 + read-only + + + BROWN_OUT_INT_ST + brown out interrupt state + 9 + 1 + read-only + + + MAIN_TIMER_INT_ST + RTC main timer interrupt state + 10 + 1 + read-only + + + SARADC1_INT_ST + saradc1 interrupt state + 11 + 1 + read-only + + + TSENS_INT_ST + tsens interrupt state + 12 + 1 + read-only + + + COCPU_INT_ST + riscV cocpu interrupt state + 13 + 1 + read-only + + + SARADC2_INT_ST + saradc2 interrupt state + 14 + 1 + read-only + + + SWD_INT_ST + super watch dog interrupt state + 15 + 1 + read-only + + + XTAL32K_DEAD_INT_ST + xtal32k dead detection interrupt state + 16 + 1 + read-only + + + COCPU_TRAP_INT_ST + cocpu trap interrupt state + 17 + 1 + read-only + + + TOUCH_TIMEOUT_INT_ST + Touch timeout interrupt state + 18 + 1 + read-only + + + GLITCH_DET_INT_ST + glitch_det_interrupt state + 19 + 1 + read-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ST + touch approach mode loop interrupt state + 20 + 1 + read-only + + + + + INT_CLR_RTC + rtc interrupt register + 0x4C + 0x20 + + + SLP_WAKEUP_INT_CLR + Clear sleep wakeup interrupt state + 0 + 1 + write-only + + + SLP_REJECT_INT_CLR + Clear sleep reject interrupt state + 1 + 1 + write-only + + + SDIO_IDLE_INT_CLR + Clear SDIO idle interrupt state + 2 + 1 + write-only + + + WDT_INT_CLR + Clear RTC WDT interrupt state + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_CLR + clear touch scan done interrupt raw + 4 + 1 + write-only + + + ULP_CP_INT_CLR + Clear ULP-coprocessor interrupt state + 5 + 1 + write-only + + + TOUCH_DONE_INT_CLR + Clear touch done interrupt state + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_CLR + Clear touch active interrupt state + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_CLR + Clear touch inactive interrupt state + 8 + 1 + write-only + + + BROWN_OUT_INT_CLR + Clear brown out interrupt state + 9 + 1 + write-only + + + MAIN_TIMER_INT_CLR + Clear RTC main timer interrupt state + 10 + 1 + write-only + + + SARADC1_INT_CLR + Clear saradc1 interrupt state + 11 + 1 + write-only + + + TSENS_INT_CLR + Clear tsens interrupt state + 12 + 1 + write-only + + + COCPU_INT_CLR + Clear riscV cocpu interrupt state + 13 + 1 + write-only + + + SARADC2_INT_CLR + Clear saradc2 interrupt state + 14 + 1 + write-only + + + SWD_INT_CLR + Clear super watch dog interrupt state + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_CLR + Clear RTC WDT interrupt state + 16 + 1 + write-only + + + COCPU_TRAP_INT_CLR + Clear cocpu trap interrupt state + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_CLR + Clear touch timeout interrupt state + 18 + 1 + write-only + + + GLITCH_DET_INT_CLR + Clear glitch det interrupt state + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_CLR + cleartouch approach mode loop interrupt state + 20 + 1 + write-only + + + + + STORE0 + Reserved register + 0x50 + 0x20 + + + SCRATCH0 + Reserved register + 0 + 32 + read-write + + + + + STORE1 + Reserved register + 0x54 + 0x20 + + + SCRATCH1 + Reserved register + 0 + 32 + read-write + + + + + STORE2 + Reserved register + 0x58 + 0x20 + + + SCRATCH2 + Reserved register + 0 + 32 + read-write + + + + + STORE3 + Reserved register + 0x5C + 0x20 + + + SCRATCH3 + Reserved register + 0 + 32 + read-write + + + + + EXT_XTL_CONF + Reserved register + 0x60 + 0x20 + 0x00066C80 + + + XTAL32K_WDT_EN + xtal 32k watch dog enable + 0 + 1 + read-write + + + XTAL32K_WDT_CLK_FO + xtal 32k watch dog clock force on + 1 + 1 + read-write + + + XTAL32K_WDT_RESET + xtal 32k watch dog sw reset + 2 + 1 + read-write + + + XTAL32K_EXT_CLK_FO + xtal 32k external xtal clock force on + 3 + 1 + read-write + + + XTAL32K_AUTO_BACKUP + xtal 32k switch to back up clock when xtal is dead + 4 + 1 + read-write + + + XTAL32K_AUTO_RESTART + xtal 32k restart xtal when xtal is dead + 5 + 1 + read-write + + + XTAL32K_AUTO_RETURN + xtal 32k switch back xtal when xtal is restarted + 6 + 1 + read-write + + + XTAL32K_XPD_FORCE + Xtal 32k xpd control by sw or fsm + 7 + 1 + read-write + + + ENCKINIT_XTAL_32K + apply an internal clock to help xtal 32k to start + 8 + 1 + read-write + + + DBUF_XTAL_32K + 0: single-end buffer 1: differential buffer + 9 + 1 + read-write + + + DGM_XTAL_32K + xtal_32k gm control + 10 + 3 + read-write + + + DRES_XTAL_32K + DRES_XTAL_32K + 13 + 3 + read-write + + + XPD_XTAL_32K + XPD_XTAL_32K + 16 + 1 + read-write + + + DAC_XTAL_32K + DAC_XTAL_32K + 17 + 3 + read-write + + + WDT_STATE + state of 32k_wdt + 20 + 3 + read-only + + + XTAL32K_GPIO_SEL + XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C + 23 + 1 + read-write + + + XTL_EXT_CTR_LV + 0: power down XTAL at high level, 1: power down XTAL at low level + 30 + 1 + read-write + + + XTL_EXT_CTR_EN + Reserved register + 31 + 1 + read-write + + + + + EXT_WAKEUP_CONF + ext wakeup configure + 0x64 + 0x20 + + + GPIO_WAKEUP_FILTER + enable filter for gpio wakeup event + 29 + 1 + read-write + + + EXT_WAKEUP0_LV + 0: external wakeup at low level, 1: external wakeup at high level + 30 + 1 + read-write + + + EXT_WAKEUP1_LV + 0: external wakeup at low level, 1: external wakeup at high level + 31 + 1 + read-write + + + + + SLP_REJECT_CONF + reject sleep register + 0x68 + 0x20 + + + SLEEP_REJECT_ENA + sleep reject enable + 12 + 18 + read-write + + + LIGHT_SLP_REJECT_EN + enable reject for light sleep + 30 + 1 + read-write + + + DEEP_SLP_REJECT_EN + enable reject for deep sleep + 31 + 1 + read-write + + + + + CPU_PERIOD_CONF + conigure cpu freq + 0x6C + 0x20 + + + CPUSEL_CONF + CPU sel option + 29 + 1 + read-write + + + CPUPERIOD_SEL + conigure cpu freq + 30 + 2 + read-write + + + + + SDIO_ACT_CONF + No public + 0x70 + 0x20 + + + SDIO_ACT_DNUM + No public + 22 + 10 + read-write + + + + + CLK_CONF + configure clock register + 0x74 + 0x20 + 0x1158321C + + + EFUSE_CLK_FORCE_GATING + force efuse clk gating + 1 + 1 + read-write + + + EFUSE_CLK_FORCE_NOGATING + force efuse clk nogating + 2 + 1 + read-write + + + CK8M_DIV_SEL_VLD + used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk + 3 + 1 + read-write + + + CK8M_DIV + CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024. + 4 + 2 + read-write + + + ENB_CK8M + disable CK8M and CK8M_D256_OUT + 6 + 1 + read-write + + + ENB_CK8M_DIV + 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256 + 7 + 1 + read-write + + + DIG_XTAL32K_EN + enable CK_XTAL_32K for digital core (no relationship with RTC core) + 8 + 1 + read-write + + + DIG_CLK8M_D256_EN + enable CK8M_D256_OUT for digital core (no relationship with RTC core) + 9 + 1 + read-write + + + DIG_CLK8M_EN + enable CK8M for digital core (no relationship with RTC core) + 10 + 1 + read-write + + + CK8M_DIV_SEL + divider = reg_ck8m_div_sel + 1 + 12 + 3 + read-write + + + XTAL_FORCE_NOGATING + XTAL force no gating during sleep + 15 + 1 + read-write + + + CK8M_FORCE_NOGATING + CK8M force no gating during sleep + 16 + 1 + read-write + + + CK8M_DFREQ + CK8M_DFREQ + 17 + 8 + read-write + + + CK8M_FORCE_PD + CK8M force power down + 25 + 1 + read-write + + + CK8M_FORCE_PU + CK8M force power up + 26 + 1 + read-write + + + XTAL_GLOBAL_FORCE_GATING + force global xtal gating + 27 + 1 + read-write + + + XTAL_GLOBAL_FORCE_NOGATING + force global xtal no gating + 28 + 1 + read-write + + + FAST_CLK_RTC_SEL + fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M + 29 + 1 + read-write + + + ANA_CLK_RTC_SEL + select slow clock + 30 + 2 + read-write + + + + + SLOW_CLK_CONF + configure slow clk + 0x78 + 0x20 + 0x00400000 + + + ANA_CLK_DIV_VLD + used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk + 22 + 1 + read-write + + + ANA_CLK_DIV + rtc clk div + 23 + 8 + read-write + + + SLOW_CLK_NEXT_EDGE + No public + 31 + 1 + read-write + + + + + SDIO_CONF + configure flash power + 0x7C + 0x20 + 0x0AB0BE0A + + + SDIO_TIMER_TARGET + timer count to apply reg_sdio_dcap after sdio power on + 0 + 8 + read-write + + + SDIO_DTHDRV + Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us. + 9 + 2 + read-write + + + SDIO_DCAP + ability to prevent LDO from overshoot + 11 + 2 + read-write + + + SDIO_INITI + add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k + 13 + 2 + read-write + + + SDIO_EN_INITI + 0 to set init[1:0]=0 + 15 + 1 + read-write + + + SDIO_DCURLIM + tune current limit threshold when tieh = 0. About 800mA/(8+d) + 16 + 3 + read-write + + + SDIO_MODECURLIM + select current limit mode + 19 + 1 + read-write + + + SDIO_ENCURLIM + enable current limit + 20 + 1 + read-write + + + SDIO_REG_PD_EN + power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + 21 + 1 + read-write + + + SDIO_FORCE + 1: use SW option to control SDIO_REG, 0: use state machine + 22 + 1 + read-write + + + SDIO_TIEH + SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + 23 + 1 + read-write + + + REG1P8_READY + read only register for REG1P8_READY + 24 + 1 + read-only + + + DREFL_SDIO + SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + 25 + 2 + read-write + + + DREFM_SDIO + SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + 27 + 2 + read-write + + + DREFH_SDIO + SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + 29 + 2 + read-write + + + XPD_SDIO + power on flash regulator + 31 + 1 + read-write + + + + + BIAS_CONF + No public + 0x80 + 0x20 + 0x00010800 + + + BIAS_BUF_IDLE + No public + 10 + 1 + read-write + + + BIAS_BUF_WAKE + No public + 11 + 1 + read-write + + + BIAS_BUF_DEEP_SLP + No public + 12 + 1 + read-write + + + BIAS_BUF_MONITOR + No public + 13 + 1 + read-write + + + PD_CUR_DEEP_SLP + xpd cur when rtc in sleep_state + 14 + 1 + read-write + + + PD_CUR_MONITOR + xpd cur when rtc in monitor state + 15 + 1 + read-write + + + BIAS_SLEEP_DEEP_SLP + bias_sleep when rtc in sleep_state + 16 + 1 + read-write + + + BIAS_SLEEP_MONITOR + bias_sleep when rtc in monitor state + 17 + 1 + read-write + + + DBG_ATTEN_DEEP_SLP + DBG_ATTEN when rtc in sleep state + 18 + 4 + read-write + + + DBG_ATTEN_MONITOR + DBG_ATTEN when rtc in monitor state + 22 + 4 + read-write + + + DBG_ATTEN_WAKEUP + No public + 26 + 4 + read-write + + + + + RTC + configure rtc regulator + 0x84 + 0x20 + 0xA0000000 + + + DIG_REG_CAL_EN + enable dig regulator cali + 7 + 1 + read-write + + + SCK_DCAP + SCK_DCAP + 14 + 8 + read-write + + + DBOOST_FORCE_PD + RTC_DBOOST force power down + 28 + 1 + read-write + + + DBOOST_FORCE_PU + RTC_DBOOST force power up + 29 + 1 + read-write + + + REGULATOR_FORCE_PD + RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 30 + 1 + read-write + + + REGULATOR_FORCE_PU + RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + 31 + 1 + read-write + + + + + PWC + configure rtc power + 0x88 + 0x20 + 0x00000925 + + + FASTMEM_FORCE_NOISO + Fast RTC memory force no ISO + 0 + 1 + read-write + + + FASTMEM_FORCE_ISO + Fast RTC memory force ISO + 1 + 1 + read-write + + + SLOWMEM_FORCE_NOISO + RTC memory force no ISO + 2 + 1 + read-write + + + SLOWMEM_FORCE_ISO + RTC memory force ISO + 3 + 1 + read-write + + + FORCE_ISO + rtc_peri force ISO + 4 + 1 + read-write + + + FORCE_NOISO + rtc_peri force no ISO + 5 + 1 + read-write + + + FASTMEM_FOLW_CPU + 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine + 6 + 1 + read-write + + + FASTMEM_FORCE_LPD + Fast RTC memory force PD + 7 + 1 + read-write + + + FASTMEM_FORCE_LPU + Fast RTC memory force no PD + 8 + 1 + read-write + + + SLOWMEM_FOLW_CPU + 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine + 9 + 1 + read-write + + + SLOWMEM_FORCE_LPD + RTC memory force PD + 10 + 1 + read-write + + + SLOWMEM_FORCE_LPU + RTC memory force no PD + 11 + 1 + read-write + + + FORCE_PD + rtc_peri force power down + 18 + 1 + read-write + + + FORCE_PU + rtc_peri force power up + 19 + 1 + read-write + + + PD_EN + enable power down rtc_peri in sleep + 20 + 1 + read-write + + + PAD_FORCE_HOLD + rtc pad force hold + 21 + 1 + read-write + + + + + REGULATOR_DRV_CTRL + No public + 0x8C + 0x20 + + + REGULATOR_DRV_B_MONITOR + No public + 0 + 6 + read-write + + + REGULATOR_DRV_B_SLP + No public + 6 + 6 + read-write + + + DG_VDD_DRV_B_SLP + No public + 12 + 8 + read-write + + + DG_VDD_DRV_B_MONITOR + No public + 20 + 8 + read-write + + + + + DIG_PWC + configure digital power + 0x90 + 0x20 + 0x00545010 + + + LSLP_MEM_FORCE_PD + memories in digital core force PD in sleep + 3 + 1 + read-write + + + LSLP_MEM_FORCE_PU + memories in digital core force no PD in sleep + 4 + 1 + read-write + + + BT_FORCE_PD + internal SRAM 2 force power down + 11 + 1 + read-write + + + BT_FORCE_PU + internal SRAM 2 force power up + 12 + 1 + read-write + + + DG_PERI_FORCE_PD + internal SRAM 3 force power down + 13 + 1 + read-write + + + DG_PERI_FORCE_PU + internal SRAM 3 force power up + 14 + 1 + read-write + + + WIFI_FORCE_PD + wifi force power down + 17 + 1 + read-write + + + WIFI_FORCE_PU + wifi force power up + 18 + 1 + read-write + + + DG_WRAP_FORCE_PD + digital core force power down + 19 + 1 + read-write + + + DG_WRAP_FORCE_PU + digital core force power up + 20 + 1 + read-write + + + CPU_TOP_FORCE_PD + digital dcdc force power down + 21 + 1 + read-write + + + CPU_TOP_FORCE_PU + digital dcdc force power up + 22 + 1 + read-write + + + BT_PD_EN + enable power down internal SRAM 2 in sleep + 27 + 1 + read-write + + + DG_PERI_PD_EN + enable power down internal SRAM 3 in sleep + 28 + 1 + read-write + + + CPU_TOP_PD_EN + enable power down internal SRAM 4 in sleep + 29 + 1 + read-write + + + WIFI_PD_EN + enable power down wifi in sleep + 30 + 1 + read-write + + + DG_WRAP_PD_EN + enable power down all digital logic + 31 + 1 + read-write + + + + + DIG_ISO + congigure digital power isolation + 0x94 + 0x20 + 0xAA805080 + + + FORCE_OFF + No public + 7 + 1 + read-write + + + FORCE_ON + No public + 8 + 1 + read-write + + + DG_PAD_AUTOHOLD + read only register to indicate digital pad auto-hold status + 9 + 1 + read-only + + + CLR_DG_PAD_AUTOHOLD + wtite only register to clear digital pad auto-hold + 10 + 1 + write-only + + + DG_PAD_AUTOHOLD_EN + digital pad enable auto-hold + 11 + 1 + read-write + + + DG_PAD_FORCE_NOISO + digital pad force no ISO + 12 + 1 + read-write + + + DG_PAD_FORCE_ISO + digital pad force ISO + 13 + 1 + read-write + + + DG_PAD_FORCE_UNHOLD + digital pad force un-hold + 14 + 1 + read-write + + + DG_PAD_FORCE_HOLD + digital pad force hold + 15 + 1 + read-write + + + BT_FORCE_ISO + internal SRAM 2 force ISO + 22 + 1 + read-write + + + BT_FORCE_NOISO + internal SRAM 2 force no ISO + 23 + 1 + read-write + + + DG_PERI_FORCE_ISO + internal SRAM 3 force ISO + 24 + 1 + read-write + + + DG_PERI_FORCE_NOISO + internal SRAM 3 force no ISO + 25 + 1 + read-write + + + CPU_TOP_FORCE_ISO + internal SRAM 4 force ISO + 26 + 1 + read-write + + + CPU_TOP_FORCE_NOISO + internal SRAM 4 force no ISO + 27 + 1 + read-write + + + WIFI_FORCE_ISO + wifi force ISO + 28 + 1 + read-write + + + WIFI_FORCE_NOISO + wifi force no ISO + 29 + 1 + read-write + + + DG_WRAP_FORCE_ISO + digital core force ISO + 30 + 1 + read-write + + + DG_WRAP_FORCE_NOISO + digita core force no ISO + 31 + 1 + read-write + + + + + WDTCONFIG0 + configure rtc watch dog + 0x98 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + chip reset siginal pulse width + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + wdt reset whole chip enable + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + pause WDT in sleep + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + enable WDT reset APP CPU + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + enable WDT reset PRO CPU + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + enable WDT in flash boot + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + system reset counter length + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset counter length + 16 + 3 + read-write + + + WDT_STG3 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 19 + 3 + read-write + + + WDT_STG2 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 22 + 3 + read-write + + + WDT_STG1 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 25 + 3 + read-write + + + WDT_STG0 + 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en + 28 + 3 + read-write + + + WDT_EN + enable rtc watch dog + 31 + 1 + read-write + + + + + WDTCONFIG1 + stage0 hold time + 0x9C + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + stage0 hold time + 0 + 32 + read-write + + + + + WDTCONFIG2 + stage1 hold time + 0xA0 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + stage1 hold time + 0 + 32 + read-write + + + + + WDTCONFIG3 + stage2 hold time + 0xA4 + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + stage2 hold time + 0 + 32 + read-write + + + + + WDTCONFIG4 + stage3 hold time + 0xA8 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + stage3 hold time + 0 + 32 + read-write + + + + + WDTFEED + rtc wdt feed + 0xAC + 0x20 + + + WDT_FEED + rtc wdt feed + 31 + 1 + write-only + + + + + WDTWPROTECT + configure rtc watch dog + 0xB0 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + rtc watch dog key + 0 + 32 + read-write + + + + + SWD_CONF + congfigure super watch dog + 0xB4 + 0x20 + 0x04B00000 + + + SWD_RESET_FLAG + swd reset flag + 0 + 1 + read-only + + + SWD_FEED_INT + swd interrupt for feeding + 1 + 1 + read-only + + + SWD_BYPASS_RST + bypass super watch dog reset + 17 + 1 + read-write + + + SWD_SIGNAL_WIDTH + adjust signal width send to swd + 18 + 10 + read-write + + + SWD_RST_FLAG_CLR + reset swd reset flag + 28 + 1 + write-only + + + SWD_FEED + Sw feed swd + 29 + 1 + write-only + + + SWD_DISABLE + disabel SWD + 30 + 1 + read-write + + + SWD_AUTO_FEED_EN + automatically feed swd when int comes + 31 + 1 + read-write + + + + + SWD_WPROTECT + super watch dog key + 0xB8 + 0x20 + 0x8F1D312A + + + SWD_WKEY + super watch dog key + 0 + 32 + read-write + + + + + SW_CPU_STALL + configure cpu stall by sw + 0xBC + 0x20 + + + SW_STALL_APPCPU_C1 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 20 + 6 + read-write + + + SW_STALL_PROCPU_C1 + {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU + 26 + 6 + read-write + + + + + STORE4 + reserved register + 0xC0 + 0x20 + + + SCRATCH4 + reserved register + 0 + 32 + read-write + + + + + STORE5 + reserved register + 0xC4 + 0x20 + + + SCRATCH5 + reserved register + 0 + 32 + read-write + + + + + STORE6 + reserved register + 0xC8 + 0x20 + + + SCRATCH6 + reserved register + 0 + 32 + read-write + + + + + STORE7 + reserved register + 0xCC + 0x20 + + + SCRATCH7 + reserved register + 0 + 32 + read-write + + + + + LOW_POWER_ST + reserved register + 0xD0 + 0x20 + + + XPD_ROM0 + rom0 power down + 0 + 1 + read-only + + + XPD_DIG_DCDC + External DCDC power down + 2 + 1 + read-only + + + PERI_ISO + rtc peripheral iso + 3 + 1 + read-only + + + XPD_RTC_PERI + rtc peripheral power down + 4 + 1 + read-only + + + WIFI_ISO + wifi iso + 5 + 1 + read-only + + + XPD_WIFI + wifi wrap power down + 6 + 1 + read-only + + + DIG_ISO + digital wrap iso + 7 + 1 + read-only + + + XPD_DIG + digital wrap power down + 8 + 1 + read-only + + + TOUCH_STATE_START + touch should start to work + 9 + 1 + read-only + + + TOUCH_STATE_SWITCH + touch is about to working. Switch rtc main state + 10 + 1 + read-only + + + TOUCH_STATE_SLP + touch is in sleep state + 11 + 1 + read-only + + + TOUCH_STATE_DONE + touch is done + 12 + 1 + read-only + + + COCPU_STATE_START + ulp/cocpu should start to work + 13 + 1 + read-only + + + COCPU_STATE_SWITCH + ulp/cocpu is about to working. Switch rtc main state + 14 + 1 + read-only + + + COCPU_STATE_SLP + ulp/cocpu is in sleep state + 15 + 1 + read-only + + + COCPU_STATE_DONE + ulp/cocpu is done + 16 + 1 + read-only + + + MAIN_STATE_XTAL_ISO + no use any more + 17 + 1 + read-only + + + MAIN_STATE_PLL_ON + rtc main state machine is in states that pll should be running + 18 + 1 + read-only + + + RDY_FOR_WAKEUP + rtc is ready to receive wake up trigger from wake up source + 19 + 1 + read-only + + + MAIN_STATE_WAIT_END + rtc main state machine has been waited for some cycles + 20 + 1 + read-only + + + IN_WAKEUP_STATE + rtc main state machine is in the states of wakeup process + 21 + 1 + read-only + + + IN_LOW_POWER_STATE + rtc main state machine is in the states of low power + 22 + 1 + read-only + + + MAIN_STATE_IN_WAIT_8M + rtc main state machine is in wait 8m state + 23 + 1 + read-only + + + MAIN_STATE_IN_WAIT_PLL + rtc main state machine is in wait pll state + 24 + 1 + read-only + + + MAIN_STATE_IN_WAIT_XTL + rtc main state machine is in wait xtal state + 25 + 1 + read-only + + + MAIN_STATE_IN_SLP + rtc main state machine is in sleep state + 26 + 1 + read-only + + + MAIN_STATE_IN_IDLE + rtc main state machine is in idle state + 27 + 1 + read-only + + + MAIN_STATE + rtc main state machine status + 28 + 4 + read-only + + + + + DIAG0 + No public + 0xD4 + 0x20 + + + LOW_POWER_DIAG1 + No public + 0 + 32 + read-only + + + + + PAD_HOLD + rtc pad hold configure + 0xD8 + 0x20 + + + TOUCH_PAD0_HOLD + hold rtc pad0 + 0 + 1 + read-write + + + TOUCH_PAD1_HOLD + hold rtc pad-1 + 1 + 1 + read-write + + + TOUCH_PAD2_HOLD + hold rtc pad-2 + 2 + 1 + read-write + + + TOUCH_PAD3_HOLD + hold rtc pad-3 + 3 + 1 + read-write + + + TOUCH_PAD4_HOLD + hold rtc pad-4 + 4 + 1 + read-write + + + TOUCH_PAD5_HOLD + hold rtc pad-5 + 5 + 1 + read-write + + + TOUCH_PAD6_HOLD + hold rtc pad-6 + 6 + 1 + read-write + + + TOUCH_PAD7_HOLD + hold rtc pad-7 + 7 + 1 + read-write + + + TOUCH_PAD8_HOLD + hold rtc pad-8 + 8 + 1 + read-write + + + TOUCH_PAD9_HOLD + hold rtc pad-9 + 9 + 1 + read-write + + + TOUCH_PAD10_HOLD + hold rtc pad-10 + 10 + 1 + read-write + + + TOUCH_PAD11_HOLD + hold rtc pad-11 + 11 + 1 + read-write + + + TOUCH_PAD12_HOLD + hold rtc pad-12 + 12 + 1 + read-write + + + TOUCH_PAD13_HOLD + hold rtc pad-13 + 13 + 1 + read-write + + + TOUCH_PAD14_HOLD + hold rtc pad-14 + 14 + 1 + read-write + + + X32P_HOLD + hold rtc pad-15 + 15 + 1 + read-write + + + X32N_HOLD + hold rtc pad-16 + 16 + 1 + read-write + + + PDAC1_HOLD + hold rtc pad-17 + 17 + 1 + read-write + + + PDAC2_HOLD + hold rtc pad-18 + 18 + 1 + read-write + + + PAD19_HOLD + hold rtc pad-19 + 19 + 1 + read-write + + + PAD20_HOLD + hold rtc pad-20 + 20 + 1 + read-write + + + PAD21_HOLD + hold rtc pad-21 + 21 + 1 + read-write + + + + + DIG_PAD_HOLD + configure digtal pad hold + 0xDC + 0x20 + + + DIG_PAD_HOLD + configure digtal pad hold + 0 + 32 + read-write + + + + + EXT_WAKEUP1 + configure ext1 wakeup + 0xE0 + 0x20 + + + EXT_WAKEUP1_SEL + Bitmap to select RTC pads for ext wakeup1 + 0 + 22 + read-write + + + EXT_WAKEUP1_STATUS_CLR + clear ext wakeup1 status + 22 + 1 + write-only + + + + + EXT_WAKEUP1_STATUS + check ext wakeup1 status + 0xE4 + 0x20 + + + EXT_WAKEUP1_STATUS + ext wakeup1 status + 0 + 22 + read-only + + + + + BROWN_OUT + congfigure brownout + 0xE8 + 0x20 + 0x43FF0010 + + + BROWN_OUT_INT_WAIT + brown out interrupt wait cycles + 4 + 10 + read-write + + + BROWN_OUT_CLOSE_FLASH_ENA + enable close flash when brown out happens + 14 + 1 + read-write + + + BROWN_OUT_PD_RF_ENA + enable power down RF when brown out happens + 15 + 1 + read-write + + + BROWN_OUT_RST_WAIT + brown out reset wait cycles + 16 + 10 + read-write + + + BROWN_OUT_RST_ENA + enable brown out reset + 26 + 1 + read-write + + + BROWN_OUT_RST_SEL + 1: 4-pos reset, 0: sys_reset + 27 + 1 + read-write + + + BROWN_OUT_ANA_RST_EN + enable brown out reset en + 28 + 1 + read-write + + + BROWN_OUT_CNT_CLR + clear brown out counter + 29 + 1 + write-only + + + BROWN_OUT_ENA + enable brown out + 30 + 1 + read-write + + + DET + get brown out detect + 31 + 1 + read-only + + + + + TIME_LOW1 + RTC timer low 32 bits + 0xEC + 0x20 + + + TIMER_VALUE1_LOW + RTC timer low 32 bits + 0 + 32 + read-only + + + + + TIME_HIGH1 + RTC timer high 16 bits + 0xF0 + 0x20 + + + TIMER_VALUE1_HIGH + RTC timer high 16 bits + 0 + 16 + read-only + + + + + XTAL32K_CLK_FACTOR + xtal 32k watch dog backup clock factor + 0xF4 + 0x20 + + + XTAL32K_CLK_FACTOR + xtal 32k watch dog backup clock factor + 0 + 32 + read-write + + + + + XTAL32K_CONF + configure xtal32k + 0xF8 + 0x20 + 0x0FF00000 + + + XTAL32K_RETURN_WAIT + cycles to wait to return noral xtal 32k + 0 + 4 + read-write + + + XTAL32K_RESTART_WAIT + cycles to wait to repower on xtal 32k + 4 + 16 + read-write + + + XTAL32K_WDT_TIMEOUT + If no clock detected for this amount of time 32k is regarded as dead + 20 + 8 + read-write + + + XTAL32K_STABLE_THRES + if restarted xtal32k period is smaller than this, it is regarded as stable + 28 + 4 + read-write + + + + + ULP_CP_TIMER + configure ulp + 0xFC + 0x20 + + + ULP_CP_PC_INIT + ULP-coprocessor PC initial address + 0 + 11 + read-write + + + ULP_CP_GPIO_WAKEUP_ENA + ULP-coprocessor wakeup by GPIO enable + 29 + 1 + read-write + + + ULP_CP_GPIO_WAKEUP_CLR + ULP-coprocessor wakeup by GPIO state clear + 30 + 1 + write-only + + + ULP_CP_SLP_TIMER_EN + ULP-coprocessor timer enable bit + 31 + 1 + read-write + + + + + ULP_CP_CTRL + configure ulp + 0x100 + 0x20 + 0x00100200 + + + ULP_CP_MEM_ADDR_INIT + No public + 0 + 11 + read-write + + + ULP_CP_MEM_ADDR_SIZE + No public + 11 + 11 + read-write + + + ULP_CP_MEM_OFFST_CLR + No public + 22 + 1 + write-only + + + ULP_CP_CLK_FO + ulp coprocessor clk force on + 28 + 1 + read-write + + + ULP_CP_RESET + ulp coprocessor clk software reset + 29 + 1 + read-write + + + ULP_CP_FORCE_START_TOP + 1: ULP-coprocessor is started by SW + 30 + 1 + read-write + + + ULP_CP_START_TOP + Write 1 to start ULP-coprocessor + 31 + 1 + read-write + + + + + COCPU_CTRL + configure ulp-riscv + 0x104 + 0x20 + 0x008A0810 + + + COCPU_CLK_FO + cocpu clk force on + 0 + 1 + read-write + + + COCPU_START_2_RESET_DIS + time from start cocpu to pull down reset + 1 + 6 + read-write + + + COCPU_START_2_INTR_EN + time from start cocpu to give start interrupt + 7 + 6 + read-write + + + COCPU_SHUT + to shut cocpu + 13 + 1 + read-write + + + COCPU_SHUT_2_CLK_DIS + time from shut cocpu to disable clk + 14 + 8 + read-write + + + COCPU_SHUT_RESET_EN + to reset cocpu + 22 + 1 + read-write + + + COCPU_SEL + 1: old ULP 0: new riscV + 23 + 1 + read-write + + + COCPU_DONE_FORCE + 1: select riscv done 0: select ulp done + 24 + 1 + read-write + + + COCPU_DONE + done signal used by riscv to control timer. + 25 + 1 + read-write + + + COCPU_SW_INT_TRIGGER + trigger cocpu register interrupt + 26 + 1 + write-only + + + COCPU_CLKGATE_EN + open ulp-riscv clk gate + 27 + 1 + read-write + + + + + TOUCH_CTRL1 + configure touch controller + 0x108 + 0x20 + 0x10000100 + + + TOUCH_SLEEP_CYCLES + sleep cycles for timer + 0 + 16 + read-write + + + TOUCH_MEAS_NUM + the meas length (in 8MHz) + 16 + 16 + read-write + + + + + TOUCH_CTRL2 + configure touch controller + 0x10C + 0x20 + 0x000840CC + + + TOUCH_DRANGE + TOUCH_DRANGE + 2 + 2 + read-write + + + TOUCH_DREFL + TOUCH_DREFL + 4 + 2 + read-write + + + TOUCH_DREFH + TOUCH_DREFH + 6 + 2 + read-write + + + TOUCH_XPD_BIAS + TOUCH_XPD_BIAS + 8 + 1 + read-write + + + TOUCH_REFC + TOUCH pad0 reference cap + 9 + 3 + read-write + + + TOUCH_DBIAS + 1:use self bias 0:use bandgap bias + 12 + 1 + read-write + + + TOUCH_SLP_TIMER_EN + touch timer enable bit + 13 + 1 + read-write + + + TOUCH_START_FSM_EN + 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm + 14 + 1 + read-write + + + TOUCH_START_EN + 1: start touch fsm + 15 + 1 + read-write + + + TOUCH_START_FORCE + 1: to start touch fsm by SW + 16 + 1 + read-write + + + TOUCH_XPD_WAIT + the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + 17 + 8 + read-write + + + TOUCH_SLP_CYC_DIV + when a touch pad is active sleep cycle could be divided by this number + 25 + 2 + read-write + + + TOUCH_TIMER_FORCE_DONE + force touch timer done + 27 + 2 + read-write + + + TOUCH_RESET + reset upgrade touch + 29 + 1 + read-write + + + TOUCH_CLK_FO + touch clock force on + 30 + 1 + read-write + + + TOUCH_CLKGATE_EN + touch clock enable + 31 + 1 + read-write + + + + + TOUCH_SCAN_CTRL + configure touch controller + 0x110 + 0x20 + 0xF0000102 + + + TOUCH_DENOISE_RES + De-noise resolution: 12/10/8/4 bit + 0 + 2 + read-write + + + TOUCH_DENOISE_EN + touch pad0 will be used to de-noise + 2 + 1 + read-write + + + TOUCH_INACTIVE_CONNECTION + inactive touch pads connect to 1: gnd 0: HighZ + 8 + 1 + read-write + + + TOUCH_SHIELD_PAD_EN + touch pad14 will be used as shield + 9 + 1 + read-write + + + TOUCH_SCAN_PAD_MAP + touch scan mode pad enable map + 10 + 15 + read-write + + + TOUCH_BUFDRV + touch7 buffer driver strength + 25 + 3 + read-write + + + TOUCH_OUT_RING + select out ring pad + 28 + 4 + read-write + + + + + TOUCH_SLP_THRES + configure touch controller + 0x114 + 0x20 + 0x78000000 + + + TOUCH_SLP_TH + the threshold for sleep touch pad + 0 + 22 + read-write + + + TOUCH_SLP_APPROACH_EN + sleep pad approach function enable + 26 + 1 + read-write + + + TOUCH_SLP_PAD + configure which pad as slp pad + 27 + 5 + read-write + + + + + TOUCH_APPROACH + configure touch controller + 0x118 + 0x20 + 0x50000000 + + + TOUCH_SLP_CHANNEL_CLR + clear touch slp channel + 23 + 1 + write-only + + + TOUCH_APPROACH_MEAS_TIME + approach pads total meas times + 24 + 8 + read-write + + + + + TOUCH_FILTER_CTRL + configure touch controller + 0x11C + 0x20 + 0x96AA8800 + + + TOUCH_BYPASS_NEG_NOISE_THRES + bypass neg noise thres + 7 + 1 + read-write + + + TOUCH_BYPASS_NOISE_THRES + bypaas noise thres + 8 + 1 + read-write + + + TOUCH_SMOOTH_LVL + smooth filter factor + 9 + 2 + read-write + + + TOUCH_JITTER_STEP + touch jitter step + 11 + 4 + read-write + + + TOUCH_NEG_NOISE_LIMIT + negative threshold counter limit + 15 + 4 + read-write + + + TOUCH_NEG_NOISE_THRES + neg noise thres + 19 + 2 + read-write + + + TOUCH_NOISE_THRES + noise thres + 21 + 2 + read-write + + + TOUCH_HYSTERESIS + hysteresis + 23 + 2 + read-write + + + TOUCH_DEBOUNCE + debounce counter + 25 + 3 + read-write + + + TOUCH_FILTER_MODE + 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter + 28 + 3 + read-write + + + TOUCH_FILTER_EN + touch filter enable + 31 + 1 + read-write + + + + + USB_CONF + usb configure + 0x120 + 0x20 + + + USB_VREFH + reg_usb_vrefh + 0 + 2 + read-write + + + USB_VREFL + reg_usb_vrefl + 2 + 2 + read-write + + + USB_VREF_OVERRIDE + reg_usb_vref_override + 4 + 1 + read-write + + + USB_PAD_PULL_OVERRIDE + reg_usb_pad_pull_override + 5 + 1 + read-write + + + USB_DP_PULLUP + reg_usb_dp_pullup + 6 + 1 + read-write + + + USB_DP_PULLDOWN + reg_usb_dp_pulldown + 7 + 1 + read-write + + + USB_DM_PULLUP + reg_usb_dm_pullup + 8 + 1 + read-write + + + USB_DM_PULLDOWN + reg_usb_dm_pulldown + 9 + 1 + read-write + + + USB_PULLUP_VALUE + reg_usb_pullup_value + 10 + 1 + read-write + + + USB_PAD_ENABLE_OVERRIDE + reg_usb_pad_enable_override + 11 + 1 + read-write + + + USB_PAD_ENABLE + reg_usb_pad_enable + 12 + 1 + read-write + + + USB_TXM + reg_usb_txm + 13 + 1 + read-write + + + USB_TXP + reg_usb_txp + 14 + 1 + read-write + + + USB_TX_EN + reg_usb_tx_en + 15 + 1 + read-write + + + USB_TX_EN_OVERRIDE + reg_usb_tx_en_override + 16 + 1 + read-write + + + USB_RESET_DISABLE + reg_usb_reset_disable + 17 + 1 + read-write + + + IO_MUX_RESET_DISABLE + reg_io_mux_reset_disable + 18 + 1 + read-write + + + SW_USB_PHY_SEL + reg_sw_usb_phy_sel + 19 + 1 + read-write + + + SW_HW_USB_PHY_SEL + reg_sw_hw_usb_phy_sel + 20 + 1 + read-write + + + + + TOUCH_TIMEOUT_CTRL + configure touch controller + 0x124 + 0x20 + 0x007FFFFF + + + TOUCH_TIMEOUT_NUM + configure touch timerout time + 0 + 22 + read-write + + + TOUCH_TIMEOUT_EN + enable touch timerout + 22 + 1 + read-write + + + + + SLP_REJECT_CAUSE + get reject casue + 0x128 + 0x20 + + + REJECT_CAUSE + sleep reject cause + 0 + 18 + read-only + + + + + OPTION1 + rtc common configure + 0x12C + 0x20 + + + FORCE_DOWNLOAD_BOOT + force chip entry download boot by sw + 0 + 1 + read-write + + + + + SLP_WAKEUP_CAUSE + get wakeup cause + 0x130 + 0x20 + + + WAKEUP_CAUSE + sleep wakeup cause + 0 + 17 + read-only + + + + + ULP_CP_TIMER_1 + configure ulp sleep time + 0x134 + 0x20 + 0x0000C800 + + + ULP_CP_TIMER_SLP_CYCLE + sleep cycles for ULP-coprocessor timer + 8 + 24 + read-write + + + + + INT_ENA_RTC_W1TS + oneset rtc interrupt + 0x138 + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TS + enable sleep wakeup interrupt + 0 + 1 + write-only + + + SLP_REJECT_INT_ENA_W1TS + enable sleep reject interrupt + 1 + 1 + write-only + + + SDIO_IDLE_INT_ENA_W1TS + enable SDIO idle interrupt + 2 + 1 + write-only + + + WDT_INT_ENA_W1TS + enable RTC WDT interrupt + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_ENA_W1TS + enable touch scan done interrupt + 4 + 1 + write-only + + + ULP_CP_INT_ENA_W1TS + enable ULP-coprocessor interrupt + 5 + 1 + write-only + + + TOUCH_DONE_INT_ENA_W1TS + enable touch done interrupt + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_ENA_W1TS + enable touch active interrupt + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_ENA_W1TS + enable touch inactive interrupt + 8 + 1 + write-only + + + BROWN_OUT_INT_ENA_W1TS + enable brown out interrupt + 9 + 1 + write-only + + + MAIN_TIMER_INT_ENA_W1TS + enable RTC main timer interrupt + 10 + 1 + write-only + + + SARADC1_INT_ENA_W1TS + enable saradc1 interrupt + 11 + 1 + write-only + + + TSENS_INT_ENA_W1TS + enable tsens interrupt + 12 + 1 + write-only + + + COCPU_INT_ENA_W1TS + enable riscV cocpu interrupt + 13 + 1 + write-only + + + SARADC2_INT_ENA_W1TS + enable saradc2 interrupt + 14 + 1 + write-only + + + SWD_INT_ENA_W1TS + enable super watch dog interrupt + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_ENA_W1TS + enable xtal32k_dead interrupt + 16 + 1 + write-only + + + COCPU_TRAP_INT_ENA_W1TS + enable cocpu trap interrupt + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_ENA_W1TS + enable touch timeout interrupt + 18 + 1 + write-only + + + GLITCH_DET_INT_ENA_W1TS + enbale gitch det interrupt + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + enbale touch approach_loop done interrupt + 20 + 1 + write-only + + + + + INT_ENA_RTC_W1TC + oneset clr rtc interrupt enable + 0x13C + 0x20 + + + SLP_WAKEUP_INT_ENA_W1TC + enable sleep wakeup interrupt + 0 + 1 + write-only + + + SLP_REJECT_INT_ENA_W1TC + enable sleep reject interrupt + 1 + 1 + write-only + + + SDIO_IDLE_INT_ENA_W1TC + enable SDIO idle interrupt + 2 + 1 + write-only + + + WDT_INT_ENA_W1TC + enable RTC WDT interrupt + 3 + 1 + write-only + + + TOUCH_SCAN_DONE_INT_ENA_W1TC + enable touch scan done interrupt + 4 + 1 + write-only + + + ULP_CP_INT_ENA_W1TC + enable ULP-coprocessor interrupt + 5 + 1 + write-only + + + TOUCH_DONE_INT_ENA_W1TC + enable touch done interrupt + 6 + 1 + write-only + + + TOUCH_ACTIVE_INT_ENA_W1TC + enable touch active interrupt + 7 + 1 + write-only + + + TOUCH_INACTIVE_INT_ENA_W1TC + enable touch inactive interrupt + 8 + 1 + write-only + + + BROWN_OUT_INT_ENA_W1TC + enable brown out interrupt + 9 + 1 + write-only + + + MAIN_TIMER_INT_ENA_W1TC + enable RTC main timer interrupt + 10 + 1 + write-only + + + SARADC1_INT_ENA_W1TC + enable saradc1 interrupt + 11 + 1 + write-only + + + TSENS_INT_ENA_W1TC + enable tsens interrupt + 12 + 1 + write-only + + + COCPU_INT_ENA_W1TC + enable riscV cocpu interrupt + 13 + 1 + write-only + + + SARADC2_INT_ENA_W1TC + enable saradc2 interrupt + 14 + 1 + write-only + + + SWD_INT_ENA_W1TC + enable super watch dog interrupt + 15 + 1 + write-only + + + XTAL32K_DEAD_INT_ENA_W1TC + enable xtal32k_dead interrupt + 16 + 1 + write-only + + + COCPU_TRAP_INT_ENA_W1TC + enable cocpu trap interrupt + 17 + 1 + write-only + + + TOUCH_TIMEOUT_INT_ENA_W1TC + enable touch timeout interrupt + 18 + 1 + write-only + + + GLITCH_DET_INT_ENA_W1TC + enbale gitch det interrupt + 19 + 1 + write-only + + + TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + enbale touch approach_loop done interrupt + 20 + 1 + write-only + + + + + RETENTION_CTRL + configure retention + 0x140 + 0x20 + 0x28340000 + + + RETENTION_TAG_MODE + No public + 10 + 4 + read-write + + + RETENTION_TARGET + congfigure retention target cpu and/or tag + 14 + 2 + read-write + + + RETENTION_CLK_SEL + No public + 16 + 1 + read-write + + + RETENTION_DONE_WAIT + wait retention done cycle + 17 + 3 + read-write + + + RETENTION_CLKOFF_WAIT + wait clk off cycle + 20 + 4 + read-write + + + RETENTION_EN + enable retention + 24 + 1 + read-write + + + RETENTION_WAIT + wait cycles for rention operation + 25 + 7 + read-write + + + + + PG_CTRL + configure power glitch + 0x144 + 0x20 + + + POWER_GLITCH_DSENSE + GLITCH_DSENSE + 26 + 2 + read-write + + + POWER_GLITCH_FORCE_PD + force power glitch disable + 28 + 1 + read-write + + + POWER_GLITCH_FORCE_PU + force power glitch enable + 29 + 1 + read-write + + + POWER_GLITCH_EFUSE_SEL + select use analog fib signal + 30 + 1 + read-write + + + POWER_GLITCH_EN + enable power glitch + 31 + 1 + read-write + + + + + FIB_SEL + No public + 0x148 + 0x20 + 0x00000007 + + + FIB_SEL + No public + 0 + 3 + read-write + + + + + TOUCH_DAC + configure touch dac + 0x14C + 0x20 + + + TOUCH_PAD9_DAC + configure touch pad dac9 + 2 + 3 + read-write + + + TOUCH_PAD8_DAC + configure touch pad dac8 + 5 + 3 + read-write + + + TOUCH_PAD7_DAC + configure touch pad dac7 + 8 + 3 + read-write + + + TOUCH_PAD6_DAC + configure touch pad dac6 + 11 + 3 + read-write + + + TOUCH_PAD5_DAC + configure touch pad dac5 + 14 + 3 + read-write + + + TOUCH_PAD4_DAC + configure touch pad dac4 + 17 + 3 + read-write + + + TOUCH_PAD3_DAC + configure touch pad dac3 + 20 + 3 + read-write + + + TOUCH_PAD2_DAC + configure touch pad dac2 + 23 + 3 + read-write + + + TOUCH_PAD1_DAC + configure touch pad dac1 + 26 + 3 + read-write + + + TOUCH_PAD0_DAC + configure touch pad dac0 + 29 + 3 + read-write + + + + + TOUCH_DAC1 + configure touch dac + 0x150 + 0x20 + + + TOUCH_PAD14_DAC + configure touch pad dac14 + 17 + 3 + read-write + + + TOUCH_PAD13_DAC + configure touch pad dac13 + 20 + 3 + read-write + + + TOUCH_PAD12_DAC + configure touch pad dac12 + 23 + 3 + read-write + + + TOUCH_PAD11_DAC + configure touch pad dac11 + 26 + 3 + read-write + + + TOUCH_PAD10_DAC + configure touch pad dac10 + 29 + 3 + read-write + + + + + COCPU_DISABLE + configure ulp diable + 0x154 + 0x20 + + + DISABLE_RTC_CPU + configure ulp diable + 31 + 1 + read-write + + + + + DATE + version register + 0x1FC + 0x20 + 0x02101271 + + + DATE + version register + 0 + 28 + read-write + + + + + + + RTC_I2C + Peripheral RTC_I2C + RTC_I2C + 0x60008C00 + + 0x0 + 0x7C + registers + + + + SCL_LOW + configure low scl period + 0x0 + 0x20 + 0x00000100 + + + PERIOD + time period that scl =0 + 0 + 20 + read-write + + + + + CTRL + configure i2c ctrl + 0x4 + 0x20 + + + SDA_FORCE_OUT + 1=push pull,0=open drain + 0 + 1 + read-write + + + SCL_FORCE_OUT + 1=push pull,0=open drain + 1 + 1 + read-write + + + MS_MODE + 1=master,0=slave + 2 + 1 + read-write + + + TRANS_START + force start + 3 + 1 + read-write + + + TX_LSB_FIRST + transit lsb first + 4 + 1 + read-write + + + RX_LSB_FIRST + receive lsb first + 5 + 1 + read-write + + + I2C_CTRL_CLK_GATE_EN + configure i2c ctrl clk enable + 29 + 1 + read-write + + + I2C_RESET + rtc i2c sw reset + 30 + 1 + read-write + + + I2CCLK_EN + rtc i2c reg clk gating + 31 + 1 + read-write + + + + + STATUS + get i2c status + 0x8 + 0x20 + + + ACK_REC + ack response + 0 + 1 + read-only + + + SLAVE_RW + slave read or write + 1 + 1 + read-only + + + ARB_LOST + arbitration is lost + 2 + 1 + read-only + + + BUS_BUSY + bus is busy + 3 + 1 + read-only + + + SLAVE_ADDRESSED + slave reg sub address + 4 + 1 + read-only + + + BYTE_TRANS + One byte transit done + 5 + 1 + read-only + + + OP_CNT + which operation is working + 6 + 2 + read-only + + + SHIFT + shifter content + 16 + 8 + read-only + + + SCL_MAIN_STATE_LAST + i2c last main status + 24 + 3 + read-only + + + SCL_STATE_LAST + scl last status + 28 + 3 + read-only + + + + + TO + configure time out + 0xC + 0x20 + 0x00010000 + + + TIME_OUT + time out threshold + 0 + 20 + read-write + + + + + SLAVE_ADDR + configure slave id + 0x10 + 0x20 + + + SLAVE_ADDR + slave address + 0 + 15 + read-write + + + ADDR_10BIT_EN + i2c 10bit mode enable + 31 + 1 + read-write + + + + + SCL_HIGH + configure high scl period + 0x14 + 0x20 + 0x00000100 + + + PERIOD + time period that scl = 1 + 0 + 20 + read-write + + + + + SDA_DUTY + configure sda duty + 0x18 + 0x20 + 0x00000010 + + + NUM + time period for SDA to toggle after SCL goes low + 0 + 20 + read-write + + + + + SCL_START_PERIOD + configure scl start period + 0x1C + 0x20 + 0x00000008 + + + SCL_START_PERIOD + time period for SCL to toggle after I2C start is triggered + 0 + 20 + read-write + + + + + SCL_STOP_PERIOD + configure scl stop period + 0x20 + 0x20 + 0x00000008 + + + SCL_STOP_PERIOD + time period for SCL to stop after I2C end is triggered + 0 + 20 + read-write + + + + + INT_CLR + interrupt clear register + 0x24 + 0x20 + + + SLAVE_TRAN_COMP_INT_CLR + clear slave transit complete interrupt + 0 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + clear arbitration lost interrupt + 1 + 1 + write-only + + + MASTER_TRAN_COMP_INT_CLR + clear master transit complete interrupt + 2 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + clear transit complete interrupt + 3 + 1 + write-only + + + TIME_OUT_INT_CLR + clear time out interrupt + 4 + 1 + write-only + + + ACK_ERR_INT_CLR + clear ack error interrupt + 5 + 1 + write-only + + + RX_DATA_INT_CLR + clear receive data interrupt + 6 + 1 + write-only + + + TX_DATA_INT_CLR + clear transit load data complete interrupt + 7 + 1 + write-only + + + DETECT_START_INT_CLR + clear detect start interrupt + 8 + 1 + write-only + + + + + INT_RAW + interrupt raw register + 0x28 + 0x20 + + + SLAVE_TRAN_COMP_INT_RAW + slave transit complete interrupt raw + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + arbitration lost interrupt raw + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_RAW + master transit complete interrupt raw + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + transit complete interrupt raw + 3 + 1 + read-only + + + TIME_OUT_INT_RAW + time out interrupt raw + 4 + 1 + read-only + + + ACK_ERR_INT_RAW + ack error interrupt raw + 5 + 1 + read-only + + + RX_DATA_INT_RAW + receive data interrupt raw + 6 + 1 + read-only + + + TX_DATA_INT_RAW + transit data interrupt raw + 7 + 1 + read-only + + + DETECT_START_INT_RAW + detect start interrupt raw + 8 + 1 + read-only + + + + + INT_ST + interrupt state register + 0x2C + 0x20 + + + SLAVE_TRAN_COMP_INT_ST + slave transit complete interrupt state + 0 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + arbitration lost interrupt state + 1 + 1 + read-only + + + MASTER_TRAN_COMP_INT_ST + master transit complete interrupt state + 2 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + transit complete interrupt state + 3 + 1 + read-only + + + TIME_OUT_INT_ST + time out interrupt state + 4 + 1 + read-only + + + ACK_ERR_INT_ST + ack error interrupt state + 5 + 1 + read-only + + + RX_DATA_INT_ST + receive data interrupt state + 6 + 1 + read-only + + + TX_DATA_INT_ST + transit data interrupt state + 7 + 1 + read-only + + + DETECT_START_INT_ST + detect start interrupt state + 8 + 1 + read-only + + + + + INT_ENA + interrupt enable register + 0x30 + 0x20 + + + SLAVE_TRAN_COMP_INT_ENA + enable slave transit complete interrupt + 0 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + enable arbitration lost interrupt + 1 + 1 + read-write + + + MASTER_TRAN_COMP_INT_ENA + enable master transit complete interrupt + 2 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + enable transit complete interrupt + 3 + 1 + read-write + + + TIME_OUT_INT_ENA + enable time out interrupt + 4 + 1 + read-write + + + ACK_ERR_INT_ENA + enable eack error interrupt + 5 + 1 + read-write + + + RX_DATA_INT_ENA + enable receive data interrupt + 6 + 1 + read-write + + + TX_DATA_INT_ENA + enable transit data interrupt + 7 + 1 + read-write + + + DETECT_START_INT_ENA + enable detect start interrupt + 8 + 1 + read-write + + + + + DATA + get i2c data status + 0x34 + 0x20 + + + I2C_RDATA + data received + 0 + 8 + read-only + + + SLAVE_TX_DATA + data sent by slave + 8 + 8 + read-write + + + I2C_DONE + i2c done + 31 + 1 + read-only + + + + + CMD0 + i2c commond0 register + 0x38 + 0x20 + 0x00000903 + + + COMMAND0 + command0 + 0 + 14 + read-write + + + COMMAND0_DONE + command0_done + 31 + 1 + read-only + + + + + CMD1 + i2c commond1 register + 0x3C + 0x20 + 0x00001901 + + + COMMAND1 + command1 + 0 + 14 + read-write + + + COMMAND1_DONE + command1_done + 31 + 1 + read-only + + + + + CMD2 + i2c commond2 register + 0x40 + 0x20 + 0x00000902 + + + COMMAND2 + command2 + 0 + 14 + read-write + + + COMMAND2_DONE + command2_done + 31 + 1 + read-only + + + + + CMD3 + i2c commond3 register + 0x44 + 0x20 + 0x00000101 + + + COMMAND3 + command3 + 0 + 14 + read-write + + + COMMAND3_DONE + command3_done + 31 + 1 + read-only + + + + + CMD4 + i2c commond4 register + 0x48 + 0x20 + 0x00000901 + + + COMMAND4 + command4 + 0 + 14 + read-write + + + COMMAND4_DONE + command4_done + 31 + 1 + read-only + + + + + CMD5 + i2c commond5_register + 0x4C + 0x20 + 0x00001701 + + + COMMAND5 + command5 + 0 + 14 + read-write + + + COMMAND5_DONE + command5_done + 31 + 1 + read-only + + + + + CMD6 + i2c commond6 register + 0x50 + 0x20 + 0x00001901 + + + COMMAND6 + command6 + 0 + 14 + read-write + + + COMMAND6_DONE + command6_done + 31 + 1 + read-only + + + + + CMD7 + i2c commond7 register + 0x54 + 0x20 + 0x00000904 + + + COMMAND7 + command7 + 0 + 14 + read-write + + + COMMAND7_DONE + command7_done + 31 + 1 + read-only + + + + + CMD8 + i2c commond8 register + 0x58 + 0x20 + 0x00001901 + + + COMMAND8 + command8 + 0 + 14 + read-write + + + COMMAND8_DONE + command8_done + 31 + 1 + read-only + + + + + CMD9 + i2c commond9 register + 0x5C + 0x20 + 0x00000903 + + + COMMAND9 + command9 + 0 + 14 + read-write + + + COMMAND9_DONE + command9_done + 31 + 1 + read-only + + + + + CMD10 + i2c commond10 register + 0x60 + 0x20 + 0x00000101 + + + COMMAND10 + command10 + 0 + 14 + read-write + + + COMMAND10_DONE + command10_done + 31 + 1 + read-only + + + + + CMD11 + i2c commond11 register + 0x64 + 0x20 + 0x00000901 + + + COMMAND11 + command11 + 0 + 14 + read-write + + + COMMAND11_DONE + command11_done + 31 + 1 + read-only + + + + + CMD12 + i2c commond12 register + 0x68 + 0x20 + 0x00001701 + + + COMMAND12 + command12 + 0 + 14 + read-write + + + COMMAND12_DONE + command12_done + 31 + 1 + read-only + + + + + CMD13 + i2c commond13 register + 0x6C + 0x20 + 0x00001901 + + + COMMAND13 + command13 + 0 + 14 + read-write + + + COMMAND13_DONE + command13_done + 31 + 1 + read-only + + + + + CMD14 + i2c commond14 register + 0x70 + 0x20 + + + COMMAND14 + command14 + 0 + 14 + read-write + + + COMMAND14_DONE + command14_done + 31 + 1 + read-only + + + + + CMD15 + i2c commond15 register + 0x74 + 0x20 + + + COMMAND15 + command15 + 0 + 14 + read-write + + + COMMAND15_DONE + command15_done + 31 + 1 + read-only + + + + + DATE + version register + 0xFC + 0x20 + 0x01905310 + + + I2C_DATE + version + 0 + 28 + read-write + + + + + + + RTCIO + Peripheral RTC_IO + RTC_IO + 0x60008400 + + 0x0 + 0xF0 + registers + + + + RTC_GPIO_OUT + RTC GPIO 0 ~ 21 output data register + 0x0 + 0x20 + + + DATA + RTC GPIO 0 ~ 21 output data + 10 + 22 + read-write + + + + + RTC_GPIO_OUT_W1TS + one set RTC GPIO output data + 0x4 + 0x20 + + + RTC_GPIO_OUT_DATA_W1TS + RTC GPIO 0 ~ 21 output data write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_OUT_W1TC + one clear RTC GPIO output data + 0x8 + 0x20 + + + RTC_GPIO_OUT_DATA_W1TC + RTC GPIO 0 ~ 21 output data write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_ENABLE + Configure RTC GPIO output enable + 0xC + 0x20 + + + RTC_GPIO_ENABLE + RTC GPIO 0 ~ 21 enable + 10 + 22 + read-write + + + + + RTC_GPIO_ENABLE_W1TS + one set RTC GPIO output enable + 0x10 + 0x20 + + + RTC_GPIO_ENABLE_W1TS + RTC GPIO 0 ~ 21 enable write 1 to set + 10 + 22 + write-only + + + + + ENABLE_W1TC + one clear RTC GPIO output enable + 0x14 + 0x20 + + + ENABLE_W1TC + RTC GPIO 0 ~ 21 enable write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS + RTC GPIO 0 ~ 21 interrupt status + 0x18 + 0x20 + + + INT + RTC GPIO 0 ~ 21 interrupt status + 10 + 22 + read-write + + + + + RTC_GPIO_STATUS_W1TS + One set RTC GPIO 0 ~ 21 interrupt status + 0x1C + 0x20 + + + RTC_GPIO_STATUS_INT_W1TS + RTC GPIO 0 ~ 21 interrupt status write 1 to set + 10 + 22 + write-only + + + + + RTC_GPIO_STATUS_W1TC + One clear RTC GPIO 0 ~ 21 interrupt status + 0x20 + 0x20 + + + RTC_GPIO_STATUS_INT_W1TC + RTC GPIO 0 ~ 21 interrupt status write 1 to clear + 10 + 22 + write-only + + + + + RTC_GPIO_IN + RTC GPIO input data + 0x24 + 0x20 + + + NEXT + RTC GPIO input data + 10 + 22 + read-only + + + + + 22 + 0x4 + 0-21 + PIN%s + configure RTC GPIO%s + 0x28 + 0x20 + + + PAD_DRIVER + if set to 0: normal output, if set to 1: open drain + 2 + 1 + read-write + + + INT_TYPE + if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger + 7 + 3 + read-write + + + WAKEUP_ENABLE + RTC GPIO wakeup enable bit + 10 + 1 + read-write + + + + + RTC_DEBUG_SEL + configure rtc debug + 0x80 + 0x20 + + + RTC_DEBUG_SEL0 + configure rtc debug + 0 + 5 + read-write + + + RTC_DEBUG_SEL1 + configure rtc debug + 5 + 5 + read-write + + + RTC_DEBUG_SEL2 + configure rtc debug + 10 + 5 + read-write + + + RTC_DEBUG_SEL3 + configure rtc debug + 15 + 5 + read-write + + + RTC_DEBUG_SEL4 + configure rtc debug + 20 + 5 + read-write + + + RTC_DEBUG_12M_NO_GATING + configure rtc debug + 25 + 1 + read-write + + + + + TOUCH_PAD0 + configure RTC PAD0 + 0x84 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD1 + configure RTC PAD1 + 0x88 + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD2 + configure RTC PAD2 + 0x8C + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD3 + configure RTC PAD3 + 0x90 + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD4 + configure RTC PAD4 + 0x94 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD5 + configure RTC PAD5 + 0x98 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD6 + configure RTC PAD6 + 0x9C + 0x20 + 0x48000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD7 + configure RTC PAD7 + 0xA0 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD8 + configure RTC PAD8 + 0xA4 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD9 + configure RTC PAD9 + 0xA8 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD10 + configure RTC PAD10 + 0xAC + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD11 + configure RTC PAD11 + 0xB0 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD12 + configure RTC PAD12 + 0xB4 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD13 + configure RTC PAD13 + 0xB8 + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + TOUCH_PAD14 + configure RTC PAD14 + 0xBC + 0x20 + 0x40000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + XPD + TOUCH_XPD + 20 + 1 + read-write + + + TIE_OPT + TOUCH_TIE_OPT + 21 + 1 + read-write + + + START + TOUCH_START + 22 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32P_PAD + configure RTC PAD15 + 0xC0 + 0x20 + 0x40000000 + + + X32P_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + X32P_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32P_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32P_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32P_FUN_SEL + function sel + 17 + 2 + read-write + + + X32P_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32P_RUE + RUE + 27 + 1 + read-write + + + X32P_RDE + RDE + 28 + 1 + read-write + + + X32P_DRV + DRV + 29 + 2 + read-write + + + + + XTAL_32N_PAD + configure RTC PAD16 + 0xC4 + 0x20 + 0x40000000 + + + X32N_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + X32N_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + X32N_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + X32N_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + X32N_FUN_SEL + function sel + 17 + 2 + read-write + + + X32N_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + X32N_RUE + RUE + 27 + 1 + read-write + + + X32N_RDE + RDE + 28 + 1 + read-write + + + X32N_DRV + DRV + 29 + 2 + read-write + + + + + PAD_DAC1 + configure RTC PAD17 + 0xC8 + 0x20 + 0x40000000 + + + PDAC1_DAC + PDAC1_DAC + 3 + 8 + read-write + + + PDAC1_XPD_DAC + PDAC1_XPD_DAC + 11 + 1 + read-write + + + PDAC1_DAC_XPD_FORCE + 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC + 12 + 1 + read-write + + + PDAC1_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC1_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC1_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC1_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC1_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC1_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC1_RUE + PDAC1_RUE + 27 + 1 + read-write + + + PDAC1_RDE + PDAC1_RDE + 28 + 1 + read-write + + + PDAC1_DRV + PDAC1_DRV + 29 + 2 + read-write + + + + + PAD_DAC2 + configure RTC PAD18 + 0xCC + 0x20 + 0x40000000 + + + PDAC2_DAC + PDAC2_DAC + 3 + 8 + read-write + + + PDAC2_XPD_DAC + PDAC2_XPD_DAC + 11 + 1 + read-write + + + PDAC2_DAC_XPD_FORCE + 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC + 12 + 1 + read-write + + + PDAC2_FUN_IE + input enable in work mode + 13 + 1 + read-write + + + PDAC2_SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + PDAC2_SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + PDAC2_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + PDAC2_FUN_SEL + PDAC1 function sel + 17 + 2 + read-write + + + PDAC2_MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + PDAC2_RUE + PDAC2_RUE + 27 + 1 + read-write + + + PDAC2_RDE + PDAC2_RDE + 28 + 1 + read-write + + + PDAC2_DRV + PDAC2_DRV + 29 + 2 + read-write + + + + + RTC_PAD19 + configure RTC PAD19 + 0xD0 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + RTC_PAD20 + configure RTC PAD20 + 0xD4 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + RTC_PAD21 + configure RTC PAD21 + 0xD8 + 0x20 + 0x50000000 + + + FUN_IE + input enable in work mode + 13 + 1 + read-write + + + SLP_OE + output enable in sleep mode + 14 + 1 + read-write + + + SLP_IE + input enable in sleep mode + 15 + 1 + read-write + + + SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 16 + 1 + read-write + + + FUN_SEL + function sel + 17 + 2 + read-write + + + MUX_SEL + 1: use RTC GPIO,0: use digital GPIO + 19 + 1 + read-write + + + RUE + RUE + 27 + 1 + read-write + + + RDE + RDE + 28 + 1 + read-write + + + DRV + DRV + 29 + 2 + read-write + + + + + EXT_WAKEUP0 + configure EXT0 wakeup + 0xDC + 0x20 + + + SEL + ******* Description configure*** + 27 + 5 + read-write + + + + + XTL_EXT_CTR + configure gpio pd XTAL + 0xE0 + 0x20 + + + SEL + select RTC GPIO 0 ~ 17 to control XTAL + 27 + 5 + read-write + + + + + SAR_I2C_IO + configure rtc i2c mux + 0xE4 + 0x20 + + + SAR_DEBUG_BIT_SEL + ******* Description configure*** + 23 + 5 + read-write + + + SAR_I2C_SCL_SEL + ******* Description configure*** + 28 + 2 + read-write + + + SAR_I2C_SDA_SEL + ******* Description configure*** + 30 + 2 + read-write + + + + + TOUCH_CTRL + configure touch pad bufmode + 0xE8 + 0x20 + + + IO_TOUCH_BUFSEL + BUF_SEL when touch work without fsm + 0 + 4 + read-write + + + IO_TOUCH_BUFMODE + BUF_MODE when touch work without fsm + 4 + 1 + read-write + + + + + DATE + version + 0x1FC + 0x20 + 0x02101180 + + + DATE + version + 0 + 28 + read-write + + + + + + + SENS + Peripheral SENS + SENS + 0x60008800 + + 0x0 + 0x11C + registers + + + + SAR_READER1_CTRL + configure saradc1 reader + 0x0 + 0x20 + 0x20040002 + + + SAR_SAR1_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR_SAR1_CLK_GATED + no public + 18 + 1 + read-write + + + SAR_SAR1_SAMPLE_NUM + no public + 19 + 8 + read-write + + + SAR_SAR1_DATA_INV + Invert SAR ADC1 data + 28 + 1 + read-write + + + SAR_SAR1_INT_EN + enable saradc1 to send out interrupt + 29 + 1 + read-write + + + + + SAR_READER1_STATUS + get saradc1 reader controller status + 0x4 + 0x20 + + + SAR_SAR1_READER_STATUS + get saradc1 reader controller status + 0 + 32 + read-only + + + + + SAR_MEAS1_CTRL1 + no public + 0x8 + 0x20 + + + SAR_FORCE_XPD_AMP + no public + 24 + 2 + read-write + + + SAR_AMP_RST_FB_FORCE + no public + 26 + 2 + read-write + + + SAR_AMP_SHORT_REF_FORCE + no public + 28 + 2 + read-write + + + SAR_AMP_SHORT_REF_GND_FORCE + no public + 30 + 2 + read-write + + + + + SAR_MEAS1_CTRL2 + configure saradc1 controller + 0xC + 0x20 + + + SAR_MEAS1_DATA_SAR + SAR ADC1 data + 0 + 16 + read-only + + + SAR_MEAS1_DONE_SAR + SAR ADC1 conversion done indication + 16 + 1 + read-only + + + SAR_MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion + 17 + 1 + read-write + + + SAR_MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by SW + 18 + 1 + read-write + + + SAR_SAR1_EN_PAD + SAR ADC1 pad enable bitmap + 19 + 12 + read-write + + + SAR_SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by SW + 31 + 1 + read-write + + + + + SAR_MEAS1_MUX + configure saradc1 controller + 0x10 + 0x20 + + + SAR_SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL + 31 + 1 + read-write + + + + + SAR_ATTEN1 + configure saradc1 controller + 0x14 + 0x20 + 0xFFFFFFFF + + + SAR_SAR1_ATTEN + 2-bit attenuation for each pad + 0 + 32 + read-write + + + + + SAR_AMP_CTRL1 + no public + 0x18 + 0x20 + 0x000A000A + + + SAR_AMP_WAIT1 + no public + 0 + 16 + read-write + + + SAR_AMP_WAIT2 + no public + 16 + 16 + read-write + + + + + SAR_AMP_CTRL2 + no public + 0x1C + 0x20 + 0x000A0000 + + + SAR_SAR1_DAC_XPD_FSM_IDLE + no public + 0 + 1 + read-write + + + SAR_XPD_SAR_AMP_FSM_IDLE + no public + 1 + 1 + read-write + + + SAR_AMP_RST_FB_FSM_IDLE + no public + 2 + 1 + read-write + + + SAR_AMP_SHORT_REF_FSM_IDLE + no public + 3 + 1 + read-write + + + SAR_AMP_SHORT_REF_GND_FSM_IDLE + no public + 4 + 1 + read-write + + + SAR_XPD_SAR_FSM_IDLE + no public + 5 + 1 + read-write + + + SAR_RSTB_FSM_IDLE + no public + 6 + 1 + read-write + + + SAR_AMP_WAIT3 + no public + 16 + 16 + read-write + + + + + SAR_AMP_CTRL3 + no public + 0x20 + 0x20 + 0x007338F3 + + + SAR_SAR1_DAC_XPD_FSM + no public + 0 + 4 + read-write + + + SAR_XPD_SAR_AMP_FSM + no public + 4 + 4 + read-write + + + SAR_AMP_RST_FB_FSM + no public + 8 + 4 + read-write + + + SAR_AMP_SHORT_REF_FSM + no public + 12 + 4 + read-write + + + SAR_AMP_SHORT_REF_GND_FSM + no public + 16 + 4 + read-write + + + SAR_XPD_SAR_FSM + no public + 20 + 4 + read-write + + + SAR_RSTB_FSM + no public + 24 + 4 + read-write + + + + + SAR_READER2_CTRL + configure saradc2 reader + 0x24 + 0x20 + 0x40050002 + + + SAR_SAR2_CLK_DIV + clock divider + 0 + 8 + read-write + + + SAR_SAR2_WAIT_ARB_CYCLE + wait arbit stable after sar_done + 16 + 2 + read-write + + + SAR_SAR2_CLK_GATED + ******* Description *********** + 18 + 1 + read-write + + + SAR_SAR2_SAMPLE_NUM + ******* Description *********** + 19 + 8 + read-write + + + SAR_SAR2_DATA_INV + Invert SAR ADC2 data + 29 + 1 + read-write + + + SAR_SAR2_INT_EN + enable saradc2 to send out interrupt + 30 + 1 + read-write + + + + + SAR_READER2_STATUS + get saradc1 reader controller status + 0x28 + 0x20 + + + SAR_SAR2_READER_STATUS + get saradc1 reader controller status + 0 + 32 + read-only + + + + + SAR_MEAS2_CTRL1 + configure saradc2 controller + 0x2C + 0x20 + 0x07020200 + + + SAR_SAR2_CNTL_STATE + saradc2_cntl_fsm + 0 + 3 + read-only + + + SAR_SAR2_PWDET_CAL_EN + rtc control pwdet enable + 3 + 1 + read-write + + + SAR_SAR2_PKDET_CAL_EN + rtc control pkdet enable + 4 + 1 + read-write + + + SAR_SAR2_EN_TEST + SAR2_EN_TEST + 5 + 1 + read-write + + + SAR_SAR2_RSTB_FORCE + no public + 6 + 2 + read-write + + + SAR_SAR2_STANDBY_WAIT + no public + 8 + 8 + read-write + + + SAR_SAR2_RSTB_WAIT + no public + 16 + 8 + read-write + + + SAR_SAR2_XPD_WAIT + no public + 24 + 8 + read-write + + + + + SAR_MEAS2_CTRL2 + configure saradc2 controller + 0x30 + 0x20 + + + SAR_MEAS2_DATA_SAR + SAR ADC2 data + 0 + 16 + read-only + + + SAR_MEAS2_DONE_SAR + SAR ADC2 conversion done indication + 16 + 1 + read-only + + + SAR_MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion + 17 + 1 + read-write + + + SAR_MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by SW + 18 + 1 + read-write + + + SAR_SAR2_EN_PAD + SAR ADC2 pad enable bitmap + 19 + 12 + read-write + + + SAR_SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by SW + 31 + 1 + read-write + + + + + SAR_MEAS2_MUX + configure saradc2 controller + 0x34 + 0x20 + + + SAR_SAR2_PWDET_CCT + SAR2_PWDET_CCT + 28 + 3 + read-write + + + SAR_SAR2_RTC_FORCE + in sleep, force to use rtc to control ADC + 31 + 1 + read-write + + + + + SAR_ATTEN2 + configure saradc2 controller + 0x38 + 0x20 + 0xFFFFFFFF + + + SAR_SAR2_ATTEN + 2-bit attenuation for each pad + 0 + 32 + read-write + + + + + SAR_POWER_XPD_SAR + configure power of saradc + 0x3C + 0x20 + + + SAR_FORCE_XPD_SAR + force power on/off saradc + 29 + 2 + read-write + + + SAR_SARCLK_EN + no public + 31 + 1 + read-write + + + + + SAR_SLAVE_ADDR1 + configure i2c slave address + 0x40 + 0x20 + + + SAR_I2C_SLAVE_ADDR1 + configure i2c slave address1 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR0 + configure i2c slave address0 + 11 + 11 + read-write + + + SAR_SARADC_MEAS_STATUS + no public + 22 + 8 + read-only + + + + + SAR_SLAVE_ADDR2 + configure i2c slave address + 0x44 + 0x20 + + + SAR_I2C_SLAVE_ADDR3 + configure i2c slave address3 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR2 + configure i2c slave address2 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR3 + configure i2c slave address + 0x48 + 0x20 + + + SAR_I2C_SLAVE_ADDR5 + configure i2c slave address5 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR4 + configure i2c slave address4 + 11 + 11 + read-write + + + + + SAR_SLAVE_ADDR4 + configure i2c slave address + 0x4C + 0x20 + + + SAR_I2C_SLAVE_ADDR7 + configure i2c slave address7 + 0 + 11 + read-write + + + SAR_I2C_SLAVE_ADDR6 + configure i2c slave address6 + 11 + 11 + read-write + + + + + SAR_TSENS_CTRL + configure tsens controller + 0x50 + 0x20 + 0x00019000 + + + SAR_TSENS_OUT + temperature sensor data out + 0 + 8 + read-only + + + SAR_TSENS_READY + indicate temperature sensor out ready + 8 + 1 + read-only + + + SAR_TSENS_INT_EN + enable temperature sensor to send out interrupt + 12 + 1 + read-write + + + SAR_TSENS_IN_INV + invert temperature sensor data + 13 + 1 + read-write + + + SAR_TSENS_CLK_DIV + temperature sensor clock divider + 14 + 8 + read-write + + + SAR_TSENS_POWER_UP + temperature sensor power up + 22 + 1 + read-write + + + SAR_TSENS_POWER_UP_FORCE + 1: dump out & power up controlled by SW 0: by FSM + 23 + 1 + read-write + + + SAR_TSENS_DUMP_OUT + temperature sensor dump out only active when reg_tsens_power_up_force = 1 + 24 + 1 + read-write + + + + + SAR_TSENS_CTRL2 + configure tsens controller + 0x54 + 0x20 + 0x00004002 + + + SAR_TSENS_XPD_WAIT + no public + 0 + 12 + read-write + + + SAR_TSENS_XPD_FORCE + no public + 12 + 2 + read-write + + + SAR_TSENS_CLK_INV + no public + 14 + 1 + read-write + + + + + SAR_I2C_CTRL + configure rtc i2c controller by sw + 0x58 + 0x20 + + + SAR_I2C_CTRL + I2C control data only active when reg_sar_i2c_start_force = 1 + 0 + 28 + read-write + + + SAR_I2C_START + start I2C only active when reg_sar_i2c_start_force = 1 + 28 + 1 + read-write + + + SAR_I2C_START_FORCE + 1: I2C started by SW 0: I2C started by FSM + 29 + 1 + read-write + + + + + SAR_TOUCH_CONF + configure touch controller + 0x5C + 0x20 + 0xFFF07FFF + + + SAR_TOUCH_OUTEN + touch controller output enable + 0 + 15 + read-write + + + SAR_TOUCH_STATUS_CLR + clear all touch active status + 15 + 1 + write-only + + + SAR_TOUCH_DATA_SEL + 3: smooth data 2: baseline 1,0: raw_data + 16 + 2 + read-write + + + SAR_TOUCH_DENOISE_END + touch_denoise_done + 18 + 1 + read-only + + + SAR_TOUCH_UNIT_END + touch_unit_done + 19 + 1 + read-only + + + SAR_TOUCH_APPROACH_PAD2 + indicate which pad is approach pad2 + 20 + 4 + read-write + + + SAR_TOUCH_APPROACH_PAD1 + indicate which pad is approach pad1 + 24 + 4 + read-write + + + SAR_TOUCH_APPROACH_PAD0 + indicate which pad is approach pad0 + 28 + 4 + read-write + + + + + SAR_TOUCH_DENOISE + configure touch controller + 0x60 + 0x20 + + + DATA + configure touch controller + 0 + 22 + read-only + + + + + SAR_TOUCH_THRES1 + configure touch thres of touch pad + 0x64 + 0x20 + + + SAR_TOUCH_OUT_TH1 + Finger threshold for touch pad 1 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES2 + configure touch thres of touch pad + 0x68 + 0x20 + + + SAR_TOUCH_OUT_TH2 + Finger threshold for touch pad 2 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES3 + configure touch thres of touch pad + 0x6C + 0x20 + + + SAR_TOUCH_OUT_TH3 + Finger threshold for touch pad 3 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES4 + configure touch thres of touch pad + 0x70 + 0x20 + + + SAR_TOUCH_OUT_TH4 + Finger threshold for touch pad 4 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES5 + configure touch thres of touch pad + 0x74 + 0x20 + + + SAR_TOUCH_OUT_TH5 + Finger threshold for touch pad 5 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES6 + configure touch thres of touch pad + 0x78 + 0x20 + + + SAR_TOUCH_OUT_TH6 + Finger threshold for touch pad 6 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES7 + configure touch thres of touch pad + 0x7C + 0x20 + + + SAR_TOUCH_OUT_TH7 + Finger threshold for touch pad 7 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES8 + configure touch thres of touch pad + 0x80 + 0x20 + + + SAR_TOUCH_OUT_TH8 + Finger threshold for touch pad 8 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES9 + configure touch thres of touch pad + 0x84 + 0x20 + + + SAR_TOUCH_OUT_TH9 + Finger threshold for touch pad 9 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES10 + configure touch thres of touch pad + 0x88 + 0x20 + + + SAR_TOUCH_OUT_TH10 + Finger threshold for touch pad 10 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES11 + configure touch thres of touch pad + 0x8C + 0x20 + + + SAR_TOUCH_OUT_TH11 + Finger threshold for touch pad 11 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES12 + configure touch thres of touch pad + 0x90 + 0x20 + + + SAR_TOUCH_OUT_TH12 + Finger threshold for touch pad 12 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES13 + configure touch thres of touch pad + 0x94 + 0x20 + + + SAR_TOUCH_OUT_TH13 + Finger threshold for touch pad 13 + 0 + 22 + read-write + + + + + SAR_TOUCH_THRES14 + configure touch thres of touch pad + 0x98 + 0x20 + + + SAR_TOUCH_OUT_TH14 + Finger threshold for touch pad 14 + 0 + 22 + read-write + + + + + SAR_TOUCH_CHN_ST + Get touch channel status + 0x9C + 0x20 + + + SAR_TOUCH_PAD_ACTIVE + touch active status + 0 + 15 + read-only + + + SAR_TOUCH_CHANNEL_CLR + Clear touch channel + 15 + 15 + write-only + + + SAR_TOUCH_MEAS_DONE + get touch meas done + 31 + 1 + read-only + + + + + SAR_TOUCH_STATUS0 + get touch scan status + 0xA0 + 0x20 + + + SAR_TOUCH_SCAN_CURR + current sample channel + 22 + 4 + read-only + + + + + SAR_TOUCH_STATUS1 + touch channel status of touch pad 1 + 0xA4 + 0x20 + + + SAR_TOUCH_PAD1_DATA + touch data debounce of touch pad 1 + 0 + 22 + read-only + + + SAR_TOUCH_PAD1_DEBOUNCE + touch current debounce of touch pad 1 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS2 + touch channel status of touch pad 2 + 0xA8 + 0x20 + + + SAR_TOUCH_PAD2_DATA + touch data debounce of touch pad 2 + 0 + 22 + read-only + + + SAR_TOUCH_PAD2_DEBOUNCE + touch current debounce of touch pad 2 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS3 + touch channel status of touch pad 3 + 0xAC + 0x20 + + + SAR_TOUCH_PAD3_DATA + touch data debounce of touch pad 3 + 0 + 22 + read-only + + + SAR_TOUCH_PAD3_DEBOUNCE + touch current debounce of touch pad 3 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS4 + touch channel status of touch pad 4 + 0xB0 + 0x20 + + + SAR_TOUCH_PAD4_DATA + touch data debounce of touch pad 4 + 0 + 22 + read-only + + + SAR_TOUCH_PAD4_DEBOUNCE + touch current debounce of touch pad 4 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS5 + touch channel status of touch pad 5 + 0xB4 + 0x20 + + + SAR_TOUCH_PAD5_DATA + touch data debounce of touch pad 5 + 0 + 22 + read-only + + + SAR_TOUCH_PAD5_DEBOUNCE + touch current debounce of touch pad 5 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS6 + touch channel status of touch pad 6 + 0xB8 + 0x20 + + + SAR_TOUCH_PAD6_DATA + touch data debounce of touch pad 6 + 0 + 22 + read-only + + + SAR_TOUCH_PAD6_DEBOUNCE + touch current debounce of touch pad 6 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS7 + touch channel status of touch pad 7 + 0xBC + 0x20 + + + SAR_TOUCH_PAD7_DATA + touch data debounce of touch pad 7 + 0 + 22 + read-only + + + SAR_TOUCH_PAD7_DEBOUNCE + touch current debounce of touch pad 7 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS8 + touch channel status of touch pad 8 + 0xC0 + 0x20 + + + SAR_TOUCH_PAD8_DATA + touch data debounce of touch pad 8 + 0 + 22 + read-only + + + SAR_TOUCH_PAD8_DEBOUNCE + touch current debounce of touch pad 8 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS9 + touch channel status of touch pad 9 + 0xC4 + 0x20 + + + SAR_TOUCH_PAD9_DATA + touch data debounce of touch pad 9 + 0 + 22 + read-only + + + SAR_TOUCH_PAD9_DEBOUNCE + touch current debounce of touch pad 9 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS10 + touch channel status of touch pad 10 + 0xC8 + 0x20 + + + SAR_TOUCH_PAD10_DATA + touch data debounce of touch pad 10 + 0 + 22 + read-only + + + SAR_TOUCH_PAD10_DEBOUNCE + touch current debounce of touch pad 10 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS11 + touch channel status of touch pad 11 + 0xCC + 0x20 + + + SAR_TOUCH_PAD11_DATA + touch data debounce of touch pad 11 + 0 + 22 + read-only + + + SAR_TOUCH_PAD11_DEBOUNCE + touch current debounce of touch pad 11 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS12 + touch channel status of touch pad 12 + 0xD0 + 0x20 + + + SAR_TOUCH_PAD12_DATA + touch data debounce of touch pad 12 + 0 + 22 + read-only + + + SAR_TOUCH_PAD12_DEBOUNCE + touch current debounce of touch pad 12 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS13 + touch channel status of touch pad 13 + 0xD4 + 0x20 + + + SAR_TOUCH_PAD13_DATA + touch data debounce of touch pad 13 + 0 + 22 + read-only + + + SAR_TOUCH_PAD13_DEBOUNCE + touch current debounce of touch pad 13 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS14 + touch channel status of touch pad 14 + 0xD8 + 0x20 + + + SAR_TOUCH_PAD14_DATA + touch data debounce of touch pad 14 + 0 + 22 + read-only + + + SAR_TOUCH_PAD14_DEBOUNCE + touch current debounce of touch pad 14 + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS15 + touch channel status of sleep pad + 0xDC + 0x20 + + + SAR_TOUCH_SLP_DATA + touch data debounce of sleep pad + 0 + 22 + read-only + + + SAR_TOUCH_SLP_DEBOUNCE + touch current debounce of sleep pad + 29 + 3 + read-only + + + + + SAR_TOUCH_STATUS16 + touch channel status of approach mode + 0xE0 + 0x20 + + + SAR_TOUCH_APPROACH_PAD2_CNT + touch current approach count of approach pad2 + 0 + 8 + read-only + + + SAR_TOUCH_APPROACH_PAD1_CNT + touch current approach count of approach pad1 + 8 + 8 + read-only + + + SAR_TOUCH_APPROACH_PAD0_CNT + touch current approach count of approach pad0 + 16 + 8 + read-only + + + SAR_TOUCH_SLP_APPROACH_CNT + touch current approach count of slp pad + 24 + 8 + read-only + + + + + SAR_COCPU_STATE + get cocpu status + 0xE4 + 0x20 + + + SAR_COCPU_DBG_TRIGGER + trigger cocpu debug registers + 25 + 1 + write-only + + + SAR_COCPU_CLK_EN_ST + check cocpu whether clk on + 26 + 1 + read-only + + + SAR_COCPU_RESET_N + check cocpu whether in reset state + 27 + 1 + read-only + + + SAR_COCPU_EOI + check cocpu whether in interrupt state + 28 + 1 + read-only + + + SAR_COCPU_TRAP + check cocpu whether in trap state + 29 + 1 + read-only + + + SAR_COCPU_EBREAK + check cocpu whether in ebreak + 30 + 1 + read-only + + + + + SAR_COCPU_INT_RAW + the interrupt raw of ulp + 0xE8 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_RAW + int from touch done + 0 + 1 + read-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_RAW + int from touch inactive + 1 + 1 + read-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_RAW + int from touch active + 2 + 1 + read-only + + + SAR_COCPU_SARADC1_INT_RAW + int from saradc1 + 3 + 1 + read-only + + + SAR_COCPU_SARADC2_INT_RAW + int from saradc2 + 4 + 1 + read-only + + + SAR_COCPU_TSENS_INT_RAW + int from tsens + 5 + 1 + read-only + + + SAR_COCPU_START_INT_RAW + int from start + 6 + 1 + read-only + + + SAR_COCPU_SW_INT_RAW + int from software + 7 + 1 + read-only + + + SAR_COCPU_SWD_INT_RAW + int from super watch dog + 8 + 1 + read-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_RAW + int from timeout done + 9 + 1 + read-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW + int from approach loop done + 10 + 1 + read-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW + int from touch scan done + 11 + 1 + read-only + + + + + SAR_COCPU_INT_ENA + the interrupt enable of ulp + 0xEC + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA + int enable of touch done + 0 + 1 + read-write + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA + int enable of from touch inactive + 1 + 1 + read-write + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA + int enable of touch active + 2 + 1 + read-write + + + SAR_COCPU_SARADC1_INT_ENA + int enable of from saradc1 + 3 + 1 + read-write + + + SAR_COCPU_SARADC2_INT_ENA + int enable of from saradc2 + 4 + 1 + read-write + + + SAR_COCPU_TSENS_INT_ENA + int enable of tsens + 5 + 1 + read-write + + + SAR_COCPU_START_INT_ENA + int enable of start + 6 + 1 + read-write + + + SAR_COCPU_SW_INT_ENA + int enable of software + 7 + 1 + read-write + + + SAR_COCPU_SWD_INT_ENA + int enable of super watch dog + 8 + 1 + read-write + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA + int enable of timeout done + 9 + 1 + read-write + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA + int enable of approach loop done + 10 + 1 + read-write + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA + int enable of touch scan done + 11 + 1 + read-write + + + + + SAR_COCPU_INT_ST + the interrupt state of ulp + 0xF0 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ST + int state of touch done + 0 + 1 + read-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ST + int state of from touch inactive + 1 + 1 + read-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ST + int state of touch active + 2 + 1 + read-only + + + SAR_COCPU_SARADC1_INT_ST + int state of from saradc1 + 3 + 1 + read-only + + + SAR_COCPU_SARADC2_INT_ST + int state of from saradc2 + 4 + 1 + read-only + + + SAR_COCPU_TSENS_INT_ST + int state of tsens + 5 + 1 + read-only + + + SAR_COCPU_START_INT_ST + int state of start + 6 + 1 + read-only + + + SAR_COCPU_SW_INT_ST + int state of software + 7 + 1 + read-only + + + SAR_COCPU_SWD_INT_ST + int state of super watch dog + 8 + 1 + read-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ST + int state of timeout done + 9 + 1 + read-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST + int state of approach loop done + 10 + 1 + read-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ST + int state of touch scan done + 11 + 1 + read-only + + + + + SAR_COCPU_INT_CLR + the interrupt clear of ulp + 0xF4 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_CLR + int clear of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_CLR + int clear of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_CLR + int clear of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_CLR + int clear of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_CLR + int clear of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_CLR + int clear of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_CLR + int clear of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_CLR + int clear of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_CLR + int clear of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_CLR + int clear of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR + int clear of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR + int clear of touch scan done + 11 + 1 + write-only + + + + + SAR_COCPU_DEBUG + Ulp-riscv debug signal + 0xF8 + 0x20 + + + SAR_COCPU_PC + cocpu Program counter + 0 + 13 + read-only + + + SAR_COCPU_MEM_VLD + cocpu mem valid output + 13 + 1 + read-only + + + SAR_COCPU_MEM_RDY + cocpu mem ready input + 14 + 1 + read-only + + + SAR_COCPU_MEM_WEN + cocpu mem write enable output + 15 + 4 + read-only + + + SAR_COCPU_MEM_ADDR + cocpu mem address output + 19 + 13 + read-only + + + + + SAR_HALL_CTRL + no public + 0xFC + 0x20 + 0xA0000000 + + + SAR_XPD_HALL + Power on hall sensor and connect to VP and VN + 28 + 1 + read-write + + + SAR_XPD_HALL_FORCE + 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor + 29 + 1 + read-write + + + SAR_HALL_PHASE + Reverse phase of hall sensor + 30 + 1 + read-write + + + SAR_HALL_PHASE_FORCE + 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor + 31 + 1 + read-write + + + + + SAR_NOUSE + no public + 0x100 + 0x20 + + + SAR_NOUSE + no public + 0 + 32 + read-write + + + + + SAR_PERI_CLK_GATE_CONF + the peri clock gate of rtc peri + 0x104 + 0x20 + + + SAR_RTC_I2C_CLK_EN + enable rtc i2c clock + 27 + 1 + read-write + + + SAR_TSENS_CLK_EN + enable tsens clock + 29 + 1 + read-write + + + SAR_SARADC_CLK_EN + enbale saradc clock + 30 + 1 + read-write + + + SAR_IOMUX_CLK_EN + enable io_mux clock + 31 + 1 + read-write + + + + + SAR_PERI_RESET_CONF + the peri reset of rtc peri + 0x108 + 0x20 + + + SAR_COCPU_RESET + enable ulp-riscv reset + 25 + 1 + read-write + + + SAR_RTC_I2C_RESET + Reserved. + 27 + 1 + read-write + + + SAR_TSENS_RESET + enbale saradc reset + 29 + 1 + read-write + + + SAR_SARADC_RESET + enable io_mux reset + 30 + 1 + read-write + + + + + SAR_COCPU_INT_ENA_W1TS + the interrupt enable of ulp + 0x10C + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS + int enable of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS + int enable of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS + int enable of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_ENA_W1TS + int enable of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_ENA_W1TS + int enable of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_ENA_W1TS + int enable of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_ENA_W1TS + int enable of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_ENA_W1TS + int enable of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_ENA_W1TS + int enable of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS + int enable of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + int enable of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS + int enable of touch scan done + 11 + 1 + write-only + + + + + SAR_COCPU_INT_ENA_W1TC + the interrupt enable clear of ulp + 0x110 + 0x20 + + + SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC + Clear int enable of touch done + 0 + 1 + write-only + + + SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC + Clear int enable of from touch inactive + 1 + 1 + write-only + + + SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC + Clear int enable of touch active + 2 + 1 + write-only + + + SAR_COCPU_SARADC1_INT_ENA_W1TC + Clear int enable of from saradc1 + 3 + 1 + write-only + + + SAR_COCPU_SARADC2_INT_ENA_W1TC + Clear int enable of from saradc2 + 4 + 1 + write-only + + + SAR_COCPU_TSENS_INT_ENA_W1TC + Clear int enable of tsens + 5 + 1 + write-only + + + SAR_COCPU_START_INT_ENA_W1TC + Clear int enable of start + 6 + 1 + write-only + + + SAR_COCPU_SW_INT_ENA_W1TC + Clear int enable of software + 7 + 1 + write-only + + + SAR_COCPU_SWD_INT_ENA_W1TC + Clear int enable of super watch dog + 8 + 1 + write-only + + + SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC + Clear int enable of timeout done + 9 + 1 + write-only + + + SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + Clear int enable of approach loop done + 10 + 1 + write-only + + + SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC + Clear int enable of touch scan done + 11 + 1 + write-only + + + + + SAR_DEBUG_CONF + rtc peri debug configure + 0x114 + 0x20 + + + SAR_DEBUG_BIT_SEL + no public + 0 + 5 + read-write + + + + + SAR_SARDATE + version + 0x1FC + 0x20 + 0x02101180 + + + SAR_DATE + version + 0 + 28 + read-write + + + + + + + SENSITIVE + Peripheral SENSITIVE + SENSITIVE + 0x600C1000 + + 0x0 + 0x314 + registers + + + + CACHE_DATAARRAY_CONNECT_0 + Cache data array configuration register 0. + 0x0 + 0x20 + + + CACHE_DATAARRAY_CONNECT_LOCK + Set 1 to lock cache data array registers. + 0 + 1 + read-write + + + + + CACHE_DATAARRAY_CONNECT_1 + Cache data array configuration register 1. + 0x4 + 0x20 + 0x000000FF + + + CACHE_DATAARRAY_CONNECT_FLATTEN + Cache data array connection configuration. + 0 + 8 + read-write + + + + + APB_PERIPHERAL_ACCESS_0 + APB peripheral configuration register 0. + 0x8 + 0x20 + + + APB_PERIPHERAL_ACCESS_LOCK + Set 1 to lock APB peripheral Configuration Register. + 0 + 1 + read-write + + + + + APB_PERIPHERAL_ACCESS_1 + APB peripheral configuration register 1. + 0xC + 0x20 + 0x00000001 + + + APB_PERIPHERAL_ACCESS_SPLIT_BURST + Set 1 to support split function for AHB access to APB peripherals. + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_0 + Internal SRAM configuration register 0. + 0x10 + 0x20 + + + INTERNAL_SRAM_USAGE_LOCK + Set 1 to lock internal SRAM Configuration Register. + 0 + 1 + read-write + + + + + INTERNAL_SRAM_USAGE_1 + Internal SRAM configuration register 1. + 0x14 + 0x20 + 0x000007FF + + + INTERNAL_SRAM_ICACHE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache. + 0 + 2 + read-write + + + INTERNAL_SRAM_DCACHE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by dcache. + 2 + 2 + read-write + + + INTERNAL_SRAM_CPU_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by cpu. + 4 + 7 + read-write + + + + + INTERNAL_SRAM_USAGE_2 + Internal SRAM configuration register 2. + 0x18 + 0x20 + + + INTERNAL_SRAM_CORE0_TRACE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus. + 0 + 7 + read-write + + + INTERNAL_SRAM_CORE1_TRACE_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus. + 7 + 7 + read-write + + + INTERNAL_SRAM_CORE0_TRACE_ALLOC + Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus. + 14 + 2 + read-write + + + INTERNAL_SRAM_CORE1_TRACE_ALLOC + Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus. + 16 + 2 + read-write + + + + + INTERNAL_SRAM_USAGE_3 + Internal SRAM configuration register 3. + 0x1C + 0x20 + + + INTERNAL_SRAM_MAC_DUMP_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump. + 0 + 4 + read-write + + + + + INTERNAL_SRAM_USAGE_4 + Internal SRAM configuration register 4. + 0x20 + 0x20 + + + INTERNAL_SRAM_LOG_USAGE + Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus. + 0 + 7 + read-write + + + + + RETENTION_DISABLE + Retention configuration register. + 0x24 + 0x20 + + + RETENTION_DISABLE + Set 1 to disable retention function and lock disable state. + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_0 + Cache tag configuration register 0. + 0x28 + 0x20 + + + CACHE_TAG_ACCESS_LOCK + Set 1 to lock cache tag Configuration Register. + 0 + 1 + read-write + + + + + CACHE_TAG_ACCESS_1 + Cache tag configuration register 1. + 0x2C + 0x20 + 0x0000000F + + + PRO_I_TAG_RD_ACS + Set 1 to enable Icache read access tag memory. + 0 + 1 + read-write + + + PRO_I_TAG_WR_ACS + Set 1 to enable Icache wrtie access tag memory. + 1 + 1 + read-write + + + PRO_D_TAG_RD_ACS + Set 1 to enable Dcache read access tag memory. + 2 + 1 + read-write + + + PRO_D_TAG_WR_ACS + Set 1 to enable Dcache wrtie access tag memory. + 3 + 1 + read-write + + + + + CACHE_MMU_ACCESS_0 + Cache MMU configuration register 0. + 0x30 + 0x20 + + + CACHE_MMU_ACCESS_LOCK + Set 1 to lock cache MMU registers. + 0 + 1 + read-write + + + + + CACHE_MMU_ACCESS_1 + Cache MMU configuration register 1. + 0x34 + 0x20 + 0x00000003 + + + PRO_MMU_RD_ACS + Set 1 to enable read access MMU memory. + 0 + 1 + read-write + + + PRO_MMU_WR_ACS + Set 1 to enable write access MMU memory. + 1 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 + spi2 dma permission configuration register 0. + 0x38 + 0x20 + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK + Set 1 to lock spi2 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 + spi2 dma permission configuration register 1. + 0x3C + 0x20 + 0x00000FFF + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 + spi2's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 + spi2's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 + spi2's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 + spi2's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + spi2's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + spi2's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_0 + spi3 dma permission configuration register 0. + 0x40 + 0x20 + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK + Set 1 to lock spi3 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_1 + spi3 dma permission configuration register 1. + 0x44 + 0x20 + 0x00000FFF + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 + spi3's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 + spi3's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 + spi3's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 + spi3's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + spi3's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + spi3's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0 + uhci0 dma permission configuration register 0. + 0x48 + 0x20 + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK + Set 1 to lock uhci0 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1 + uhci0 dma permission configuration register 1. + 0x4C + 0x20 + 0x00000FFF + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 + uhci0's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 + uhci0's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 + uhci0's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 + uhci0's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + uhci0's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + uhci0's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 + i2s0 dma permission configuration register 0. + 0x50 + 0x20 + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK + Set 1 to lock i2s0 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 + i2s0 dma permission configuration register 1. + 0x54 + 0x20 + 0x00000FFF + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 + i2s0's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 + i2s0's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 + i2s0's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 + i2s0's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + i2s0's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + i2s0's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_0 + i2s1 dma permission configuration register 0. + 0x58 + 0x20 + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK + Set 1 to lock i2s1 dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_1 + i2s1 dma permission configuration register 1. + 0x5C + 0x20 + 0x00000FFF + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 + i2s1's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 + i2s1's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 + i2s1's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 + i2s1's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + i2s1's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + i2s1's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_0 + mac dma permission configuration register 0. + 0x60 + 0x20 + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK + Set 1 to lock mac dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_1 + mac dma permission configuration register 1. + 0x64 + 0x20 + 0x00000FFF + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 + mac's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 + mac's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 + mac's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 + mac's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + mac's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + mac's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 + backup dma permission configuration register 0. + 0x68 + 0x20 + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK + Set 1 to lock backup dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 + backup dma permission configuration register 1. + 0x6C + 0x20 + 0x00000FFF + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 + backup's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 + backup's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 + backup's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 + backup's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + backup's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + backup's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_0 + aes dma permission configuration register 0. + 0x70 + 0x20 + + + DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK + Set 1 to lock aes dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_AES_PMS_CONSTRAIN_1 + aes dma permission configuration register 1. + 0x74 + 0x20 + 0x00000FFF + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 + aes's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 + aes's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 + aes's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 + aes's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + aes's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + aes's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_0 + sha dma permission configuration register 0. + 0x78 + 0x20 + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK + Set 1 to lock sha dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_1 + sha dma permission configuration register 1. + 0x7C + 0x20 + 0x00000FFF + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 + sha's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 + sha's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 + sha's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 + sha's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + sha's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + sha's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 + adc_dac dma permission configuration register 0. + 0x80 + 0x20 + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK + Set 1 to lock adc_dac dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 + adc_dac dma permission configuration register 1. + 0x84 + 0x20 + 0x00000FFF + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 + adc_dac's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 + adc_dac's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 + adc_dac's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 + adc_dac's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + adc_dac's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + adc_dac's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_0 + rmt dma permission configuration register 0. + 0x88 + 0x20 + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK + Set 1 to lock rmt dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_1 + rmt dma permission configuration register 1. + 0x8C + 0x20 + 0x00000FFF + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 + rmt's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 + rmt's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 + rmt's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 + rmt's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + rmt's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + rmt's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0 + lcd_cam dma permission configuration register 0. + 0x90 + 0x20 + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK + Set 1 to lock lcd_cam dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1 + lcd_cam dma permission configuration register 1. + 0x94 + 0x20 + 0x00000FFF + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 + lcd_cam's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 + lcd_cam's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 + lcd_cam's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 + lcd_cam's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + lcd_cam's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + lcd_cam's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_USB_PMS_CONSTRAIN_0 + usb dma permission configuration register 0. + 0x98 + 0x20 + + + DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK + Set 1 to lock usb dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_USB_PMS_CONSTRAIN_1 + usb dma permission configuration register 1. + 0x9C + 0x20 + 0x00000FFF + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 + usb's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 + usb's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 + usb's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 + usb's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + usb's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + usb's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_LC_PMS_CONSTRAIN_0 + lc dma permission configuration register 0. + 0xA0 + 0x20 + + + DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK + Set 1 to lock lc dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_LC_PMS_CONSTRAIN_1 + lc dma permission configuration register 1. + 0xA4 + 0x20 + 0x00000FFF + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 + lc's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 + lc's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 + lc's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 + lc's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + lc's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + lc's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_0 + sdio dma permission configuration register 0. + 0xA8 + 0x20 + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK + Set 1 to lock sdio dma permission Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_1 + sdio dma permission configuration register 1. + 0xAC + 0x20 + 0x00000FFF + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 + sdio's permission(store,load) in data region0 of SRAM + 0 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 + sdio's permission(store,load) in data region1 of SRAM + 2 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 + sdio's permission(store,load) in data region2 of SRAM + 4 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 + sdio's permission(store,load) in data region3 of SRAM + 6 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + sdio's permission(store,load) in dcache data sram block0 + 8 + 2 + read-write + + + DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + sdio's permission(store,load) in dcache data sram block1 + 10 + 2 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_0 + dma permission monitor configuration register 0. + 0xB0 + 0x20 + + + DMA_APBPERI_PMS_MONITOR_LOCK + Set 1 to lock dma permission monitor Configuration Register. + 0 + 1 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_1 + dma permission monitor configuration register 1. + 0xB4 + 0x20 + 0x00000003 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear dma_pms_monitor_violate interrupt + 0 + 1 + read-write + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_EN + Set 1 to enable dma pms monitor, if dma access violated permission, will trigger interrupt. + 1 + 1 + read-write + + + + + DMA_APBPERI_PMS_MONITOR_2 + dma permission monitor configuration register 2. + 0xB8 + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR + recorded dma's interrupt status when dma access violated permission + 0 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded dma's world status when dma access violated permission + 1 + 2 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded dma's address bit[25:4] status when dma access violated permission, real address is 0x3c00_0000+addr*16 + 3 + 22 + read-only + + + + + DMA_APBPERI_PMS_MONITOR_3 + dma permission monitor configuration register 3. + 0xBC + 0x20 + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR + recorded dma's write status when dma access violated permission, 1(write), 0(read) + 0 + 1 + read-only + + + DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded dma's byte enable status when dma access violated permission + 1 + 16 + read-only + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 + sram split line configuration register 0 + 0xC0 + 0x20 + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK + Set 1 to lock sram split configuration register + 0 + 1 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 + sram split line configuration register 1 + 0xC4 + 0x20 + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 + sram split line configuration register 1 + 0xC8 + 0x20 + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 + sram split line configuration register 1 + 0xCC + 0x20 + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 + sram split line configuration register 1 + 0xD0 + 0x20 + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 + sram split line configuration register 1 + 0xD4 + 0x20 + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 + category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00 + 0 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 + category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00 + 2 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 + category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00 + 4 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 + category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00 + 6 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 + category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00 + 8 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 + category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00 + 10 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 + category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00 + 12 + 2 + read-write + + + CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR + splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address + 14 + 8 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_0 + corex iram0 permission configuration register 0 + 0xD8 + 0x20 + + + CORE_X_IRAM0_PMS_CONSTRAIN_LOCK + Set 1 to lock corex iram0 permission configuration register + 0 + 1 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_1 + corex iram0 permission configuration register 0 + 0xDC + 0x20 + 0x001FFFFF + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core0/core1's permission of instruction region0 of SRAM in world1 + 0 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core0/core1's permission of instruction region1 of SRAM in world1 + 3 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core0/core1's permission of instruction region2 of SRAM in world1 + 6 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core0/core1's permission of instruction region3 of SRAM in world1 + 9 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core0/core1's permission of icache data sram block0 in world1 + 12 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + core0/core1's permission of icache data sram block1 in world1 + 15 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core0/core1's permission of rom in world1 + 18 + 3 + read-write + + + + + CORE_X_IRAM0_PMS_CONSTRAIN_2 + corex iram0 permission configuration register 1 + 0xE0 + 0x20 + 0x001FFFFF + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core0/core1's permission of instruction region0 of SRAM in world1 + 0 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core0/core1's permission of instruction region1 of SRAM in world1 + 3 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core0/core1's permission of instruction region2 of SRAM in world1 + 6 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core0/core1's permission of instruction region3 of SRAM in world1 + 9 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core0/core1's permission of icache data sram block0 in world1 + 12 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + core0/core1's permission of icache data sram block1 in world1 + 15 + 3 + read-write + + + CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core0/core1's permission of rom in world1 + 18 + 3 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_0 + core0 iram0 permission monitor configuration register 0 + 0xE4 + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_LOCK + Set 1 to lock core0 iram0 permission monitor register + 0 + 1 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_1 + core0 iram0 permission monitor configuration register 1 + 0xE8 + 0x20 + 0x00000003 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core0 iram0 permission violated interrupt + 0 + 1 + read-write + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt + 1 + 1 + read-write + + + + + CORE_0_IRAM0_PMS_MONITOR_2 + core0 iram0 permission monitor configuration register 2 + 0xEC + 0x20 + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core0 iram0 pms monitor interrupt status. + 0 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + 1 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + 2 + 1 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1. + 3 + 2 + read-only + + + CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core0 iram0 address [25:2] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4 + 5 + 24 + read-only + + + + + CORE_1_IRAM0_PMS_MONITOR_0 + core1 iram0 permission monitor configuration register 0 + 0xF0 + 0x20 + + + CORE_1_IRAM0_PMS_MONITOR_LOCK + Set 1 to lock core1 iram0 permission monitor register + 0 + 1 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_1 + core1 iram0 permission monitor configuration register 1 + 0xF4 + 0x20 + 0x00000003 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core1 iram0 permission violated interrupt + 0 + 1 + read-write + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt + 1 + 1 + read-write + + + + + CORE_1_IRAM0_PMS_MONITOR_2 + core1 iram0 permission monitor configuration register 2 + 0xF8 + 0x20 + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core1 iram0 pms monitor interrupt status. + 0 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load). + 1 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store). + 2 + 1 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1. + 3 + 2 + read-only + + + CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core1 iram0 address [25:2] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4 + 5 + 24 + read-only + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_0 + corex dram0 permission configuration register 0 + 0xFC + 0x20 + + + CORE_X_DRAM0_PMS_CONSTRAIN_LOCK + Set 1 to lock corex dram0 permission configuration register + 0 + 1 + read-write + + + + + CORE_X_DRAM0_PMS_CONSTRAIN_1 + corex dram0 permission configuration register 1 + 0x100 + 0x20 + 0x0FFFFFFF + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + core0/core1's permission of data region0 of SRAM in world0. + 0 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + core0/core1's permission of data region1 of SRAM in world0. + 2 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + core0/core1's permission of data region2 of SRAM in world0. + 4 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + core0/core1's permission of data region3 of SRAM in world0. + 6 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + core0/core1's permission of dcache data sram block0 in world0. + 8 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + core0/core1's permission of dcache data sram block1 in world0. + 10 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + core0/core1's permission of data region0 of SRAM in world1. + 12 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + core0/core1's permission of data region1 of SRAM in world1. + 14 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + core0/core1's permission of data region2 of SRAM in world1. + 16 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + core0/core1's permission of data region3 of SRAM in world1. + 18 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + core0/core1's permission of dcache data sram block0 in world1. + 20 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + core0/core1's permission of dcache data sram block1 in world1. + 22 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + core0/core1's permission(sotre,load) of rom in world0. + 24 + 2 + read-write + + + CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + core0/core1's permission(sotre,load) of rom in world1. + 26 + 2 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_0 + core0 dram0 permission monitor configuration register 0 + 0x104 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_LOCK + Set 1 to lock core0 dram0 permission monitor configuration register. + 0 + 1 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_1 + core0 dram0 permission monitor configuration register 1 + 0x108 + 0x20 + 0x00000003 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core0 dram0 permission monior interrupt. + 0 + 1 + read-write + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core0 dram0 permission monitor interrupt. + 1 + 1 + read-write + + + + + CORE_0_DRAM0_PMS_MONITOR_2 + core0 dram0 permission monitor configuration register 2. + 0x10C + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core0 dram0 permission monitor interrupt status. + 0 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + recorded core0 dram0 lock status, 1 means s32c1i access. + 1 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1. + 2 + 2 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core0 dram0 address[25:4] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16 + 4 + 22 + read-only + + + + + CORE_0_DRAM0_PMS_MONITOR_3 + core0 dram0 permission monitor configuration register 3. + 0x110 + 0x20 + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core0 dram0 wr status, 1 means store, 0 means load. + 0 + 1 + read-only + + + CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded core0 dram0 byteen status. + 1 + 16 + read-only + + + + + CORE_1_DRAM0_PMS_MONITOR_0 + core1 dram0 permission monitor configuration register 0 + 0x114 + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_LOCK + Set 1 to lock core1 dram0 permission monitor configuration register. + 0 + 1 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_1 + core1 dram0 permission monitor configuration register 1 + 0x118 + 0x20 + 0x00000003 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear core1 dram0 permission monior interrupt. + 0 + 1 + read-write + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN + Set 1 to enable core1 dram0 permission monitor interrupt. + 1 + 1 + read-write + + + + + CORE_1_DRAM0_PMS_MONITOR_2 + core1 dram0 permission monitor configuration register 2. + 0x11C + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR + recorded core1 dram0 permission monitor interrupt status. + 0 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + recorded core1 dram0 lock status, 1 means s32c1i access. + 1 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1. + 2 + 2 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + recorded core1 dram0 address[25:4] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16 + 4 + 22 + read-only + + + + + CORE_1_DRAM0_PMS_MONITOR_3 + core1 dram0 permission monitor configuration register 3. + 0x120 + 0x20 + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + recorded core1 dram0 wr status, 1 means store, 0 means load. + 0 + 1 + read-only + + + CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + recorded core1 dram0 byteen status. + 1 + 16 + read-only + + + + + CORE_0_PIF_PMS_CONSTRAIN_0 + Core0 access peripherals permission configuration register 0. + 0x124 + 0x20 + + + CORE_0_PIF_PMS_CONSTRAIN_LOCK + Set 1 to lock core0 access peripherals permission Configuration Register. + 0 + 1 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_1 + Core0 access peripherals permission configuration register 1. + 0x128 + 0x20 + 0xFF33CFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART + Core0 access uart permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + Core0 access g0spi_1 permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + Core0 access g0spi_0 permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + Core0 access gpio permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + Core0 access fe2 permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE + Core0 access fe permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC + Core0 access rtc permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + Core0 access io_mux permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF + Core0 access hinf permission in world0. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC + Core0 access misc permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C + Core0 access i2c permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + Core0 access i2s0 permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + Core0 access uart1 permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_2 + Core0 access peripherals permission configuration register 2. + 0x12C + 0x20 + 0xFFCFFFF3 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT + Core0 access bt permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + Core0 access i2c_ext0 permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + Core0 access uhci0 permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + Core0 access slchost permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT + Core0 access rmt permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + Core0 access pcnt permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC + Core0 access slc permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + Core0 access ledc permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + Core0 access backup permission in world0. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB + Core0 access bb permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + Core0 access pwm0 permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + Core0 access timergroup permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + Core0 access timergroup1 permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + Core0 access systimer permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_3 + Core0 access peripherals permission configuration register 3. + 0x130 + 0x20 + 0x3CC3FFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + Core0 access spi_2 permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + Core0 access spi_3 permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + Core0 access apb_ctrl permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + Core0 access i2c_ext1 permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + Core0 access sdio_host permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN + Core0 access can permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + Core0 access pwm1 permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + Core0 access i2s1 permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + Core0 access uart2 permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + Core0 access rwbt permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + Core0 access wifimac permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR + Core0 access pwr permission in world0. + 28 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_4 + Core0 access peripherals permission configuration register 4. + 0x134 + 0x20 + 0xFFFFFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + Core0 access usb_device permission in world0. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + Core0 access usb_wrap permission in world0. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + Core0 access crypto_peri permission in world0. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + Core0 access crypto_dma permission in world0. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + Core0 access apb_adc permission in world0. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + Core0 access lcd_cam permission in world0. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + Core0 access bt_pwr permission in world0. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB + Core0 access usb permission in world0. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + Core0 access system permission in world0. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + Core0 access sensitive permission in world0. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + Core0 access interrupt permission in world0. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + Core0 access dma_copy permission in world0. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + Core0 access cache_config permission in world0. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD + Core0 access ad permission in world0. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO + Core0 access dio permission in world0. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + Core0 access world_controller permission in world0. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_5 + Core0 access peripherals permission configuration register 5. + 0x138 + 0x20 + 0xFF33CFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART + Core0 access uart permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + Core0 access g0spi_1 permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + Core0 access g0spi_0 permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + Core0 access gpio permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + Core0 access fe2 permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE + Core0 access fe permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC + Core0 access rtc permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + Core0 access io_mux permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF + Core0 access hinf permission in world1. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC + Core0 access misc permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C + Core0 access i2c permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + Core0 access i2s0 permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + Core0 access uart1 permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_6 + Core0 access peripherals permission configuration register 6. + 0x13C + 0x20 + 0xFFCFFFF3 + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT + Core0 access bt permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + Core0 access i2c_ext0 permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + Core0 access uhci0 permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + Core0 access slchost permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT + Core0 access rmt permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + Core0 access pcnt permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC + Core0 access slc permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + Core0 access ledc permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + Core0 access backup permission in world1. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB + Core0 access bb permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + Core0 access pwm0 permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + Core0 access timergroup permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + Core0 access timergroup1 permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + Core0 access systimer permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_7 + Core0 access peripherals permission configuration register 7. + 0x140 + 0x20 + 0x3CC3FFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + Core0 access spi_2 permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + Core0 access spi_3 permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + Core0 access apb_ctrl permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + Core0 access i2c_ext1 permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + Core0 access sdio_host permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN + Core0 access can permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + Core0 access pwm1 permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + Core0 access i2s1 permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + Core0 access uart2 permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + Core0 access rwbt permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + Core0 access wifimac permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR + Core0 access pwr permission in world1. + 28 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_8 + Core0 access peripherals permission configuration register 8. + 0x144 + 0x20 + 0xFFFFFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + Core0 access usb_device permission in world1. + 0 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + Core0 access usb_wrap permission in world1. + 2 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + Core0 access crypto_peri permission in world1. + 4 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + Core0 access crypto_dma permission in world1. + 6 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + Core0 access apb_adc permission in world1. + 8 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + Core0 access lcd_cam permission in world1. + 10 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + Core0 access bt_pwr permission in world1. + 12 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB + Core0 access usb permission in world1. + 14 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + Core0 access system permission in world1. + 16 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + Core0 access sensitive permission in world1. + 18 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + Core0 access interrupt permission in world1. + 20 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + Core0 access dma_copy permission in world1. + 22 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + Core0 access cache_config permission in world1. + 24 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD + Core0 access ad permission in world1. + 26 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO + Core0 access dio permission in world1. + 28 + 2 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + Core0 access world_controller permission in world1. + 30 + 2 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_9 + Core0 access peripherals permission configuration register 9. + 0x148 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + RTCFast memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + RTCFast memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_10 + Core0 access peripherals permission configuration register 10. + 0x14C + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + RTCFast memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + RTCFast memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + RTCFast memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + RTCFast memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_11 + Core0 access peripherals permission configuration register 11. + 0x150 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + RTCSlow_0 memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + RTCSlow_0 memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_12 + Core0 access peripherals permission configuration register 12. + 0x154 + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + RTCSlow_0 memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + RTCSlow_0 memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + RTCSlow_0 memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + RTCSlow_0 memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_13 + Core0 access peripherals permission configuration register 13. + 0x158 + 0x20 + 0x003FFFFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + RTCSlow_1 memory split address in world 0 for core0. + 0 + 11 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + RTCSlow_1 memory split address in world 1 for core0. + 11 + 11 + read-write + + + + + CORE_0_PIF_PMS_CONSTRAIN_14 + Core0 access peripherals permission configuration register 14. + 0x15C + 0x20 + 0x00000FFF + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + RTCSlow_1 memory low region permission in world 0 for core0. + 0 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + RTCSlow_1 memory high region permission in world 0 for core0. + 3 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + RTCSlow_1 memory low region permission in world 1 for core0. + 6 + 3 + read-write + + + CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + RTCSlow_1 memory high region permission in world 1 for core0. + 9 + 3 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_0 + Core0 region permission register 0. + 0x160 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_LOCK + Set 1 to lock core0 region permission registers. + 0 + 1 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_1 + Core0 region permission register 1. + 0x164 + 0x20 + 0x003FFFFF + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + Region 0 permission in world 0 for core0. + 0 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + Region 1 permission in world 0 for core0. + 2 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + Region 2 permission in world 0 for core0. + 4 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + Region 3 permission in world 0 for core0. + 6 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + Region 4 permission in world 0 for core0. + 8 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + Region 5 permission in world 0 for core0. + 10 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + Region 6 permission in world 0 for core0. + 12 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + Region 7 permission in world 0 for core0. + 14 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + Region 8 permission in world 0 for core0. + 16 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + Region 9 permission in world 0 for core0. + 18 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + Region 10 permission in world 0 for core0. + 20 + 2 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_2 + Core0 region permission register 2. + 0x168 + 0x20 + 0x003FFFFF + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + Region 0 permission in world 1 for core0. + 0 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + Region 1 permission in world 1 for core0. + 2 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + Region 2 permission in world 1 for core0. + 4 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + Region 3 permission in world 1 for core0. + 6 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + Region 4 permission in world 1 for core0. + 8 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + Region 5 permission in world 1 for core0. + 10 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + Region 6 permission in world 1 for core0. + 12 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + Region 7 permission in world 1 for core0. + 14 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + Region 8 permission in world 1 for core0. + 16 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + Region 9 permission in world 1 for core0. + 18 + 2 + read-write + + + CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + Region 10 permission in world 1 for core0. + 20 + 2 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_3 + Core0 region permission register 3. + 0x16C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 + Region 0 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_4 + Core0 region permission register 4. + 0x170 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 + Region 0 end address and Region 1 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_5 + Core0 region permission register 5. + 0x174 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 + Region 1 end address and Region 2 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_6 + Core0 region permission register 6. + 0x178 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 + Region 2 end address and Region 3 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_7 + Core0 region permission register 7. + 0x17C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 + Region 3 end address and Region 4 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_8 + Core0 region permission register 8. + 0x180 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 + Region 4 end address and Region 5 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_9 + Core0 region permission register 9. + 0x184 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 + Region 5 end address and Region 6 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_10 + Core0 region permission register 10. + 0x188 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 + Region 6 end address and Region 7 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_11 + Core0 region permission register 11. + 0x18C + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 + Region 7 end address and Region 8 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_12 + Core0 region permission register 12. + 0x190 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 + Region 8 end address and Region 9 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_13 + Core0 region permission register 13. + 0x194 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 + Region 9 end address and Region 10 start address for core0. + 0 + 30 + read-write + + + + + CORE_0_REGION_PMS_CONSTRAIN_14 + Core0 region permission register 14. + 0x198 + 0x20 + + + CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 + Region 10 end address for core0. + 0 + 30 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_0 + Core0 permission report register 0. + 0x19C + 0x20 + + + CORE_0_PIF_PMS_MONITOR_LOCK + Set 1 to lock core0 permission report registers. + 0 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_1 + Core0 permission report register 1. + 0x1A0 + 0x20 + 0x00000003 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that core0 initiate illegal PIF bus access. + 0 + 1 + read-write + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that core0 initiate illegal PIF bus access. + 1 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_2 + Core0 permission report register 2. + 0x1A4 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR + Record core0 illegal access interrupt state. + 0 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + Record hport information when core0 initiate illegal access. + 1 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when core0 initate illegal access. + 2 + 3 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when core0 initiate illegal access. + 5 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + Record world information when core0 initiate illegal access. + 6 + 2 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_3 + Core0 permission report register 3. + 0x1A8 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + Record address information when core0 initiate illegal access. + 0 + 32 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_4 + Core0 permission report register 4. + 0x1AC + 0x20 + 0x00000003 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + Set 1 to clear interrupt that core0 initiate unsupported access type. + 0 + 1 + read-write + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + Set 1 to enable interrupt that core0 initiate unsupported access type. + 1 + 1 + read-write + + + + + CORE_0_PIF_PMS_MONITOR_5 + Core0 permission report register 5. + 0x1B0 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + Record core0 unsupported access type interrupt state. + 0 + 1 + read-only + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Record access type when core0 initiate unsupported access type. + 1 + 2 + read-only + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + Record world information when core0 initiate unsupported access type. + 3 + 2 + read-only + + + + + CORE_0_PIF_PMS_MONITOR_6 + Core0 permission report register 6. + 0x1B4 + 0x20 + + + CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Record address information when core0 initiate unsupported access type. + 0 + 32 + read-only + + + + + CORE_0_VECBASE_OVERRIDE_LOCK + core0 vecbase override configuration register 0 + 0x1B8 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_LOCK + Set 1 to lock core0 vecbase configuration register + 0 + 1 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_0 + core0 vecbase override configuration register 0 + 0x1BC + 0x20 + 0x00000001 + + + CORE_0_VECBASE_WORLD_MASK + Set 1 to mask world, then only world0_value will work. + 0 + 1 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_1 + core0 vecbase override configuration register 1 + 0x1C0 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE + world0 vecbase_override register, when core0 in world0 use this register to override vecbase register. + 0 + 22 + read-write + + + CORE_0_VECBASE_OVERRIDE_SEL + Set 0x3 to sel vecbase_override to override vecbase register. + 22 + 2 + read-write + + + + + CORE_0_VECBASE_OVERRIDE_2 + core0 vecbase override configuration register 1 + 0x1C4 + 0x20 + + + CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE + world1 vecbase_override register, when core0 in world1 use this register to override vecbase register. + 0 + 22 + read-write + + + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + core0 toomanyexception override configuration register 0. + 0x1C8 + 0x20 + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + Set 1 to lock core0 toomanyexception override configuration register + 0 + 1 + read-write + + + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + core0 toomanyexception override configuration register 1. + 0x1CC + 0x20 + 0x00000001 + + + CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE + Set 1 to mask toomanyexception. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_0 + Core1 access peripherals permission configuration register 0. + 0x1D0 + 0x20 + + + CORE_1_PIF_PMS_CONSTRAIN_LOCK + Set 1 to lock core1 pif permission configuration register. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_1 + Core1 access peripherals permission configuration register 1. + 0x1D4 + 0x20 + 0xFF33CFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART + Core1 access uart permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + Core1 access g0spi_1 permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + Core1 access g0spi_0 permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + Core1 access gpio permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + Core1 access fe2 permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE + Core1 access fe permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC + Core1 access rtc permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + Core1 access io_mux permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF + Core1 access hinf permission in world0. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC + Core1 access misc permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C + Core1 access i2c permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + Core1 access i2s0 permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + Core1 access uart1 permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_2 + Core1 access peripherals permission configuration register 2. + 0x1D8 + 0x20 + 0xFFCFFFF3 + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT + Core1 access bt permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + Core1 access i2c_ext0 permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + Core1 access uhci0 permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + Core1 access slchost permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT + Core1 access rmt permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + Core1 access pcnt permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC + Core1 access slc permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + Core1 access ledc permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + Core1 access backup permission in world0. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB + Core1 access bb permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + Core1 access pwm0 permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + Core1 access timergroup permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + Core1 access timergroup1 permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + Core1 access systimer permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_3 + Core1 access peripherals permission configuration register 3. + 0x1DC + 0x20 + 0x3CC3FFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + Core1 access spi_2 permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + Core1 access spi_3 permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + Core1 access apb_ctrl permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + Core1 access i2c_ext1 permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + Core1 access sdio_host permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN + Core1 access can permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + Core1 access pwm1 permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + Core1 access i2s1 permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + Core1 access uart2 permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + Core1 access rwbt permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + Core1 access wifimac permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR + Core1 access pwr permission in world0. + 28 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_4 + Core1 access peripherals permission configuration register 4. + 0x1E0 + 0x20 + 0xFFFFFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + Core1 access usb_device permission in world0. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + Core1 access usb_wrap permission in world0. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + Core1 access crypto_peri permission in world0. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + Core1 access crypto_dma permission in world0. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + Core1 access apb_adc permission in world0. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + Core1 access lcd_cam permission in world0. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + Core1 access bt_pwr permission in world0. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB + Core1 access usb permission in world0. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + Core1 access system permission in world0. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + Core1 access sensitive permission in world0. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + Core1 access interrupt permission in world0. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + Core1 access dma_copy permission in world0. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + Core1 access cache_config permission in world0. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD + Core1 access ad permission in world0. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO + Core1 access dio permission in world0. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + Core1 access world_controller permission in world0. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_5 + Core1 access peripherals permission configuration register 5. + 0x1E4 + 0x20 + 0xFF33CFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART + Core1 access uart permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + Core1 access g0spi_1 permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + Core1 access g0spi_0 permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + Core1 access gpio permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + Core1 access fe2 permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE + Core1 access fe permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC + Core1 access rtc permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + Core1 access io_mux permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF + Core1 access hinf permission in world1. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC + Core1 access misc permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C + Core1 access i2c permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + Core1 access i2s0 permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + Core1 access uart1 permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_6 + Core1 access peripherals permission configuration register 6. + 0x1E8 + 0x20 + 0xFFCFFFF3 + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT + Core1 access bt permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + Core1 access i2c_ext0 permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + Core1 access uhci0 permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + Core1 access slchost permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT + Core1 access rmt permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + Core1 access pcnt permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC + Core1 access slc permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + Core1 access ledc permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + Core1 access backup permission in world1. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB + Core1 access bb permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + Core1 access pwm0 permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + Core1 access timergroup permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + Core1 access timergroup1 permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + Core1 access systimer permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_7 + Core1 access peripherals permission configuration register 7. + 0x1EC + 0x20 + 0x3CC3FFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + Core1 access spi_2 permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + Core1 access spi_3 permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + Core1 access apb_ctrl permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + Core1 access i2c_ext1 permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + Core1 access sdio_host permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN + Core1 access can permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + Core1 access pwm1 permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + Core1 access i2s1 permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + Core1 access uart2 permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + Core1 access rwbt permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + Core1 access wifimac permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR + Core1 access pwr permission in world1. + 28 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_8 + Core1 access peripherals permission configuration register 8. + 0x1F0 + 0x20 + 0xFFFFFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + Core1 access usb_device permission in world1. + 0 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + Core1 access usb_wrap permission in world1. + 2 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + Core1 access crypto_peri permission in world1. + 4 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + Core1 access crypto_dma permission in world1. + 6 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + Core1 access apb_adc permission in world1. + 8 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + Core1 access lcd_cam permission in world1. + 10 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + Core1 access bt_pwr permission in world1. + 12 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB + Core1 access usb permission in world1. + 14 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + Core1 access system permission in world1. + 16 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + Core1 access sensitive permission in world1. + 18 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + Core1 access interrupt permission in world1. + 20 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + Core1 access dma_copy permission in world1. + 22 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + Core1 access cache_config permission in world1. + 24 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD + Core1 access ad permission in world1. + 26 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO + Core1 access dio permission in world1. + 28 + 2 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + Core1 access world_controller permission in world1. + 30 + 2 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_9 + Core1 access peripherals permission configuration register 9. + 0x1F4 + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + RTCFast memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + RTCFast memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_10 + core1 access peripherals permission configuration register 10. + 0x1F8 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + RTCFast memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + RTCFast memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + RTCFast memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + RTCFast memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_11 + core1 access peripherals permission configuration register 11. + 0x1FC + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + RTCSlow_0 memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + RTCSlow_0 memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_12 + core1 access peripherals permission configuration register 12. + 0x200 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + RTCSlow_0 memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + RTCSlow_0 memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + RTCSlow_0 memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + RTCSlow_0 memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_13 + core1 access peripherals permission configuration register 13. + 0x204 + 0x20 + 0x003FFFFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + RTCSlow_1 memory split address in world 0 for core1. + 0 + 11 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + RTCSlow_1 memory split address in world 1 for core1. + 11 + 11 + read-write + + + + + CORE_1_PIF_PMS_CONSTRAIN_14 + core1 access peripherals permission configuration register 14. + 0x208 + 0x20 + 0x00000FFF + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + RTCSlow_1 memory low region permission in world 0 for core1. + 0 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + RTCSlow_1 memory high region permission in world 0 for core1. + 3 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + RTCSlow_1 memory low region permission in world 1 for core1. + 6 + 3 + read-write + + + CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + RTCSlow_1 memory high region permission in world 1 for core1. + 9 + 3 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_0 + core1 region permission register 0. + 0x20C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_LOCK + Set 1 to lock core1 region permission registers. + 0 + 1 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_1 + core1 region permission register 1. + 0x210 + 0x20 + 0x003FFFFF + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + Region 0 permission in world 0 for core1. + 0 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + Region 1 permission in world 0 for core1. + 2 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + Region 2 permission in world 0 for core1. + 4 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + Region 3 permission in world 0 for core1. + 6 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + Region 4 permission in world 0 for core1. + 8 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + Region 5 permission in world 0 for core1. + 10 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + Region 6 permission in world 0 for core1. + 12 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + Region 7 permission in world 0 for core1. + 14 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + Region 8 permission in world 0 for core1. + 16 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + Region 9 permission in world 0 for core1. + 18 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + Region 10 permission in world 0 for core1. + 20 + 2 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_2 + core1 region permission register 2. + 0x214 + 0x20 + 0x003FFFFF + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + Region 0 permission in world 1 for core1. + 0 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + Region 1 permission in world 1 for core1. + 2 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + Region 2 permission in world 1 for core1. + 4 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + Region 3 permission in world 1 for core1. + 6 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + Region 4 permission in world 1 for core1. + 8 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + Region 5 permission in world 1 for core1. + 10 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + Region 6 permission in world 1 for core1. + 12 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + Region 7 permission in world 1 for core1. + 14 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + Region 8 permission in world 1 for core1. + 16 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + Region 9 permission in world 1 for core1. + 18 + 2 + read-write + + + CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + Region 10 permission in world 1 for core1. + 20 + 2 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_3 + core1 region permission register 3. + 0x218 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 + Region 0 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_4 + core1 region permission register 4. + 0x21C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 + Region 0 end address and Region 1 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_5 + core1 region permission register 5. + 0x220 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 + Region 1 end address and Region 2 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_6 + core1 region permission register 6. + 0x224 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 + Region 2 end address and Region 3 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_7 + core1 region permission register 7. + 0x228 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 + Region 3 end address and Region 4 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_8 + core1 region permission register 8. + 0x22C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 + Region 4 end address and Region 5 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_9 + core1 region permission register 9. + 0x230 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 + Region 5 end address and Region 6 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_10 + core1 region permission register 10. + 0x234 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 + Region 6 end address and Region 7 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_11 + core1 region permission register 11. + 0x238 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 + Region 7 end address and Region 8 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_12 + core1 region permission register 12. + 0x23C + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 + Region 8 end address and Region 9 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_13 + core1 region permission register 13. + 0x240 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 + Region 9 end address and Region 10 start address for core1. + 0 + 30 + read-write + + + + + CORE_1_REGION_PMS_CONSTRAIN_14 + core1 region permission register 14. + 0x244 + 0x20 + + + CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 + Region 10 end address for core1. + 0 + 30 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_0 + core1 permission report register 0. + 0x248 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_LOCK + Set 1 to lock core1 permission report registers. + 0 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_1 + core1 permission report register 1. + 0x24C + 0x20 + 0x00000003 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that core1 initiate illegal PIF bus access. + 0 + 1 + read-write + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that core1 initiate illegal PIF bus access. + 1 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_2 + core1 permission report register 2. + 0x250 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR + Record core1 illegal access interrupt state. + 0 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + Record hport information when core1 initiate illegal access. + 1 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when core1 initate illegal access. + 2 + 3 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when core1 initiate illegal access. + 5 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + Record world information when core1 initiate illegal access. + 6 + 2 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_3 + core1 permission report register 3. + 0x254 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + Record address information when core1 initiate illegal access. + 0 + 32 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_4 + core1 permission report register 4. + 0x258 + 0x20 + 0x00000003 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + Set 1 to clear interrupt that core1 initiate unsupported access type. + 0 + 1 + read-write + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + Set 1 to enable interrupt that core1 initiate unsupported access type. + 1 + 1 + read-write + + + + + CORE_1_PIF_PMS_MONITOR_5 + core1 permission report register 5. + 0x25C + 0x20 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + Record core1 unsupported access type interrupt state. + 0 + 1 + read-only + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + Record access type when core1 initiate unsupported access type. + 1 + 2 + read-only + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + Record world information when core1 initiate unsupported access type. + 3 + 2 + read-only + + + + + CORE_1_PIF_PMS_MONITOR_6 + core1 permission report register 6. + 0x260 + 0x20 + + + CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + Record address information when core1 initiate unsupported access type. + 0 + 32 + read-only + + + + + CORE_1_VECBASE_OVERRIDE_LOCK + core1 vecbase override configuration register 0 + 0x264 + 0x20 + + + CORE_1_VECBASE_OVERRIDE_LOCK + Set 1 to lock core1 vecbase configuration register + 0 + 1 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_0 + core1 vecbase override configuration register 0 + 0x268 + 0x20 + 0x00000001 + + + CORE_1_VECBASE_WORLD_MASK + Set 1 to mask world, then only world0_value will work. + 0 + 1 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_1 + core1 vecbase override configuration register 1 + 0x26C + 0x20 + + + CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE + world0 vecbase_override register, when core1 in world0 use this register to override vecbase register. + 0 + 22 + read-write + + + CORE_1_VECBASE_OVERRIDE_SEL + Set 0x3 to sel vecbase_override to override vecbase register. + 22 + 2 + read-write + + + + + CORE_1_VECBASE_OVERRIDE_2 + core1 vecbase override configuration register 1 + 0x270 + 0x20 + + + CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE + world1 vecbase_override register, when core1 in world1 use this register to override vecbase register. + 0 + 22 + read-write + + + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + core1 toomanyexception override configuration register 0. + 0x274 + 0x20 + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + Set 1 to lock core1 toomanyexception override configuration register + 0 + 1 + read-write + + + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + core1 toomanyexception override configuration register 1. + 0x278 + 0x20 + 0x00000001 + + + CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE + Set 1 to mask toomanyexception. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_0 + BackUp access peripherals permission configuration register 0. + 0x27C + 0x20 + + + BACKUP_BUS_PMS_CONSTRAIN_LOCK + Set 1 to lock BackUp permission configuration registers. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_1 + BackUp access peripherals permission configuration register 1. + 0x280 + 0x20 + 0xFF33CFFF + + + BACKUP_BUS_PMS_CONSTRAIN_UART + BackUp access uart permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 + BackUp access g0spi_1 permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 + BackUp access g0spi_0 permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_GPIO + BackUp access gpio permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE2 + BackUp access fe2 permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_FE + BackUp access fe permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTC + BackUp access rtc permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_IO_MUX + BackUp access io_mux permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_HINF + BackUp access hinf permission. + 20 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_MISC + BackUp access misc permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C + BackUp access i2c permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S0 + BackUp access i2s0 permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART1 + BackUp access uart1 permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_2 + BackUp access peripherals permission configuration register 2. + 0x284 + 0x20 + 0xFFCFFFF3 + + + BACKUP_BUS_PMS_CONSTRAIN_BT + BackUp access bt permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 + BackUp access i2c_ext0 permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UHCI0 + BackUp access uhci0 permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SLCHOST + BackUp access slchost permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RMT + BackUp access rmt permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PCNT + BackUp access pcnt permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SLC + BackUp access slc permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LEDC + BackUp access ledc permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BACKUP + BackUp access backup permission. + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BB + BackUp access bb permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWM0 + BackUp access pwm0 permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP + BackUp access timergroup permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 + BackUp access timergroup1 permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER + BackUp access systimer permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_3 + BackUp access peripherals permission configuration register 3. + 0x288 + 0x20 + 0x3CC3FFFF + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_2 + BackUp access spi_2 permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SPI_3 + BackUp access spi_3 permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL + BackUp access apb_ctrl permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 + BackUp access i2c_ext1 permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST + BackUp access sdio_host permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CAN + BackUp access can permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWM1 + BackUp access pwm1 permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_I2S1 + BackUp access i2s1 permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_UART2 + BackUp access uart2 permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RWBT + BackUp access rwbt permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC + BackUp access wifimac permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_PWR + BackUp access pwr permission. + 28 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_4 + BackUp access peripherals permission configuration register 4. + 0x28C + 0x20 + 0xFFFFFFFF + + + BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE + BackUp access usb_device permission. + 0 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP + BackUp access usb_wrap permission. + 2 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI + BackUp access crypto_peri permission. + 4 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA + BackUp access crypto_dma permission. + 6 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_APB_ADC + BackUp access apb_adc permission. + 8 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM + BackUp access lcd_cam permission. + 10 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_BT_PWR + BackUp access bt_pwr permission. + 12 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_USB + BackUp access usb permission. + 14 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SYSTEM + BackUp access system permission. + 16 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE + BackUp access sensitive permission. + 18 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT + BackUp access interrupt permission. + 20 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY + BackUp access dma_copy permission. + 22 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG + BackUp access cache_config permission. + 24 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_AD + BackUp access ad permission. + 26 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_DIO + BackUp access dio permission. + 28 + 2 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER + BackUp access world_controller permission. + 30 + 2 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_5 + BackUp access peripherals permission configuration register 5. + 0x290 + 0x20 + 0x000007FF + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR + BackUp access rtcfast_spltaddr permission. + 0 + 11 + read-write + + + + + BACKUP_BUS_PMS_CONSTRAIN_6 + BackUp access peripherals permission configuration register 6. + 0x294 + 0x20 + 0x0000003F + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L + BackUp access rtcfast_l permission. + 0 + 3 + read-write + + + BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H + BackUp access rtcfast_h permission. + 3 + 3 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_0 + BackUp permission report register 0. + 0x298 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_LOCK + Set 1 to lock BackUp permission report registers. + 0 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_1 + BackUp permission report register 1. + 0x29C + 0x20 + 0x00000003 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR + Set 1 to clear interrupt that BackUp initiate illegal access. + 0 + 1 + read-write + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_EN + Set 1 to enable interrupt that BackUp initiate illegal access. + 1 + 1 + read-write + + + + + BACKUP_BUS_PMS_MONITOR_2 + BackUp permission report register 2. + 0x2A0 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR + Record BackUp illegal access interrupt state. + 0 + 1 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS + Record htrans when BackUp initate illegal access. + 1 + 2 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE + Record access type when BackUp initate illegal access. + 3 + 3 + read-only + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE + Record access direction when BackUp initiate illegal access. + 6 + 1 + read-only + + + + + BACKUP_BUS_PMS_MONITOR_3 + BackUp permission report register 3. + 0x2A4 + 0x20 + + + BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR + Record address information when BackUp initiate illegal access. + 0 + 32 + read-only + + + + + EDMA_BOUNDARY_LOCK + EDMA boundary lock register. + 0x2A8 + 0x20 + + + EDMA_BOUNDARY_LOCK + Set 1 to lock EDMA boundary registers. + 0 + 1 + read-write + + + + + EDMA_BOUNDARY_0 + EDMA boundary 0 configuration + 0x2AC + 0x20 + + + EDMA_BOUNDARY_0 + This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_BOUNDARY_1 + EDMA boundary 1 configuration + 0x2B0 + 0x20 + 0x00002000 + + + EDMA_BOUNDARY_1 + This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_BOUNDARY_2 + EDMA boundary 2 configuration + 0x2B4 + 0x20 + 0x00002000 + + + EDMA_BOUNDARY_2 + This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + 0 + 14 + read-write + + + + + EDMA_PMS_SPI2_LOCK + EDMA-SPI2 permission lock register. + 0x2B8 + 0x20 + + + EDMA_PMS_SPI2_LOCK + Set 1 to lock EDMA-SPI2 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SPI2 + EDMA-SPI2 permission control register. + 0x2BC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_SPI3_LOCK + EDMA-SPI3 permission lock register. + 0x2C0 + 0x20 + + + EDMA_PMS_SPI3_LOCK + Set 1 to lock EDMA-SPI3 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SPI3 + EDMA-SPI3 permission control register. + 0x2C4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_UHCI0_LOCK + EDMA-UHCI0 permission lock register. + 0x2C8 + 0x20 + + + EDMA_PMS_UHCI0_LOCK + Set 1 to lock EDMA-UHCI0 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_UHCI0 + EDMA-UHCI0 permission control register. + 0x2CC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_I2S0_LOCK + EDMA-I2S0 permission lock register. + 0x2D0 + 0x20 + + + EDMA_PMS_I2S0_LOCK + Set 1 to lock EDMA-I2S0 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_I2S0 + EDMA-I2S0 permission control register. + 0x2D4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_I2S1_LOCK + EDMA-I2S1 permission lock register. + 0x2D8 + 0x20 + + + EDMA_PMS_I2S1_LOCK + Set 1 to lock EDMA-I2S1 permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_I2S1 + EDMA-I2S1 permission control register. + 0x2DC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_LCD_CAM_LOCK + EDMA-LCD/CAM permission lock register. + 0x2E0 + 0x20 + + + EDMA_PMS_LCD_CAM_LOCK + Set 1 to lock EDMA-LCD/CAM permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_LCD_CAM + EDMA-LCD/CAM permission control register. + 0x2E4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_AES_LOCK + EDMA-AES permission lock register. + 0x2E8 + 0x20 + + + EDMA_PMS_AES_LOCK + Set 1 to lock EDMA-AES permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_AES + EDMA-AES permission control register. + 0x2EC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of AES accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_SHA_LOCK + EDMA-SHA permission lock register. + 0x2F0 + 0x20 + + + EDMA_PMS_SHA_LOCK + Set 1 to lock EDMA-SHA permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_SHA + EDMA-SHA permission control register. + 0x2F4 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of SHA accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_ADC_DAC_LOCK + EDMA-ADC/DAC permission lock register. + 0x2F8 + 0x20 + + + EDMA_PMS_ADC_DAC_LOCK + Set 1 to lock EDMA-ADC/DAC permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_ADC_DAC + EDMA-ADC/DAC permission control register. + 0x2FC + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + EDMA_PMS_RMT_LOCK + EDMA-RMT permission lock register. + 0x300 + 0x20 + + + EDMA_PMS_RMT_LOCK + Set 1 to lock EDMA-RMT permission control registers. + 0 + 1 + read-write + + + + + EDMA_PMS_RMT + EDMA-RMT permission control register. + 0x304 + 0x20 + 0x0000000F + + + ATTR1 + This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 0 + 2 + read-write + + + ATTR2 + This field is used to configure the permission of RMT accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission. + 2 + 2 + read-write + + + + + CLOCK_GATE_REG + Sensitive module clock gate configuration register. + 0x308 + 0x20 + 0x00000001 + + + REG_CLK_EN + Set 1 to enable clock gate function. + 0 + 1 + read-write + + + + + RTC_PMS + RTC coprocessor permission register. + 0x30C + 0x20 + + + DIS_RTC_CPU + Set 1 to disable rtc coprocessor. + 0 + 1 + read-write + + + + + DATE + Sensitive version register. + 0xFFC + 0x20 + 0x02101280 + + + DATE + Sensitive Date register. + 0 + 28 + read-write + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x6003B000 + + 0x0 + 0xB0 + registers + + + SHA + 78 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + sha mode + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + sha t_string(used if and only if mode == sha_256/t) + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + sha t_length(used if and only if mode == sha_256/t) + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + dma-sha block number + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + sha busy state. 1'b0: idle 1'b1: busy + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + start dma-sha + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + continue dma-sha + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + clear sha interrupt + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + sha interrupt enable register. 1'b0: disable(default) 1'b1: enable + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20190402 + + + DATE + sha date information/ sha version information + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller + SPI0 + 0x60003000 + + 0x0 + 0x98 + registers + + + SPI_MEM_REJECT + 60 + + + + CTRL + SPI0 control register. + 0x8 + 0x20 + 0x002C2000 + + + FDUMMY_OUT + In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 3 + 1 + read-write + + + FDOUT_OCT + Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + 4 + 1 + read-write + + + FDIN_OCT + Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + 5 + 1 + read-write + + + FADDR_OCT + Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + 6 + 1 + read-write + + + FCMD_DUAL + Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + 7 + 1 + read-write + + + FCMD_QUAD + Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + 8 + 1 + read-write + + + FCMD_OCT + Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + 9 + 1 + read-write + + + FASTRD_MODE + This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + 13 + 1 + read-write + + + FREAD_DUAL + In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + FREAD_DIO + In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI0 control 1 register. + 0xC + 0x20 + + + CLK_MODE + SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + RXFIFO_RST + SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts. + 30 + 1 + read-write + + + + + CTRL2 + SPI0 control 2 register. + 0x10 + 0x20 + 0x00002C21 + + + CS_SETUP_TIME + (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + CS_HOLD_TIME + SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-write + + + ECC_SKIP_PAGE_CORNER + 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-write + + + ECC_16TO18_BYTE_EN + Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-write + + + CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + read-write + + + + + CLOCK + SPI_CLK clock division register when SPI0 accesses to flash. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + It must equal to the value of SPI_MEM_CLKCNT_N. + 0 + 8 + read-write + + + CLKCNT_H + It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + USER + SPI0 user register. + 0x18 + 0x20 + + + CS_HOLD + Set this bit to keep SPI_CS low when MSPI is in DONE state. + 6 + 1 + read-write + + + CS_SETUP + Set this bit to keep SPI_CS low when MSPI is in PREP state. + 7 + 1 + read-write + + + CK_OUT_EDGE + This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + 9 + 1 + read-write + + + USR_DUMMY_IDLE + SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + 26 + 1 + read-write + + + USR_DUMMY + This bit enable the DUMMY phase of an SPI transfer. + 29 + 1 + read-write + + + + + USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The SPI_CLK cycle length minus 1 of DUMMY phase. + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of ADDR phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of user defined(USR) command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of CMD phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + WB_MODE + Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + 16 + 8 + read-write + + + + + EXT_ADDR + SPI0 extended address register. + 0x30 + 0x20 + + + EXT_ADDR + The register are the higher 32bits in the 64 bits address mode. + 0 + 32 + read-write + + + + + MISC + SPI0 misc register + 0x34 + 0x20 + + + FSUB_PIN + Flash is connected to SPI SUBPIN bus. + 7 + 1 + read-write + + + SSUB_PIN + Ext_RAM is connected to SPI SUBPIN bus. + 8 + 1 + read-write + + + CK_IDLE_EDGE + 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + CACHE_FCTRL + SPI0 external RAM bit mode control register. + 0x3C + 0x20 + + + CACHE_REQ_EN + Set this bit to enable Cache's access and SPI0's transfer. + 0 + 1 + read-write + + + CACHE_USR_CMD_4BYTE + Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + 1 + 1 + read-write + + + CACHE_FLASH_USR_CMD + 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits. + 2 + 1 + read-write + + + FDIN_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase. + 3 + 1 + read-write + + + FDOUT_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase. + 4 + 1 + read-write + + + FADDR_DUAL + When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase. + 5 + 1 + read-write + + + FDIN_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase. + 6 + 1 + read-write + + + FDOUT_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase. + 7 + 1 + read-write + + + FADDR_QUAD + When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase. + 8 + 1 + read-write + + + + + CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + CACHE_USR_SCMD_4BYTE + Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. + 0 + 1 + read-write + + + USR_SRAM_DIO + Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer. + 1 + 1 + read-write + + + USR_SRAM_QIO + Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. + 2 + 1 + read-write + + + USR_WR_SRAM_DUMMY + When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations. + 3 + 1 + read-write + + + USR_RD_SRAM_DUMMY + When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations. + 4 + 1 + read-write + + + CACHE_SRAM_USR_RCMD + 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2. + 5 + 1 + read-write + + + SRAM_RDUMMY_CYCLELEN + When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer. + 6 + 6 + read-write + + + SRAM_ADDR_BITLEN + When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1). + 14 + 6 + read-write + + + CACHE_SRAM_USR_WCMD + 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3. + 20 + 1 + read-write + + + SRAM_OCT + Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer. + 21 + 1 + read-write + + + SRAM_WDUMMY_CYCLELEN + When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer. + 22 + 6 + read-write + + + + + SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + + + SCLK_MODE + SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + SWB_MODE + Mode bits when SPI0 accesses to Ext_RAM. + 2 + 8 + read-write + + + SDIN_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase. + 10 + 1 + read-write + + + SDOUT_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase. + 11 + 1 + read-write + + + SADDR_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase. + 12 + 1 + read-write + + + SCMD_DUAL + When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase. + 13 + 1 + read-write + + + SDIN_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase. + 14 + 1 + read-write + + + SDOUT_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase. + 15 + 1 + read-write + + + SADDR_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase. + 16 + 1 + read-write + + + SCMD_QUAD + When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase. + 17 + 1 + read-write + + + SDIN_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase. + 18 + 1 + read-write + + + SDOUT_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase. + 19 + 1 + read-write + + + SADDR_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase. + 20 + 1 + read-write + + + SCMD_OCT + When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase. + 21 + 1 + read-write + + + SDUMMY_OUT + When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 22 + 1 + read-write + + + + + SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + CACHE_SRAM_USR_RD_CMD_VALUE + When SPI0 reads Ext_RAM, it is the command value of CMD phase. + 0 + 16 + read-write + + + CACHE_SRAM_USR_RD_CMD_BITLEN + When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + CACHE_SRAM_USR_WR_CMD_VALUE + When SPI0 writes Ext_RAM, it is the command value of CMD phase. + 0 + 16 + read-write + + + CACHE_SRAM_USR_WR_CMD_BITLEN + When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SRAM_CLK + SPI_CLK clock division register when SPI0 accesses to Ext_RAM. + 0x50 + 0x20 + 0x00030103 + + + SCLKCNT_L + It must equal to the value of SPI_MEM_SCLKCNT_N. + 0 + 8 + read-write + + + SCLKCNT_H + It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + SCLKCNT_N + When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) + 16 + 8 + read-write + + + SCLK_EQU_SYSCLK + When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + FSM + SPI0 state machine(FSM) status register. + 0x54 + 0x20 + + + ST + The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + 0 + 3 + read-only + + + + + TIMING_CALI + SPI0 timing compensation register when accesses to flash. + 0xA8 + 0x20 + + + TIMING_CLK_ENA + Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + 0 + 1 + read-write + + + TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + DIN_MODE + MSPI input timing delay mode control register when accesses to flash. + 0xAC + 0x20 + + + DIN0_MODE + SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 0 + 3 + read-write + + + DIN1_MODE + SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 3 + 3 + read-write + + + DIN2_MODE + SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 6 + 3 + read-write + + + DIN3_MODE + SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 9 + 3 + read-write + + + DIN4_MODE + SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 12 + 3 + read-write + + + DIN5_MODE + SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 15 + 3 + read-write + + + DIN6_MODE + SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 18 + 3 + read-write + + + DIN7_MODE + SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 21 + 3 + read-write + + + DINS_MODE + SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 24 + 3 + read-write + + + + + DIN_NUM + MSPI input timing delay number control register when accesses to flash. + 0xB0 + 0x20 + + + DIN0_NUM + SPI_D input delay number. + 0 + 2 + read-write + + + DIN1_NUM + SPI_Q input delay number. + 2 + 2 + read-write + + + DIN2_NUM + SPI_WP input delay number. + 4 + 2 + read-write + + + DIN3_NUM + SPI_HD input delay number. + 6 + 2 + read-write + + + DIN4_NUM + SPI_IO4 input delay number. + 8 + 2 + read-write + + + DIN5_NUM + SPI_IO5 input delay number. + 10 + 2 + read-write + + + DIN6_NUM + SPI_IO6 input delay number. + 12 + 2 + read-write + + + DIN7_NUM + SPI_IO7 input delay number. + 14 + 2 + read-write + + + DINS_NUM + SPI_DQS input delay number. + 16 + 2 + read-write + + + + + DOUT_MODE + MSPI output timing delay mode control register when accesses to flash. + 0xB4 + 0x20 + + + DOUT0_MODE + SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 0 + 1 + read-write + + + DOUT1_MODE + SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 1 + 1 + read-write + + + DOUT2_MODE + SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 2 + 1 + read-write + + + DOUT3_MODE + SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 3 + 1 + read-write + + + DOUT4_MODE + SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 4 + 1 + read-write + + + DOUT5_MODE + SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 5 + 1 + read-write + + + DOUT6_MODE + SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 6 + 1 + read-write + + + DOUT7_MODE + SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 7 + 1 + read-write + + + DOUTS_MODE + SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + SPI0 Ext_RAM timing compensation register. + 0xBC + 0x20 + + + SPI_SMEM_TIMING_CLK_ENA + Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. + 0 + 1 + read-write + + + SPI_SMEM_TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + SPI_SMEM_DIN_MODE + MSPI input timing delay mode control register when accesses to Ext_RAM. + 0xC0 + 0x20 + + + SPI_SMEM_DIN0_MODE + SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 0 + 3 + read-write + + + SPI_SMEM_DIN1_MODE + SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 3 + 3 + read-write + + + SPI_SMEM_DIN2_MODE + SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 6 + 3 + read-write + + + SPI_SMEM_DIN3_MODE + SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 9 + 3 + read-write + + + SPI_SMEM_DIN4_MODE + SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 12 + 3 + read-write + + + SPI_SMEM_DIN5_MODE + SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 15 + 3 + read-write + + + SPI_SMEM_DIN6_MODE + SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 18 + 3 + read-write + + + SPI_SMEM_DIN7_MODE + SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 21 + 3 + read-write + + + SPI_SMEM_DINS_MODE + SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_NUM + MSPI input timing delay number control register when accesses to Ext_RAM. + 0xC4 + 0x20 + + + SPI_SMEM_DIN0_NUM + SPI_D input delay number. + 0 + 2 + read-write + + + SPI_SMEM_DIN1_NUM + SPI_Q input delay number. + 2 + 2 + read-write + + + SPI_SMEM_DIN2_NUM + SPI_WP input delay number. + 4 + 2 + read-write + + + SPI_SMEM_DIN3_NUM + SPI_HD input delay number. + 6 + 2 + read-write + + + SPI_SMEM_DIN4_NUM + SPI_IO4 input delay number. + 8 + 2 + read-write + + + SPI_SMEM_DIN5_NUM + SPI_IO5 input delay number. + 10 + 2 + read-write + + + SPI_SMEM_DIN6_NUM + SPI_IO6 input delay number. + 12 + 2 + read-write + + + SPI_SMEM_DIN7_NUM + SPI_IO7 input delay number. + 14 + 2 + read-write + + + SPI_SMEM_DINS_NUM + SPI_DQS input delay number. + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_MODE + MSPI output timing delay mode control register when accesses to Ext_RAM. + 0xC8 + 0x20 + + + SPI_SMEM_DOUT0_MODE + SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 0 + 1 + read-write + + + SPI_SMEM_DOUT1_MODE + SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 1 + 1 + read-write + + + SPI_SMEM_DOUT2_MODE + SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 2 + 1 + read-write + + + SPI_SMEM_DOUT3_MODE + SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 3 + 1 + read-write + + + SPI_SMEM_DOUT4_MODE + SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 4 + 1 + read-write + + + SPI_SMEM_DOUT5_MODE + SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 5 + 1 + read-write + + + SPI_SMEM_DOUT6_MODE + SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 6 + 1 + read-write + + + SPI_SMEM_DOUT7_MODE + SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_MODE + SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge. + 8 + 1 + read-write + + + + + ECC_CTRL + MSPI ECC control register + 0xCC + 0x20 + 0x0000000A + + + ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 0 + 8 + read-write + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 8 + 1 + read-write + + + + + ECC_ERR_ADDR + MSPI ECC error address register + 0xD0 + 0x20 + + + ECC_ERR_ADDR + These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte error and data error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 32 + read-only + + + + + ECC_ERR_BIT + MSPI ECC error bits register + 0xD4 + 0x20 + + + ECC_DATA_ERR_BIT + It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + 6 + 7 + read-only + + + ECC_CHK_ERR_BIT + When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte. + 13 + 3 + read-only + + + ECC_BYTE_ERR + It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + 16 + 1 + read-only + + + ECC_ERR_CNT + This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 17 + 8 + read-only + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0xDC + 0x20 + 0x0000B084 + + + SPI_SMEM_CS_SETUP + Set this bit to keep SPI_CS low when MSPI is in PREP state. + 0 + 1 + read-write + + + SPI_SMEM_CS_HOLD + Set this bit to keep SPI_CS low when MSPI is in DONE state. + 1 + 1 + read-write + + + SPI_SMEM_CS_SETUP_TIME + (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + 2 + 5 + read-write + + + SPI_SMEM_CS_HOLD_TIME + SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit. + 7 + 5 + read-write + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM. + 12 + 3 + read-write + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM. + 15 + 1 + read-write + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM. + 16 + 1 + read-write + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 24 + 1 + read-write + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + + + DDR + SPI0 flash DDR mode control register + 0xE0 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in DDR mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder RX data of the word in DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to swap TX data of a word in DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in CMD phase when ddr mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash. + 12 + 1 + read-write + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash. + 13 + 1 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + SPI_FMEM_DDR_DQS_LOOP_MODE + When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xE4 + 0x20 + 0x00003020 + + + EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-write + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-write + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-write + + + CMD_DIS + the bit is used to disable dual edge in CMD phase when ddr mode. + 4 + 1 + read-write + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the ddr psram. + 5 + 7 + read-write + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-write + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-write + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + DQS_LOOP_MODE + When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_SMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-write + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + CLOCK_GATE + SPI0 clk_gate register + 0xE8 + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + CORE_CLK_SEL + SPI0 module clock select register + 0xEC + 0x20 + + + CORE_CLK_SEL + When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. + 0 + 2 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xF0 + 0x20 + + + TOTAL_TRANS_END_INT_ENA + The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-write + + + ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 4 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xF4 + 0x20 + + + TOTAL_TRANS_END_INT_CLR + The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + write-only + + + ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit. + 4 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xF8 + 0x20 + + + TOTAL_TRANS_END_INT_RAW + The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + 2 + 1 + read-only + + + ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered. + 4 + 1 + read-only + + + + + INT_ST + SPI1 interrupt status register + 0xFC + 0x20 + + + TOTAL_TRANS_END_INT_ST + The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-only + + + ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 4 + 1 + read-only + + + + + DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02101040 + + + SPI_SMEM_SPICLK_FUN_DRV + The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM. + 0 + 2 + read-write + + + SPI_FMEM_SPICLK_FUN_DRV + The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash. + 2 + 2 + read-write + + + SPI_SPICLK_PAD_DRV_CTL_EN + SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD. + 4 + 1 + read-write + + + DATE + SPI register version. + 5 + 23 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller + SPI1 + 0x60002000 + + 0x0 + 0xB4 + registers + + + SPI1 + 20 + + + + CMD + SPI1 memory command register + 0x0 + 0x20 + + + FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + FLASH_RES + This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + FLASH_PP + Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + ADDR + SPI1 address register + 0x4 + 0x20 + + + USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + CTRL + SPI1 control register + 0x8 + 0x20 + 0x002CA000 + + + FDUMMY_OUT + In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + 3 + 1 + read-write + + + FDOUT_OCT + Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + 4 + 1 + read-write + + + FDIN_OCT + Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + 5 + 1 + read-write + + + FADDR_OCT + Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + 6 + 1 + read-write + + + FCMD_DUAL + Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + 7 + 1 + read-write + + + FCMD_QUAD + Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + 8 + 1 + read-write + + + FCMD_OCT + Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + 9 + 1 + read-write + + + FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + FASTRD_MODE + This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + 13 + 1 + read-write + + + FREAD_DUAL + In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + FREAD_QUAD + In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 20 + 1 + read-write + + + WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + WRSR_2B + Two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + FREAD_DIO + In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. + 23 + 1 + read-write + + + FREAD_QIO + In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. + 24 + 1 + read-write + + + + + CTRL1 + SPI1 control1 register + 0xC + 0x20 + 0x00000FFC + + + CLK_MODE + SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on. + 0 + 2 + read-write + + + CS_HOLD_DLY_RES + After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. + 2 + 10 + read-write + + + + + CTRL2 + SPI1 control2 register + 0x10 + 0x20 + + + SYNC_RESET + The FSM will be reset. + 31 + 1 + read-write + + + + + CLOCK + SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. + 0x14 + 0x20 + 0x00030103 + + + CLKCNT_L + It must equal to the value of SPI_MEM_CLKCNT_N. + 0 + 8 + read-write + + + CLKCNT_H + It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + 8 + 8 + read-write + + + CLKCNT_N + When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1) + 16 + 8 + read-write + + + CLK_EQU_SYSCLK + When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + 31 + 1 + read-write + + + + + USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + CK_OUT_EDGE + This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. + 9 + 1 + read-write + + + FWRITE_DUAL + Set this bit to enable 2-bm in DOUT phase in SPI1 write operation. + 12 + 1 + read-write + + + FWRITE_QUAD + Set this bit to enable 4-bm in DOUT phase in SPI1 write operation. + 13 + 1 + read-write + + + FWRITE_DIO + Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation. + 14 + 1 + read-write + + + FWRITE_QIO + Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation. + 15 + 1 + read-write + + + USR_MISO_HIGHPART + DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + 26 + 1 + read-write + + + USR_MOSI + Set this bit to enable the DOUT phase of an write-data operation. + 27 + 1 + read-write + + + USR_MISO + Set this bit to enable enable the DIN phase of a read-data operation. + 28 + 1 + read-write + + + USR_DUMMY + Set this bit to enable enable the DUMMY phase of an operation. + 29 + 1 + read-write + + + USR_ADDR + Set this bit to enable enable the ADDR phase of an operation. + 30 + 1 + read-write + + + USR_COMMAND + Set this bit to enable enable the CMD phase of an operation. + 31 + 1 + read-write + + + + + USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + USR_DUMMY_CYCLELEN + The SPI_CLK cycle length minus 1 of DUMMY phase. + 0 + 6 + read-write + + + USR_ADDR_BITLEN + The length in bits of ADDR phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + USR_COMMAND_VALUE + The value of user defined(USR) command. + 0 + 16 + read-write + + + USR_COMMAND_BITLEN + The length in bits of CMD phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + MOSI_DLEN + SPI1 write-data bit length register. + 0x24 + 0x20 + + + USR_MOSI_DBITLEN + The length in bits of DOUT phase. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + MISO_DLEN + SPI1 read-data bit length register. + 0x28 + 0x20 + + + USR_MISO_DBITLEN + The length in bits of DIN phase. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + RD_STATUS + SPI1 read control register. + 0x2C + 0x20 + + + STATUS + The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit. + 0 + 16 + read-write + + + WB_MODE + Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + 16 + 8 + read-write + + + + + EXT_ADDR + SPI1 extended address register. + 0x30 + 0x20 + + + EXT_ADDR + The register are the higher 32bits in the 64 bits address mode. + 0 + 32 + read-write + + + + + MISC + SPI1 misc register. + 0x34 + 0x20 + 0x00000002 + + + CS0_DIS + Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts. + 0 + 1 + read-write + + + CS1_DIS + Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts. + 1 + 1 + read-write + + + CK_IDLE_EDGE + 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle. + 9 + 1 + read-write + + + CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + AUTO_PER + Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent. + 11 + 1 + read-write + + + + + TX_CRC + SPI1 CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + CACHE_USR_CMD_4BYTE + Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + 1 + 1 + read-write + + + FDIN_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase. + 3 + 1 + read-write + + + FDOUT_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase. + 4 + 1 + read-write + + + FADDR_DUAL + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase. + 5 + 1 + read-write + + + FDIN_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase. + 6 + 1 + read-write + + + FDOUT_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase. + 7 + 1 + read-write + + + FADDR_QUAD + When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase. + 8 + 1 + read-write + + + + + FSM + SPI1 state machine(FSM) status register. + 0x54 + 0x20 + + + ST + The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE). + 0 + 3 + read-only + + + + + W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00000014 + + + WAITI_EN + Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent. + 0 + 1 + read-write + + + WAITI_DUMMY + Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR). + 1 + 1 + read-write + + + WAITI_CMD + The command value of auto wait flash idle transfer(RDSR). + 2 + 8 + read-write + + + WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + + + FLASH_SUS_CMD + SPI1 flash suspend control register + 0x9C + 0x20 + + + FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + FLASH_PER_WAIT_EN + Set this bit to add delay time after program erase resume(PER) is sent. + 2 + 1 + read-write + + + FLASH_PES_WAIT_EN + Set this bit to add delay time after program erase suspend(PES) command is sent. + 3 + 1 + read-write + + + PES_PER_EN + Set this bit to enable PES transfer trigger PES transfer option. + 4 + 1 + read-write + + + PESR_IDLE_EN + 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate. + 5 + 1 + read-write + + + + + FLASH_SUS_CTRL + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x0000EAF4 + + + FLASH_PES_EN + Set this bit to enable auto-suspend function. + 0 + 1 + read-write + + + FLASH_PER_COMMAND + Program/Erase resume command value. + 1 + 8 + read-write + + + FLASH_PES_COMMAND + Program/Erase suspend command value. + 9 + 8 + read-write + + + + + SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + + + FLASH_SUS + The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1. + 0 + 1 + read-write + + + FLASH_HPM_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + FLASH_RES_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + FLASH_DP_DLY_256 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + FLASH_PER_DLY_256 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + FLASH_PES_DLY_256 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + + + TIMING_CALI + SPI1 timing compensation register when accesses to flash or Ext_RAM. + 0xA8 + 0x20 + + + TIMING_CALI + Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + 1 + 1 + read-write + + + EXTRA_DUMMY_CYCLELEN + Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set. + 2 + 3 + read-write + + + + + DDR + SPI1 DDR control register + 0xE0 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0: in SDR mode. + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in DDRmode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder RX data of the word in DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder TX data of the word in DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI_CLK. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module + 21 + 1 + read-write + + + SPI_FMEM_DDR_DQS_LOOP_MODE + When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active. + 22 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_HYPERBUS_MODE + Set this bit to enable the SPI HyperBus mode. + 25 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + CLOCK_GATE + SPI1 clk_gate register + 0xE8 + 0x20 + 0x00000001 + + + CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + INT_ENA + SPI1 interrupt enable register + 0xF0 + 0x20 + + + PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + TOTAL_TRANS_END_INT_ENA + The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-write + + + BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + SPI1 interrupt clear register + 0xF4 + 0x20 + + + PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + TOTAL_TRANS_END_INT_CLR + The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + write-only + + + BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + write-only + + + + + INT_RAW + SPI1 interrupt raw register + 0xF8 + 0x20 + + + PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-only + + + PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-only + + + TOTAL_TRANS_END_INT_RAW + The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others. + 2 + 1 + read-only + + + BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 3 + 1 + read-only + + + + + INT_ST + SPI1 interrupt status register + 0xFC + 0x20 + + + PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + TOTAL_TRANS_END_INT_ST + The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + 2 + 1 + read-only + + + BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 3 + 1 + read-only + + + + + DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02101040 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller + SPI2 + 0x60024000 + + 0x0 + 0x98 + registers + + + SPI2 + 21 + + + + CMD + Command control register + 0x0 + 0x20 + + + CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + read-write + + + USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + ADDR + Address value register + 0x4 + 0x20 + + + USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-write + + + TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-write + + + USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-write + + + DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-write + + + ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-write + + + CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-write + + + SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-write + + + CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-write + + + TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-write + + + DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-write + + + DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-write + + + DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-write + + + D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-write + + + + + DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-only + + + SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-only + + + SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-only + + + SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-only + + + SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-only + + + TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-only + + + APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-only + + + APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-only + + + + + DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + BUF0 + data buffer + 0 + 32 + read-write + + + + + W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + BUF1 + data buffer + 0 + 32 + read-write + + + + + W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + BUF2 + data buffer + 0 + 32 + read-write + + + + + W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + BUF3 + data buffer + 0 + 32 + read-write + + + + + W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + BUF4 + data buffer + 0 + 32 + read-write + + + + + W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + BUF5 + data buffer + 0 + 32 + read-write + + + + + W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + BUF6 + data buffer + 0 + 32 + read-write + + + + + W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + BUF7 + data buffer + 0 + 32 + read-write + + + + + W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + BUF8 + data buffer + 0 + 32 + read-write + + + + + W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + BUF9 + data buffer + 0 + 32 + read-write + + + + + W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + BUF10 + data buffer + 0 + 32 + read-write + + + + + W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + BUF11 + data buffer + 0 + 32 + read-write + + + + + W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + BUF12 + data buffer + 0 + 32 + read-write + + + + + W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + BUF13 + data buffer + 0 + 32 + read-write + + + + + W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + BUF14 + data buffer + 0 + 32 + read-write + + + + + W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + BUF15 + data buffer + 0 + 32 + read-write + + + + + SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + + + SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + DATE + Version control + 0xF0 + 0x20 + 0x02101190 + + + DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI3 + SPI (Serial Peripheral Interface) Controller + 0x60025000 + + SPI3 + 22 + + + + SYSTEM + System + SYSTEM + 0x600C0000 + + 0x0 + 0xA8 + registers + + + + CORE_1_CONTROL_0 + Core0 control regiter 0 + 0x0 + 0x20 + 0x00000004 + + + CONTROL_CORE_1_RUNSTALL + Set 1 to stall core1 + 0 + 1 + read-write + + + CONTROL_CORE_1_CLKGATE_EN + Set 1 to open core1 clock + 1 + 1 + read-write + + + CONTROL_CORE_1_RESETING + Set 1 to let core1 reset + 2 + 1 + read-write + + + + + CORE_1_CONTROL_1 + Core0 control regiter 1 + 0x4 + 0x20 + + + CONTROL_CORE_1_MESSAGE + it's only a R/W register, no function, software can write any value + 0 + 32 + read-write + + + + + CPU_PERI_CLK_EN + cpu_peripheral clock configuration register + 0x8 + 0x20 + + + CLK_EN_ASSIST_DEBUG + Set 1 to open assist_debug module clock + 6 + 1 + read-write + + + CLK_EN_DEDICATED_GPIO + Set 1 to open dedicated_gpio module clk + 7 + 1 + read-write + + + + + CPU_PERI_RST_EN + cpu_peripheral reset configuration regsiter + 0xC + 0x20 + 0x000000C0 + + + RST_EN_ASSIST_DEBUG + Set 1 to let assist_debug module reset + 6 + 1 + read-write + + + RST_EN_DEDICATED_GPIO + Set 1 to let dedicated_gpio module reset + 7 + 1 + read-write + + + + + CPU_PER_CONF + cpu peripheral clock configuration register + 0x10 + 0x20 + 0x0000000C + + + CPUPERIOD_SEL + This field used to sel cpu clock frequent. + 0 + 2 + read-write + + + PLL_FREQ_SEL + This field used to sel pll frequent. + 2 + 1 + read-write + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 3 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 4 + 4 + read-write + + + + + MEM_PD_MASK + memory power down mask configuration register + 0x14 + 0x20 + 0x00000001 + + + LSLP_MEM_PD_MASK + Set 1 to mask memory power down. + 0 + 1 + read-write + + + + + PERIP_CLK_EN0 + peripheral clock configuration regsiter 0 + 0x18 + 0x20 + 0xF9C1E06F + + + TIMERS_CLK_EN + Set 1 to enable TIMERS clock + 0 + 1 + read-write + + + SPI01_CLK_EN + Set 1 to enable SPI01 clock + 1 + 1 + read-write + + + UART_CLK_EN + Set 1 to enable UART clock + 2 + 1 + read-write + + + WDG_CLK_EN + Set 1 to enable WDG clock + 3 + 1 + read-write + + + I2S0_CLK_EN + Set 1 to enable I2S0 clock + 4 + 1 + read-write + + + UART1_CLK_EN + Set 1 to enable UART1 clock + 5 + 1 + read-write + + + SPI2_CLK_EN + Set 1 to enable SPI2 clock + 6 + 1 + read-write + + + I2C_EXT0_CLK_EN + Set 1 to enable I2C_EXT0 clock + 7 + 1 + read-write + + + UHCI0_CLK_EN + Set 1 to enable UHCI0 clock + 8 + 1 + read-write + + + RMT_CLK_EN + Set 1 to enable RMT clock + 9 + 1 + read-write + + + PCNT_CLK_EN + Set 1 to enable PCNT clock + 10 + 1 + read-write + + + LEDC_CLK_EN + Set 1 to enable LEDC clock + 11 + 1 + read-write + + + UHCI1_CLK_EN + Set 1 to enable UHCI1 clock + 12 + 1 + read-write + + + TIMERGROUP_CLK_EN + Set 1 to enable TIMERGROUP clock + 13 + 1 + read-write + + + EFUSE_CLK_EN + Set 1 to enable EFUSE clock + 14 + 1 + read-write + + + TIMERGROUP1_CLK_EN + Set 1 to enable TIMERGROUP1 clock + 15 + 1 + read-write + + + SPI3_CLK_EN + Set 1 to enable SPI3 clock + 16 + 1 + read-write + + + PWM0_CLK_EN + Set 1 to enable PWM0 clock + 17 + 1 + read-write + + + I2C_EXT1_CLK_EN + Set 1 to enable I2C_EXT1 clock + 18 + 1 + read-write + + + CAN_CLK_EN + Set 1 to enable CAN clock + 19 + 1 + read-write + + + PWM1_CLK_EN + Set 1 to enable PWM1 clock + 20 + 1 + read-write + + + I2S1_CLK_EN + Set 1 to enable I2S1 clock + 21 + 1 + read-write + + + SPI2_DMA_CLK_EN + Set 1 to enable SPI2_DMA clock + 22 + 1 + read-write + + + USB_CLK_EN + Set 1 to enable USB clock + 23 + 1 + read-write + + + UART_MEM_CLK_EN + Set 1 to enable UART_MEM clock + 24 + 1 + read-write + + + PWM2_CLK_EN + Set 1 to enable PWM2 clock + 25 + 1 + read-write + + + PWM3_CLK_EN + Set 1 to enable PWM3 clock + 26 + 1 + read-write + + + SPI3_DMA_CLK_EN + Set 1 to enable SPI4 clock + 27 + 1 + read-write + + + APB_SARADC_CLK_EN + Set 1 to enable APB_SARADC clock + 28 + 1 + read-write + + + SYSTIMER_CLK_EN + Set 1 to enable SYSTEMTIMER clock + 29 + 1 + read-write + + + ADC2_ARB_CLK_EN + Set 1 to enable ADC2_ARB clock + 30 + 1 + read-write + + + SPI4_CLK_EN + Set 1 to enable SPI4 clock + 31 + 1 + read-write + + + + + PERIP_CLK_EN1 + peripheral clock configuration regsiter 1 + 0x1C + 0x20 + 0x00000600 + + + PERI_BACKUP_CLK_EN + Set 1 to enable BACKUP clock + 0 + 1 + read-write + + + CRYPTO_AES_CLK_EN + Set 1 to enable AES clock + 1 + 1 + read-write + + + CRYPTO_SHA_CLK_EN + Set 1 to enable SHA clock + 2 + 1 + read-write + + + CRYPTO_RSA_CLK_EN + Set 1 to enable RSA clock + 3 + 1 + read-write + + + CRYPTO_DS_CLK_EN + Set 1 to enable DS clock + 4 + 1 + read-write + + + CRYPTO_HMAC_CLK_EN + Set 1 to enable HMAC clock + 5 + 1 + read-write + + + DMA_CLK_EN + Set 1 to enable DMA clock + 6 + 1 + read-write + + + SDIO_HOST_CLK_EN + Set 1 to enable SDIO_HOST clock + 7 + 1 + read-write + + + LCD_CAM_CLK_EN + Set 1 to enable LCD_CAM clock + 8 + 1 + read-write + + + UART2_CLK_EN + Set 1 to enable UART2 clock + 9 + 1 + read-write + + + USB_DEVICE_CLK_EN + Set 1 to enable USB_DEVICE clock + 10 + 1 + read-write + + + + + PERIP_RST_EN0 + peripheral reset configuration register0 + 0x20 + 0x20 + + + TIMERS_RST + Set 1 to let TIMERS reset + 0 + 1 + read-write + + + SPI01_RST + Set 1 to let SPI01 reset + 1 + 1 + read-write + + + UART_RST + Set 1 to let UART reset + 2 + 1 + read-write + + + WDG_RST + Set 1 to let WDG reset + 3 + 1 + read-write + + + I2S0_RST + Set 1 to let I2S0 reset + 4 + 1 + read-write + + + UART1_RST + Set 1 to let UART1 reset + 5 + 1 + read-write + + + SPI2_RST + Set 1 to let SPI2 reset + 6 + 1 + read-write + + + I2C_EXT0_RST + Set 1 to let I2C_EXT0 reset + 7 + 1 + read-write + + + UHCI0_RST + Set 1 to let UHCI0 reset + 8 + 1 + read-write + + + RMT_RST + Set 1 to let RMT reset + 9 + 1 + read-write + + + PCNT_RST + Set 1 to let PCNT reset + 10 + 1 + read-write + + + LEDC_RST + Set 1 to let LEDC reset + 11 + 1 + read-write + + + UHCI1_RST + Set 1 to let UHCI1 reset + 12 + 1 + read-write + + + TIMERGROUP_RST + Set 1 to let TIMERGROUP reset + 13 + 1 + read-write + + + EFUSE_RST + Set 1 to let EFUSE reset + 14 + 1 + read-write + + + TIMERGROUP1_RST + Set 1 to let TIMERGROUP1 reset + 15 + 1 + read-write + + + SPI3_RST + Set 1 to let SPI3 reset + 16 + 1 + read-write + + + PWM0_RST + Set 1 to let PWM0 reset + 17 + 1 + read-write + + + I2C_EXT1_RST + Set 1 to let I2C_EXT1 reset + 18 + 1 + read-write + + + CAN_RST + Set 1 to let CAN reset + 19 + 1 + read-write + + + PWM1_RST + Set 1 to let PWM1 reset + 20 + 1 + read-write + + + I2S1_RST + Set 1 to let I2S1 reset + 21 + 1 + read-write + + + SPI2_DMA_RST + Set 1 to let SPI2 reset + 22 + 1 + read-write + + + USB_RST + Set 1 to let USB reset + 23 + 1 + read-write + + + UART_MEM_RST + Set 1 to let UART_MEM reset + 24 + 1 + read-write + + + PWM2_RST + Set 1 to let PWM2 reset + 25 + 1 + read-write + + + PWM3_RST + Set 1 to let PWM3 reset + 26 + 1 + read-write + + + SPI3_DMA_RST + Set 1 to let SPI3 reset + 27 + 1 + read-write + + + APB_SARADC_RST + Set 1 to let APB_SARADC reset + 28 + 1 + read-write + + + SYSTIMER_RST + Set 1 to let SYSTIMER reset + 29 + 1 + read-write + + + ADC2_ARB_RST + Set 1 to let ADC2_ARB reset + 30 + 1 + read-write + + + SPI4_RST + Set 1 to let SPI4 reset + 31 + 1 + read-write + + + + + PERIP_RST_EN1 + peripheral reset configuration regsiter 1 + 0x24 + 0x20 + 0x000001FE + + + PERI_BACKUP_RST + Set 1 to let BACKUP reset + 0 + 1 + read-write + + + CRYPTO_AES_RST + Set 1 to let CRYPTO_AES reset + 1 + 1 + read-write + + + CRYPTO_SHA_RST + Set 1 to let CRYPTO_SHA reset + 2 + 1 + read-write + + + CRYPTO_RSA_RST + Set 1 to let CRYPTO_RSA reset + 3 + 1 + read-write + + + CRYPTO_DS_RST + Set 1 to let CRYPTO_DS reset + 4 + 1 + read-write + + + CRYPTO_HMAC_RST + Set 1 to let CRYPTO_HMAC reset + 5 + 1 + read-write + + + DMA_RST + Set 1 to let DMA reset + 6 + 1 + read-write + + + SDIO_HOST_RST + Set 1 to let SDIO_HOST reset + 7 + 1 + read-write + + + LCD_CAM_RST + Set 1 to let LCD_CAM reset + 8 + 1 + read-write + + + UART2_RST + Set 1 to let UART2 reset + 9 + 1 + read-write + + + USB_DEVICE_RST + Set 1 to let USB_DEVICE reset + 10 + 1 + read-write + + + + + BT_LPCK_DIV_INT + low power clock frequent division factor configuration regsiter + 0x28 + 0x20 + 0x000000FF + + + BT_LPCK_DIV_NUM + This field is lower power clock frequent division factor + 0 + 12 + read-write + + + + + BT_LPCK_DIV_FRAC + low power clock configuration register + 0x2C + 0x20 + 0x02001001 + + + BT_LPCK_DIV_B + This field is lower power clock frequent division factor b + 0 + 12 + read-write + + + BT_LPCK_DIV_A + This field is lower power clock frequent division factor a + 12 + 12 + read-write + + + LPCLK_SEL_RTC_SLOW + Set 1 to select rtc-slow clock as rtc low power clock + 24 + 1 + read-write + + + LPCLK_SEL_8M + Set 1 to select 8m clock as rtc low power clock + 25 + 1 + read-write + + + LPCLK_SEL_XTAL + Set 1 to select xtal clock as rtc low power clock + 26 + 1 + read-write + + + LPCLK_SEL_XTAL32K + Set 1 to select xtal32k clock as low power clock + 27 + 1 + read-write + + + LPCLK_RTC_EN + Set 1 to enable RTC low power clock + 28 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + interrupt source register 0 + 0x30 + 0x20 + + + CPU_INTR_FROM_CPU_0 + Set 1 to generate cpu interrupt 0 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + interrupt source register 1 + 0x34 + 0x20 + + + CPU_INTR_FROM_CPU_1 + Set 1 to generate cpu interrupt 1 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + interrupt source register 2 + 0x38 + 0x20 + + + CPU_INTR_FROM_CPU_2 + Set 1 to generate cpu interrupt 2 + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + interrupt source register 3 + 0x3C + 0x20 + + + CPU_INTR_FROM_CPU_3 + Set 1 to generate cpu interrupt 3 + 0 + 1 + read-write + + + + + RSA_PD_CTRL + rsa memory power control register + 0x40 + 0x20 + 0x00000001 + + + RSA_MEM_PD + Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set 1 to force power up RSA memory, this bit has the second highest priority. + 1 + 1 + read-write + + + RSA_MEM_FORCE_PD + Set 1 to force power down RSA memory,this bit has the highest priority. + 2 + 1 + read-write + + + + + EDMA_CTRL + EDMA control register + 0x44 + 0x20 + 0x00000001 + + + EDMA_CLK_ON + Set 1 to enable EDMA clock. + 0 + 1 + read-write + + + EDMA_RESET + Set 1 to let EDMA reset + 1 + 1 + read-write + + + + + CACHE_CONTROL + Cache control register + 0x48 + 0x20 + 0x00000005 + + + ICACHE_CLK_ON + Set 1 to enable icache clock + 0 + 1 + read-write + + + ICACHE_RESET + Set 1 to let icache reset + 1 + 1 + read-write + + + DCACHE_CLK_ON + Set 1 to enable dcache clock + 2 + 1 + read-write + + + DCACHE_RESET + Set 1 to let dcache reset + 3 + 1 + read-write + + + + + EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + External memory encrypt and decrypt control register + 0x4C + 0x20 + + + ENABLE_SPI_MANUAL_ENCRYPT + Set 1 to enable the SPI manual encrypt. + 0 + 1 + read-write + + + ENABLE_DOWNLOAD_DB_ENCRYPT + Set 1 to enable download DB encrypt. + 1 + 1 + read-write + + + ENABLE_DOWNLOAD_G0CB_DECRYPT + Set 1 to enable download G0CB decrypt + 2 + 1 + read-write + + + ENABLE_DOWNLOAD_MANUAL_ENCRYPT + Set 1 to enable download manual encrypt + 3 + 1 + read-write + + + + + RTC_FASTMEM_CONFIG + RTC fast memory configuration register + 0x50 + 0x20 + 0x7FF00000 + + + RTC_MEM_CRC_START + Set 1 to start the CRC of RTC memory + 8 + 1 + read-write + + + RTC_MEM_CRC_ADDR + This field is used to set address of RTC memory for CRC. + 9 + 11 + read-write + + + RTC_MEM_CRC_LEN + This field is used to set length of RTC memory for CRC based on start address. + 20 + 11 + read-write + + + RTC_MEM_CRC_FINISH + This bit stores the status of RTC memory CRC.1 means finished. + 31 + 1 + read-only + + + + + RTC_FASTMEM_CRC + RTC fast memory CRC control register + 0x54 + 0x20 + + + RTC_MEM_CRC_RES + This field stores the CRC result of RTC memory. + 0 + 32 + read-only + + + + + REDUNDANT_ECO_CTRL + ******* Description *********** + 0x58 + 0x20 + + + REDUNDANT_ECO_DRIVE + ******* Description *********** + 0 + 1 + read-write + + + REDUNDANT_ECO_RESULT + ******* Description *********** + 1 + 1 + read-only + + + + + CLOCK_GATE + ******* Description *********** + 0x5C + 0x20 + 0x00000001 + + + CLK_EN + ******* Description *********** + 0 + 1 + read-write + + + + + SYSCLK_CONF + System clock configuration register. + 0x60 + 0x20 + 0x00000001 + + + PRE_DIV_CNT + This field is used to set the count of prescaler of XTAL_CLK. + 0 + 10 + read-write + + + SOC_CLK_SEL + This field is used to select soc clock. + 10 + 2 + read-write + + + CLK_XTAL_FREQ + This field is used to read xtal frequency in MHz. + 12 + 7 + read-only + + + CLK_DIV_EN + Reserved. + 19 + 1 + read-only + + + + + MEM_PVT + ******* Description *********** + 0x64 + 0x20 + 0x00000003 + + + MEM_PATH_LEN + ******* Description *********** + 0 + 4 + read-write + + + MEM_ERR_CNT_CLR + ******* Description *********** + 4 + 1 + write-only + + + MONITOR_EN + ******* Description *********** + 5 + 1 + read-write + + + MEM_TIMING_ERR_CNT + ******* Description *********** + 6 + 16 + read-only + + + MEM_VT_SEL + ******* Description *********** + 22 + 2 + read-write + + + + + COMB_PVT_LVT_CONF + ******* Description *********** + 0x68 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_LVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_LVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_LVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_NVT_CONF + ******* Description *********** + 0x6C + 0x20 + 0x00000003 + + + COMB_PATH_LEN_NVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_NVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_NVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_HVT_CONF + ******* Description *********** + 0x70 + 0x20 + 0x00000003 + + + COMB_PATH_LEN_HVT + ******* Description *********** + 0 + 5 + read-write + + + COMB_ERR_CNT_CLR_HVT + ******* Description *********** + 5 + 1 + write-only + + + COMB_PVT_MONITOR_EN_HVT + ******* Description *********** + 6 + 1 + read-write + + + + + COMB_PVT_ERR_LVT_SITE0 + ******* Description *********** + 0x74 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE0 + ******* Description *********** + 0x78 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE0 + ******* Description *********** + 0x7C + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE0 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE1 + ******* Description *********** + 0x80 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE1 + ******* Description *********** + 0x84 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE1 + ******* Description *********** + 0x88 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE1 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE2 + ******* Description *********** + 0x8C + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE2 + ******* Description *********** + 0x90 + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE2 + ******* Description *********** + 0x94 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE2 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_LVT_SITE3 + ******* Description *********** + 0x98 + 0x20 + + + COMB_TIMING_ERR_CNT_LVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_NVT_SITE3 + ******* Description *********** + 0x9C + 0x20 + + + COMB_TIMING_ERR_CNT_NVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + COMB_PVT_ERR_HVT_SITE3 + ******* Description *********** + 0xA0 + 0x20 + + + COMB_TIMING_ERR_CNT_HVT_SITE3 + ******* Description *********** + 0 + 16 + read-only + + + + + DATE + version register + 0xFFC + 0x20 + 0x02101220 + + + DATE + version register + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x60023000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 57 + + + SYSTIMER_TARGET1 + 58 + + + SYSTIMER_TARGET2 + 59 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-only + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-only + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-only + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02012251 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group + TIMG + 0x6001F000 + + 0x0 + 0x8C + registers + + + TG0_T0_LEVEL + 50 + + + TG0_T1_LEVEL + 51 + + + TG0_WDT_LEVEL + 52 + + + + 2 + 0x24 + T%sCONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sLO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + 2 + 0x24 + T%sHI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + 2 + 0x24 + T%sUPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + 2 + 0x24 + T%sALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + 2 + 0x24 + T%sLOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + 2 + 0x24 + T%sLOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + 2 + 0x24 + T%sLOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + LOAD + +Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + Reserved + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00013000 + + + RTC_CALI_START_CYCLING + Reserved + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_80m. 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + Reserved + 15 + 1 + read-only + + + RTC_CALI_MAX + Reserved + 16 + 15 + read-write + + + RTC_CALI_START + Reserved + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + Reserved + 0 + 1 + read-only + + + RTC_CALI_VALUE + Reserved + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + T1_INT_ENA + The interrupt enable bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_RAW + The raw interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_ST + The masked interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + T1_INT_CLR + Set this bit to clear the TIMG_T1_INT interrupt. + 1 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 2 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02003071 + + + NTIMERS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + + + CLK_EN + Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group + 0x60020000 + + TG1_T0_LEVEL + 53 + + + TG1_T1_LEVEL + 54 + + + TG1_WDT_LEVEL + 55 + + + + TWAI + Two-Wire Automotive Interface + TWAI + 0x6002B000 + + 0x0 + 0x6C + registers + + + TWAI + 45 + + + + MODE + Mode Register + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. + 2 + 1 + read-write + + + RX_FILTER_MODE + This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. + 3 + 1 + read-write + + + + + CMD + Command Register + 0x4 + 0x20 + + + TX_REQ + Set the bit to 1 to allow the driving nodes start transmission. + 0 + 1 + write-only + + + ABORT_TX + Set the bit to 1 to cancel a pending transmission request. + 1 + 1 + write-only + + + RELEASE_BUF + Set the bit to 1 to release the RX buffer. + 2 + 1 + write-only + + + CLR_OVERRUN + Set the bit to 1 to clear the data overrun status bit. + 3 + 1 + write-only + + + SELF_RX_REQ + Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + 4 + 1 + write-only + + + + + STATUS + Status register + 0x8 + 0x20 + + + RX_BUF_ST + 1: The data in the RX buffer is not empty, with at least one received data packet. + 0 + 1 + read-only + + + OVERRUN_ST + 1: The RX FIFO is full and data overrun has occurred. + 1 + 1 + read-only + + + TX_BUF_ST + 1: The TX buffer is empty, the CPU may write a message into it. + 2 + 1 + read-only + + + TX_COMPLETE + 1: The TWAI controller has successfully received a packet from the bus. + 3 + 1 + read-only + + + RX_ST + 1: The TWAI Controller is receiving a message from the bus. + 4 + 1 + read-only + + + TX_ST + 1: The TWAI Controller is transmitting a message to the bus. + 5 + 1 + read-only + + + ERR_ST + 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. + 6 + 1 + read-only + + + BUS_OFF_ST + 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. + 7 + 1 + read-only + + + MISS_ST + This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete + 8 + 1 + read-only + + + + + INT_RAW + Interrupt Register + 0xC + 0x20 + + + RX_INT_ST + Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. + 0 + 1 + read-only + + + TX_INT_ST + Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. + 1 + 1 + read-only + + + ERR_WARN_INT_ST + Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). + 2 + 1 + read-only + + + OVERRUN_INT_ST + Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. + 3 + 1 + read-only + + + ERR_PASSIVE_INT_ST + Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. + 5 + 1 + read-only + + + ARB_LOST_INT_ST + Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. + 6 + 1 + read-only + + + BUS_ERR_INT_ST + Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. + 7 + 1 + read-only + + + + + INT_ENA + Interrupt Enable Register + 0x10 + 0x20 + + + RX_INT_ENA + Set this bit to 1 to enable receive interrupt. + 0 + 1 + read-write + + + TX_INT_ENA + Set this bit to 1 to enable transmit interrupt. + 1 + 1 + read-write + + + ERR_WARN_INT_ENA + Set this bit to 1 to enable error warning interrupt. + 2 + 1 + read-write + + + OVERRUN_INT_ENA + Set this bit to 1 to enable data overrun interrupt. + 3 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + Set this bit to 1 to enable error passive interrupt. + 5 + 1 + read-write + + + ARB_LOST_INT_ENA + Set this bit to 1 to enable arbitration lost interrupt. + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + Set this bit to 1 to enable error interrupt. + 7 + 1 + read-write + + + + + BUS_TIMING_0 + Bus Timing Register 0 + 0x18 + 0x20 + + + BAUD_PRESC + Baud Rate Prescaler, determines the frequency dividing ratio. + 0 + 14 + + + SYNC_JUMP_WIDTH + Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. + 14 + 2 + + + + + BUS_TIMING_1 + Bus Timing Register 1 + 0x1C + 0x20 + + + TIME_SEG1 + The width of PBS1. + 0 + 4 + + + TIME_SEG2 + The width of PBS2. + 4 + 3 + + + TIME_SAMP + The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times + 7 + 1 + + + + + ARB_LOST_CAP + Arbitration Lost Capture Register + 0x2C + 0x20 + + + ARB_LOST_CAP + This register contains information about the bit position of lost arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + Error Code Capture Register + 0x30 + 0x20 + + + ECC_SEGMENT + This register contains information about the location of errors, see Table 181 for details. + 0 + 5 + read-only + + + ECC_DIRECTION + This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message + 5 + 1 + read-only + + + ECC_TYPE + This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + Error Warning Limit Register + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). + 0 + 8 + + + + + RX_ERR_CNT + Receive Error Counter Register + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register, reflects value changes under reception status. + 0 + 8 + + + + + TX_ERR_CNT + Transmit Error Counter Register + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register, reflects value changes under transmission status. + 0 + 8 + + + + + DATA_0 + Data register 0 + 0x40 + 0x20 + + + TX_BYTE_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_1 + Data register 1 + 0x44 + 0x20 + + + TX_BYTE_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_2 + Data register 2 + 0x48 + 0x20 + + + TX_BYTE_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_3 + Data register 3 + 0x4C + 0x20 + + + TX_BYTE_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_4 + Data register 4 + 0x50 + 0x20 + + + TX_BYTE_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_5 + Data register 5 + 0x54 + 0x20 + + + TX_BYTE_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_6 + Data register 6 + 0x58 + 0x20 + + + TX_BYTE_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_7 + Data register 7 + 0x5C + 0x20 + + + TX_BYTE_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_8 + Data register 8 + 0x60 + 0x20 + + + TX_BYTE_8 + Stored the 8th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_9 + Data register 9 + 0x64 + 0x20 + + + TX_BYTE_9 + Stored the 9th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_10 + Data register 10 + 0x68 + 0x20 + + + TX_BYTE_10 + Stored the 10th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_11 + Data register 11 + 0x6C + 0x20 + + + TX_BYTE_11 + Stored the 11th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + DATA_12 + Data register 12 + 0x70 + 0x20 + + + TX_BYTE_12 + Stored the 12th byte information of the data to be transmitted under operating mode. + 0 + 8 + write-only + + + + + RX_MESSAGE_CNT + Receive Message Counter Register + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + This register reflects the number of messages available within the RX FIFO. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock Divider register + 0x7C + 0x20 + + + CD + These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin + 8 + 1 + + + + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller + UART + 0x60000000 + + 0x0 + 0x84 + registers + + + UART0 + 27 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-only + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-only + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-only + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-only + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-only + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-only + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-only + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-only + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-only + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-only + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value, the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 10 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 10 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0 + a + 0x20 + 0x20 + 0x1000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 6 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 7 + 1 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 8 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 9 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 10 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 11 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 12 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 13 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 14 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 15 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 16 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 17 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 18 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 19 + 1 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 20 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 21 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 22 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 23 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 24 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 25 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 26 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 27 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 28 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00018060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 10 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 10 + 10 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 20 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 21 + 1 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 22 + 1 + read-write + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 23 + 1 + read-write + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x28 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x2C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x30 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + FLOW_CONF + Software flow-control configuration + 0x34 + 0x20 + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 0 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 1 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 2 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 3 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 4 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 5 + 1 + read-write + + + + + SLEEP_CONF + Sleep-mode configuration + 0x38 + 0x20 + 0x000000F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + + + SWFC_CONF0 + Software flow-control character configuration + 0x3C + 0x20 + 0x00004CE0 + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. + 0 + 10 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 10 + 8 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00004400 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. + 0 + 10 + read-write + + + XON_CHAR + This register stores the Xon flow control char. + 10 + 8 + read-write + + + + + TXBRK_CONF + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART threshold and allocation configuration + 0x60 + 0x20 + 0x00140012 + + + RX_SIZE + This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + 1 + 3 + read-write + + + TX_SIZE + This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + 4 + 3 + read-write + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 7 + 10 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 17 + 10 + read-write + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 27 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 28 + 1 + read-write + + + + + MEM_TX_STATUS + Tx-FIFO write and read offset address. + 0x64 + 0x20 + + + APB_TX_WADDR + This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. + 0 + 10 + read-only + + + TX_RADDR + This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + 11 + 10 + read-only + + + + + MEM_RX_STATUS + Rx-FIFO write and read offset address. + 0x68 + 0x20 + 0x00100200 + + + APB_RX_RADDR + This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + 0 + 10 + read-only + + + RX_WADDR + This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. + 11 + 10 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x6C + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x70 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x74 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x78 + 0x20 + 0x03701000 + + + SCLK_DIV_B + The denominator of the frequency divider factor. + 0 + 6 + read-write + + + SCLK_DIV_A + The numerator of the frequency divider factor. + 6 + 6 + read-write + + + SCLK_DIV_NUM + The integral part of the frequency divider factor. + 12 + 8 + read-write + + + SCLK_SEL + UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. + 20 + 2 + read-write + + + SCLK_EN + Set this bit to enable UART Tx/Rx clock. + 22 + 1 + read-write + + + RST_CORE + Write 1 then write 0 to this bit, reset UART Tx/Rx. + 23 + 1 + read-write + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit, reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit, reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x7C + 0x20 + 0x02008270 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + ID + UART ID register + 0x80 + 0x20 + 0x40000500 + + + ID + This register is used to configure the uart_id. + 0 + 30 + read-write + + + HIGH_SPEED + This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. + 30 + 1 + read-write + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 31 + 1 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x60010000 + + UART1 + 28 + + + + UART2 + UART (Universal Asynchronous Receiver-Transmitter) Controller + 0x6002E000 + + UART2 + 29 + + + + UHCI0 + Universal Host Controller Interface + UHCI + 0x60014000 + + 0x0 + 0x88 + registers + + + UHCI0 + 14 + + + + CONF0 + UHCI configuration register + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1, then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1, then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART0_CE + Set this bit to link up HCI and UART0. + 2 + 1 + read-write + + + UART1_CE + Set this bit to link up HCI and UART1. + 3 + 1 + read-write + + + UART2_CE + Set this bit to link up HCI and UART2. + 4 + 1 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + + + RX_START_INT_RAW + This is the interrupt raw bit. Triggered when a separator char has been sent. + 0 + 1 + read-only + + + TX_START_INT_RAW + This is the interrupt raw bit. Triggered when UHCI detects a separator char. + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value. + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_RAW + This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_RAW + This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers. + 5 + 1 + read-only + + + OUT_EOF_INT_RAW + This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data. + 6 + 1 + read-only + + + APP_CTRL0_INT_RAW + This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET. + 8 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RX_START_INT_ST + This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. + 0 + 1 + read-only + + + TX_START_INT_ST + This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1. + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1. + 8 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RX_START_INT_ENA + This is the interrupt enable bit for UHCI_RX_START_INT interrupt. + 0 + 1 + read-write + + + TX_START_INT_ENA + This is the interrupt enable bit for UHCI_TX_START_INT interrupt. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt. + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt. + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt. + 8 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear UHCI_RX_START_INT interrupt. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear UHCI_TX_START_INT interrupt. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear UHCI_RX_HUNG_INT interrupt. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear UHCI_TX_HUNG_INT interrupt. + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt. + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt. + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + Set this bit to clear UHCI_APP_CTRL0_INT interrupt. + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + Set this bit to clear UHCI_APP_CTRL1_INT interrupt. + 8 + 1 + write-only + + + + + APP_INT_SET + Software interrupt trigger source + 0x14 + 0x20 + + + APP_CTRL0_INT_SET + This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT. + 0 + 1 + write-only + + + APP_CTRL1_INT_SET + This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT. + 1 + 1 + write-only + + + + + CONF1 + UHCI configuration register + 0x18 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + This is the enable bit to check header checksum when UHCI receives a data packet. + 0 + 1 + read-write + + + CHECK_SEQ_EN + This is the enable bit to check sequence number when UHCI receives a data packet. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save the packet header when HCI receives a data packet. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode the data packet with a checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit. + 5 + 1 + read-write + + + WAIT_SW_START + The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1. + 7 + 1 + read-write + + + SW_START + If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1. + 8 + 1 + read-write + + + + + STATE0 + UHCI receive status + 0x1C + 0x20 + + + RX_ERR_CAUSE + This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error. + 0 + 3 + read-only + + + DECODE_STATE + UHCI decoder status. + 3 + 3 + read-only + + + + + STATE1 + UHCI transmit status + 0x20 + 0x20 + + + ENCODE_STATE + UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + Escape character configuration + 0x24 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable decoding char 0xc0 when DMA receives data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable decoding char 0xdb when DMA receives data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable decoding flow control char 0x11 when DMA receives data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable decoding flow control char 0x13 when DMA receives data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable replacing 0xc0 by special char when DMA sends data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable replacing 0xdb by special char when DMA sends data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data. + 7 + 1 + read-write + + + + + HUNG_CONF + Timeout configuration + 0x28 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + This register is used to configure the tick count maximum value. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + This is the enable bit for Tx-FIFO receive-data timeout. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + This register is used to configure the tick count maximum value. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + This is the enable bit for DMA send-data timeout. + 23 + 1 + read-write + + + + + ACK_NUM + UHCI ACK number configuration + 0x2C + 0x20 + 0x00000008 + + + ACK_NUM + This ACK number used in software flow control. + 0 + 3 + read-write + + + LOAD + Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded. + 3 + 1 + write-only + + + + + RX_HEAD + UHCI packet header register + 0x30 + 0x20 + + + RX_HEAD + This register stores the header of the current received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UHCI quick send configuration register + 0x34 + 0x20 + + + SINGLE_SEND_NUM + This register is used to specify the single_send register. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable single_send mode to send short packet. + 3 + 1 + read-write + + + ALWAYS_SEND_NUM + This register is used to specify the always_send register. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable always_send mode to send short packet. + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + Q0_WORD0 quick_sent register + 0x38 + 0x20 + + + SEND_Q0_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + Q0_WORD1 quick_sent register + 0x3C + 0x20 + + + SEND_Q0_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + Q1_WORD0 quick_sent register + 0x40 + 0x20 + + + SEND_Q1_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + Q1_WORD1 quick_sent register + 0x44 + 0x20 + + + SEND_Q1_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + Q2_WORD0 quick_sent register + 0x48 + 0x20 + + + SEND_Q2_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + Q2_WORD1 quick_sent register + 0x4C + 0x20 + + + SEND_Q2_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + Q3_WORD0 quick_sent register + 0x50 + 0x20 + + + SEND_Q3_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + Q3_WORD1 quick_sent register + 0x54 + 0x20 + + + SEND_Q3_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + Q4_WORD0 quick_sent register + 0x58 + 0x20 + + + SEND_Q4_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + Q4_WORD1 quick_sent register + 0x5C + 0x20 + + + SEND_Q4_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + Q5_WORD0 quick_sent register + 0x60 + 0x20 + + + SEND_Q5_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + Q5_WORD1 quick_sent register + 0x64 + 0x20 + + + SEND_Q5_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + Q6_WORD0 quick_sent register + 0x68 + 0x20 + + + SEND_Q6_WORD0 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + Q6_WORD1 quick_sent register + 0x6C + 0x20 + + + SEND_Q6_WORD1 + This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + Escape sequence configuration register 0 + 0x70 + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + This register is used to define the separate char that need to be encoded, default is 0xc0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc. + 16 + 8 + read-write + + + + + ESC_CONF1 + Escape sequence configuration register 1 + 0x74 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + This register is used to define a char that need to be encoded, default is 0xdb that used as the first char of slip escape sequence. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdd. + 16 + 8 + read-write + + + + + ESC_CONF2 + Escape sequence configuration register 2 + 0x78 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + This register is used to define a char that need to be encoded, default is 0x11 that used as flow control char. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xde. + 16 + 8 + read-write + + + + + ESC_CONF3 + Escape sequence configuration register 3 + 0x7C + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + This register is used to define a char that need to be decoded, default is 0x13 that used as flow control char. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdb. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdf. + 16 + 8 + read-write + + + + + PKT_THRES + Configure register for packet length + 0x80 + 0x20 + 0x00000080 + + + PKT_THRS + This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI version control register + 0x84 + 0x20 + 0x02010090 + + + DATE + This is the version control register. + 0 + 32 + read-write + + + + + + + UHCI1 + Universal Host Controller Interface + 0x6000C000 + + + USB_DEVICE + Peripheral USB_DEVICE + USB_DEVICE + 0x60038000 + + 0x0 + 0x50 + registers + + + USB_DEVICE + 96 + + + + EP1 + Endpoint 1 FIFO register + 0x0 + 0x20 + + + RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-write + + + + + EP1_CONF + Endpoint 1 configure and status register + 0x4 + 0x20 + 0x00000002 + + + WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Raw status interrupt + 0x8 + 0x20 + 0x00000008 + + + JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-only + + + SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-only + + + SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-only + + + SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-only + + + PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-only + + + CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-only + + + CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-only + + + STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-only + + + IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-only + + + USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-only + + + OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-only + + + OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-only + + + + + INT_ST + Masked interrupt + 0xC + 0x20 + + + JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x10 + 0x20 + + + JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x14 + 0x20 + + + JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + + + CONF0 + Configure 0 register + 0x18 + 0x20 + 0x00004200 + + + PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + PHY_TX_EDGE_SEL + 0: TX output at clock negedge. 1: Tx output at clock posedge. + 15 + 1 + read-write + + + USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 16 + 1 + read-write + + + + + TEST + USB Internal PHY test register + 0x1C + 0x20 + + + ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + RX_RCV + USB differential rx value in test + 4 + 1 + read-only + + + RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + USB-JTAG FIFO status + 0x20 + 0x20 + 0x00000044 + + + IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + SOF frame number + 0x24 + 0x20 + + + SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + IN Endpoint 0 status + 0x28 + 0x20 + 0x00000001 + + + IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + IN Endpoint 1 status + 0x2C + 0x20 + 0x00000001 + + + IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + IN Endpoint 2 status + 0x30 + 0x20 + 0x00000001 + + + IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + IN Endpoint 3 status + 0x34 + 0x20 + 0x00000001 + + + IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + OUT Endpoint 0 status + 0x38 + 0x20 + + + OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + OUT Endpoint 1 status + 0x3C + 0x20 + + + OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + OUT Endpoint 2 status + 0x40 + 0x20 + + + OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + MISC register + 0x44 + 0x20 + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Power control + 0x48 + 0x20 + 0x00000002 + + + USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02101200 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + USB_WRAP + Peripheral USB_WRAP + USB_WRAP + 0x60039000 + + 0x0 + 0xC + registers + + + + OTG_CONF + USB OTG Wrapper Configure Register + 0x0 + 0x20 + 0x001C0000 + + + SRP_SESSEND_OVERRIDE + This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software. + 0 + 1 + read-write + + + SRP_SESSEND_VALUE + Software over-ride value of srp session end signal. + 1 + 1 + read-write + + + PHY_SEL + Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY. + 2 + 1 + read-write + + + DFIFO_FORCE_PD + Force the dfifo to go into low power mode. The data in dfifo will not lost. + 3 + 1 + read-write + + + DBNCE_FLTR_BYPASS + Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + 4 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software controlle USB D+ D- exchange + 5 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D- + 6 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 7 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 9 + 2 + read-write + + + VREF_OVERRIDE + Enable software controlle input threshold + 11 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software controlle USB D+ D- pullup pulldown + 12 + 1 + read-write + + + DP_PULLUP + Controlle USB D+ pullup + 13 + 1 + read-write + + + DP_PULLDOWN + Controlle USB D+ pulldown + 14 + 1 + read-write + + + DM_PULLUP + Controlle USB D+ pullup + 15 + 1 + read-write + + + DM_PULLDOWN + Controlle USB D+ pulldown + 16 + 1 + read-write + + + PULLUP_VALUE + Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K. + 17 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function + 18 + 1 + read-write + + + AHB_CLK_FORCE_ON + Force ahb clock always on + 19 + 1 + read-write + + + PHY_CLK_FORCE_ON + Force phy clock always on + 20 + 1 + read-write + + + PHY_TX_EDGE_SEL + Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge. + 21 + 1 + read-write + + + DFIFO_FORCE_PU + Disable the dfifo to go into low power mode. The data in dfifo will not lost. + 22 + 1 + read-write + + + CLK_EN + Disable auto clock gating of CSR registers + 31 + 1 + read-write + + + + + TEST_CONF + USB Internal PHY Testing Register + 0x4 + 0x20 + + + TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + TEST_RX_RCV + USB differential rx value in test + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + DATE + Version Control Register + 0x3FC + 0x20 + 0x02102010 + + + USB_WRAP_DATE + Date register + 0 + 32 + read-write + + + + + + + WCL + Peripheral WCL + WCL + 0x600D0000 + + 0x0 + 0x160 + registers + + + + Core_0_ENTRY_1_ADDR + Core_0 Entry 1 address configuration Register + 0x0 + 0x20 + + + CORE_0_ENTRY_1_ADDR + Core_0 Entry 1 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_2_ADDR + Core_0 Entry 2 address configuration Register + 0x4 + 0x20 + + + CORE_0_ENTRY_2_ADDR + Core_0 Entry 2 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_3_ADDR + Core_0 Entry 3 address configuration Register + 0x8 + 0x20 + + + CORE_0_ENTRY_3_ADDR + Core_0 Entry 3 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_4_ADDR + Core_0 Entry 4 address configuration Register + 0xC + 0x20 + + + CORE_0_ENTRY_4_ADDR + Core_0 Entry 4 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_5_ADDR + Core_0 Entry 5 address configuration Register + 0x10 + 0x20 + + + CORE_0_ENTRY_5_ADDR + Core_0 Entry 5 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_6_ADDR + Core_0 Entry 6 address configuration Register + 0x14 + 0x20 + + + CORE_0_ENTRY_6_ADDR + Core_0 Entry 6 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_7_ADDR + Core_0 Entry 7 address configuration Register + 0x18 + 0x20 + + + CORE_0_ENTRY_7_ADDR + Core_0 Entry 7 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_8_ADDR + Core_0 Entry 8 address configuration Register + 0x1C + 0x20 + + + CORE_0_ENTRY_8_ADDR + Core_0 Entry 8 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_9_ADDR + Core_0 Entry 9 address configuration Register + 0x20 + 0x20 + + + CORE_0_ENTRY_9_ADDR + Core_0 Entry 9 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_10_ADDR + Core_0 Entry 10 address configuration Register + 0x24 + 0x20 + + + CORE_0_ENTRY_10_ADDR + Core_0 Entry 10 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_11_ADDR + Core_0 Entry 11 address configuration Register + 0x28 + 0x20 + + + CORE_0_ENTRY_11_ADDR + Core_0 Entry 11 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_12_ADDR + Core_0 Entry 12 address configuration Register + 0x2C + 0x20 + + + CORE_0_ENTRY_12_ADDR + Core_0 Entry 12 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_13_ADDR + Core_0 Entry 13 address configuration Register + 0x30 + 0x20 + + + CORE_0_ENTRY_13_ADDR + Core_0 Entry 13 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_0_ENTRY_CHECK + Core_0 Entry check configuration Register + 0x7C + 0x20 + 0x00000002 + + + CORE_0_ENTRY_CHECK + This filed is used to enable entry address check + 1 + 13 + read-write + + + + + Core_0_STATUSTABLE1 + Status register of world switch of entry 1 + 0x80 + 0x20 + + + CORE_0_FROM_WORLD_1 + This bit is used to confirm world before enter entry 1 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_1 + This filed is used to confirm in which entry before enter entry 1 + 1 + 4 + read-write + + + CORE_0_CURRENT_1 + This bit is used to confirm whether the current state is in entry 1 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE2 + Status register of world switch of entry 2 + 0x84 + 0x20 + + + CORE_0_FROM_WORLD_2 + This bit is used to confirm world before enter entry 2 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_2 + This filed is used to confirm in which entry before enter entry 2 + 1 + 4 + read-write + + + CORE_0_CURRENT_2 + This bit is used to confirm whether the current state is in entry 2 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE3 + Status register of world switch of entry 3 + 0x88 + 0x20 + + + CORE_0_FROM_WORLD_3 + This bit is used to confirm world before enter entry 3 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_3 + This filed is used to confirm in which entry before enter entry 3 + 1 + 4 + read-write + + + CORE_0_CURRENT_3 + This bit is used to confirm whether the current state is in entry 3 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE4 + Status register of world switch of entry 4 + 0x8C + 0x20 + + + CORE_0_FROM_WORLD_4 + This bit is used to confirm world before enter entry 4 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_4 + This filed is used to confirm in which entry before enter entry 4 + 1 + 4 + read-write + + + CORE_0_CURRENT_4 + This bit is used to confirm whether the current state is in entry 4 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE5 + Status register of world switch of entry 5 + 0x90 + 0x20 + + + CORE_0_FROM_WORLD_5 + This bit is used to confirm world before enter entry 5 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_5 + This filed is used to confirm in which entry before enter entry 5 + 1 + 4 + read-write + + + CORE_0_CURRENT_5 + This bit is used to confirm whether the current state is in entry 5 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE6 + Status register of world switch of entry 6 + 0x94 + 0x20 + + + CORE_0_FROM_WORLD_6 + This bit is used to confirm world before enter entry 6 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_6 + This filed is used to confirm in which entry before enter entry 6 + 1 + 4 + read-write + + + CORE_0_CURRENT_6 + This bit is used to confirm whether the current state is in entry 6 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE7 + Status register of world switch of entry 7 + 0x98 + 0x20 + + + CORE_0_FROM_WORLD_7 + This bit is used to confirm world before enter entry 7 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_7 + This filed is used to confirm in which entry before enter entry 7 + 1 + 4 + read-write + + + CORE_0_CURRENT_7 + This bit is used to confirm whether the current state is in entry 7 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE8 + Status register of world switch of entry 8 + 0x9C + 0x20 + + + CORE_0_FROM_WORLD_8 + This bit is used to confirm world before enter entry 8 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_8 + This filed is used to confirm in which entry before enter entry 8 + 1 + 4 + read-write + + + CORE_0_CURRENT_8 + This bit is used to confirm whether the current state is in entry 8 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE9 + Status register of world switch of entry 9 + 0xA0 + 0x20 + + + CORE_0_FROM_WORLD_9 + This bit is used to confirm world before enter entry 9 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_9 + This filed is used to confirm in which entry before enter entry 9 + 1 + 4 + read-write + + + CORE_0_CURRENT_9 + This bit is used to confirm whether the current state is in entry 9 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE10 + Status register of world switch of entry 10 + 0xA4 + 0x20 + + + CORE_0_FROM_WORLD_10 + This bit is used to confirm world before enter entry 10 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_10 + This filed is used to confirm in which entry before enter entry 10 + 1 + 4 + read-write + + + CORE_0_CURRENT_10 + This bit is used to confirm whether the current state is in entry 10 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE11 + Status register of world switch of entry 11 + 0xA8 + 0x20 + + + CORE_0_FROM_WORLD_11 + This bit is used to confirm world before enter entry 11 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_11 + This filed is used to confirm in which entry before enter entry 11 + 1 + 4 + read-write + + + CORE_0_CURRENT_11 + This bit is used to confirm whether the current state is in entry 11 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE12 + Status register of world switch of entry 12 + 0xAC + 0x20 + + + CORE_0_FROM_WORLD_12 + This bit is used to confirm world before enter entry 12 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_12 + This filed is used to confirm in which entry before enter entry 12 + 1 + 4 + read-write + + + CORE_0_CURRENT_12 + This bit is used to confirm whether the current state is in entry 12 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE13 + Status register of world switch of entry 13 + 0xB0 + 0x20 + + + CORE_0_FROM_WORLD_13 + This bit is used to confirm world before enter entry 13 + 0 + 1 + read-write + + + CORE_0_FROM_ENTRY_13 + This filed is used to confirm in which entry before enter entry 13 + 1 + 4 + read-write + + + CORE_0_CURRENT_13 + This bit is used to confirm whether the current state is in entry 13 + 5 + 1 + read-write + + + + + Core_0_STATUSTABLE_CURRENT + Status register of statustable current + 0xFC + 0x20 + + + CORE_0_STATUSTABLE_CURRENT + This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 represents the current field of STATUSTABLE2 + 1 + 13 + read-write + + + + + Core_0_MESSAGE_ADDR + Clear writer_buffer write address configuration register + 0x100 + 0x20 + + + CORE_0_MESSAGE_ADDR + This field is used to set address that need to write when enter WORLD0 + 0 + 32 + read-write + + + + + Core_0_MESSAGE_MAX + Clear writer_buffer write number configuration register + 0x104 + 0x20 + + + CORE_0_MESSAGE_MAX + This filed is used to set the max value of clear write_buffer + 0 + 4 + read-write + + + + + Core_0_MESSAGE_PHASE + Clear writer_buffer status register + 0x108 + 0x20 + + + CORE_0_MESSAGE_MATCH + This bit indicates whether the check is successful + 0 + 1 + read-only + + + CORE_0_MESSAGE_EXPECT + This field indicates the data to be written next time + 1 + 4 + read-only + + + CORE_0_MESSAGE_DATAPHASE + If this bit is 1, it means that is checking clear write_buffer operation,and is checking data + 5 + 1 + read-only + + + CORE_0_MESSAGE_ADDRESSPHASE + If this bit is 1, it means that is checking clear write_buffer operation,and is checking address. + 6 + 1 + read-only + + + + + Core_0_World_TRIGGER_ADDR + Core_0 trigger address configuration Register + 0x140 + 0x20 + + + CORE_0_WORLD_TRIGGER_ADDR + This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1 + 0 + 32 + read-write + + + + + Core_0_World_PREPARE + Core_0 prepare world configuration Register + 0x144 + 0x20 + + + CORE_0_WORLD_PREPARE + This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1 + 0 + 2 + read-write + + + + + Core_0_World_UPDATE + Core_0 configuration update register + 0x148 + 0x20 + + + CORE_0_UPDATE + This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_0_World_Cancel + Core_0 configuration cancel register + 0x14C + 0x20 + + + CORE_0_WORLD_CANCEL + This field is used to cancel switch world configuration,if the trigger address and update configuration complete,use this register to cancel world switch, jujst need write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_0_World_IRam0 + Core_0 Iram0 world register + 0x150 + 0x20 + + + CORE_0_WORLD_IRAM0 + this field is used to read current world of Iram0 bus + 0 + 2 + read-write + + + + + Core_0_World_DRam0_PIF + Core_0 dram0 and PIF world register + 0x154 + 0x20 + + + CORE_0_WORLD_DRAM0_PIF + this field is used to read current world of Dram0 bus and PIF bus + 0 + 2 + read-write + + + + + Core_0_World_Phase + Core_0 world status register + 0x158 + 0x20 + + + CORE_0_WORLD_PHASE + This bit indicates whether is preparing to switch to WORLD1, 1 means value. + 0 + 1 + read-only + + + + + Core_0_NMI_MASK_ENABLE + Core_0 NMI mask enable register + 0x180 + 0x20 + + + CORE_0_NMI_MASK_ENABLE + this field is used to set NMI mask,it can write any value,when write this register,the hardware start masking NMI interrupt + 0 + 32 + write-only + + + + + Core_0_NMI_MASK_TRIGGER_ADDR + Core_0 NMI mask trigger address register + 0x184 + 0x20 + + + CORE_0_NMI_MASK_TRIGGER_ADDR + this field to used to set trigger address, when CPU executes to this address,NMI mask automatically fails + 0 + 32 + read-write + + + + + Core_0_NMI_MASK_DISABLE + Core_0 NMI mask disable register + 0x188 + 0x20 + + + CORE_0_NMI_MASK_DISABLE + this field is used to disable NMI mask,it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask + 0 + 32 + write-only + + + + + Core_0_NMI_MASK_CANCLE + Core_0 NMI mask disable register + 0x18C + 0x20 + + + CORE_0_NMI_MASK_CANCEL + this field is used to cancel NMI mask disable function. + 0 + 32 + write-only + + + + + Core_0_NMI_MASK + Core_0 NMI mask register + 0x190 + 0x20 + + + CORE_0_NMI_MASK + this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + 0 + 1 + read-write + + + + + Core_0_NMI_MASK_PHASE + Core_0 NMI mask phase register + 0x194 + 0x20 + + + CORE_0_NMI_MASK_PHASE + this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked + 0 + 1 + read-only + + + + + Core_1_ENTRY_1_ADDR + Core_1 Entry 1 address configuration Register + 0x400 + 0x20 + + + CORE_1_ENTRY_1_ADDR + Core_1 Entry 1 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_2_ADDR + Core_1 Entry 2 address configuration Register + 0x404 + 0x20 + + + CORE_1_ENTRY_2_ADDR + Core_1 Entry 2 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_3_ADDR + Core_1 Entry 3 address configuration Register + 0x408 + 0x20 + + + CORE_1_ENTRY_3_ADDR + Core_1 Entry 3 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_4_ADDR + Core_1 Entry 4 address configuration Register + 0x40C + 0x20 + + + CORE_1_ENTRY_4_ADDR + Core_1 Entry 4 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_5_ADDR + Core_1 Entry 5 address configuration Register + 0x410 + 0x20 + + + CORE_1_ENTRY_5_ADDR + Core_1 Entry 5 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_6_ADDR + Core_1 Entry 6 address configuration Register + 0x414 + 0x20 + + + CORE_1_ENTRY_6_ADDR + Core_1 Entry 6 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_7_ADDR + Core_1 Entry 7 address configuration Register + 0x418 + 0x20 + + + CORE_1_ENTRY_7_ADDR + Core_1 Entry 7 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_8_ADDR + Core_1 Entry 8 address configuration Register + 0x41C + 0x20 + + + CORE_1_ENTRY_8_ADDR + Core_1 Entry 8 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_9_ADDR + Core_1 Entry 9 address configuration Register + 0x420 + 0x20 + + + CORE_1_ENTRY_9_ADDR + Core_1 Entry 9 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_10_ADDR + Core_1 Entry 10 address configuration Register + 0x424 + 0x20 + + + CORE_1_ENTRY_10_ADDR + Core_1 Entry 10 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_11_ADDR + Core_1 Entry 11 address configuration Register + 0x428 + 0x20 + + + CORE_1_ENTRY_11_ADDR + Core_1 Entry 11 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_12_ADDR + Core_1 Entry 12 address configuration Register + 0x42C + 0x20 + + + CORE_1_ENTRY_12_ADDR + Core_1 Entry 12 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_13_ADDR + Core_1 Entry 13 address configuration Register + 0x430 + 0x20 + + + CORE_1_ENTRY_13_ADDR + Core_1 Entry 13 address from WORLD1 to WORLD0 + 0 + 32 + read-write + + + + + Core_1_ENTRY_CHECK + Core_1 Entry check configuration Register + 0x47C + 0x20 + 0x00000002 + + + CORE_1_ENTRY_CHECK + This filed is used to enable entry address check + 1 + 13 + read-write + + + + + Core_1_STATUSTABLE1 + Status register of world switch of entry 1 + 0x480 + 0x20 + + + CORE_1_FROM_WORLD_1 + This bit is used to confirm world before enter entry 1 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_1 + This filed is used to confirm in which entry before enter entry 1 + 1 + 4 + read-write + + + CORE_1_CURRENT_1 + This bit is used to confirm whether the current state is in entry 1 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE2 + Status register of world switch of entry 2 + 0x484 + 0x20 + + + CORE_1_FROM_WORLD_2 + This bit is used to confirm world before enter entry 2 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_2 + This filed is used to confirm in which entry before enter entry 2 + 1 + 4 + read-write + + + CORE_1_CURRENT_2 + This bit is used to confirm whether the current state is in entry 2 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE3 + Status register of world switch of entry 3 + 0x488 + 0x20 + + + CORE_1_FROM_WORLD_3 + This bit is used to confirm world before enter entry 3 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_3 + This filed is used to confirm in which entry before enter entry 3 + 1 + 4 + read-write + + + CORE_1_CURRENT_3 + This bit is used to confirm whether the current state is in entry 3 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE4 + Status register of world switch of entry 4 + 0x48C + 0x20 + + + CORE_1_FROM_WORLD_4 + This bit is used to confirm world before enter entry 4 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_4 + This filed is used to confirm in which entry before enter entry 4 + 1 + 4 + read-write + + + CORE_1_CURRENT_4 + This bit is used to confirm whether the current state is in entry 4 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE5 + Status register of world switch of entry 5 + 0x490 + 0x20 + + + CORE_1_FROM_WORLD_5 + This bit is used to confirm world before enter entry 5 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_5 + This filed is used to confirm in which entry before enter entry 5 + 1 + 4 + read-write + + + CORE_1_CURRENT_5 + This bit is used to confirm whether the current state is in entry 5 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE6 + Status register of world switch of entry 6 + 0x494 + 0x20 + + + CORE_1_FROM_WORLD_6 + This bit is used to confirm world before enter entry 6 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_6 + This filed is used to confirm in which entry before enter entry 6 + 1 + 4 + read-write + + + CORE_1_CURRENT_6 + This bit is used to confirm whether the current state is in entry 6 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE7 + Status register of world switch of entry 7 + 0x498 + 0x20 + + + CORE_1_FROM_WORLD_7 + This bit is used to confirm world before enter entry 7 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_7 + This filed is used to confirm in which entry before enter entry 7 + 1 + 4 + read-write + + + CORE_1_CURRENT_7 + This bit is used to confirm whether the current state is in entry 7 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE8 + Status register of world switch of entry 8 + 0x49C + 0x20 + + + CORE_1_FROM_WORLD_8 + This bit is used to confirm world before enter entry 8 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_8 + This filed is used to confirm in which entry before enter entry 8 + 1 + 4 + read-write + + + CORE_1_CURRENT_8 + This bit is used to confirm whether the current state is in entry 8 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE9 + Status register of world switch of entry 9 + 0x4A0 + 0x20 + + + CORE_1_FROM_WORLD_9 + This bit is used to confirm world before enter entry 9 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_9 + This filed is used to confirm in which entry before enter entry 9 + 1 + 4 + read-write + + + CORE_1_CURRENT_9 + This bit is used to confirm whether the current state is in entry 9 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE10 + Status register of world switch of entry 10 + 0x4A4 + 0x20 + + + CORE_1_FROM_WORLD_10 + This bit is used to confirm world before enter entry 10 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_10 + This filed is used to confirm in which entry before enter entry 10 + 1 + 4 + read-write + + + CORE_1_CURRENT_10 + This bit is used to confirm whether the current state is in entry 10 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE11 + Status register of world switch of entry 11 + 0x4A8 + 0x20 + + + CORE_1_FROM_WORLD_11 + This bit is used to confirm world before enter entry 11 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_11 + This filed is used to confirm in which entry before enter entry 11 + 1 + 4 + read-write + + + CORE_1_CURRENT_11 + This bit is used to confirm whether the current state is in entry 11 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE12 + Status register of world switch of entry 12 + 0x4AC + 0x20 + + + CORE_1_FROM_WORLD_12 + This bit is used to confirm world before enter entry 12 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_12 + This filed is used to confirm in which entry before enter entry 12 + 1 + 4 + read-write + + + CORE_1_CURRENT_12 + This bit is used to confirm whether the current state is in entry 12 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE13 + Status register of world switch of entry 13 + 0x4B0 + 0x20 + + + CORE_1_FROM_WORLD_13 + This bit is used to confirm world before enter entry 13 + 0 + 1 + read-write + + + CORE_1_FROM_ENTRY_13 + This filed is used to confirm in which entry before enter entry 13 + 1 + 4 + read-write + + + CORE_1_CURRENT_13 + This bit is used to confirm whether the current state is in entry 13 + 5 + 1 + read-write + + + + + Core_1_STATUSTABLE_CURRENT + Status register of statustable current + 0x4FC + 0x20 + + + CORE_1_STATUSTABLE_CURRENT + This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1 + 1 + 13 + read-write + + + + + Core_1_MESSAGE_ADDR + Clear writer_buffer write address configuration register + 0x500 + 0x20 + + + CORE_1_MESSAGE_ADDR + This field is used to set address that need to write when enter WORLD0 + 0 + 32 + read-write + + + + + Core_1_MESSAGE_MAX + Clear writer_buffer write number configuration register + 0x504 + 0x20 + + + CORE_1_MESSAGE_MAX + This filed is used to set the max value of clear write_buffer + 0 + 4 + read-write + + + + + Core_1_MESSAGE_PHASE + Clear writer_buffer status register + 0x508 + 0x20 + + + CORE_1_MESSAGE_MATCH + This bit indicates whether the check is successful + 0 + 1 + read-only + + + CORE_1_MESSAGE_EXPECT + This field indicates the data to be written next time + 1 + 4 + read-only + + + CORE_1_MESSAGE_DATAPHASE + If this bit is 1, it means that is checking clear write_buffer operation, and is checking data + 5 + 1 + read-only + + + CORE_1_MESSAGE_ADDRESSPHASE + If this bit is 1, it means that is checking clear write_buffer operation, and is checking address. + 6 + 1 + read-only + + + + + Core_1_World_TRIGGER_ADDR + Core_1 trigger address configuration Register + 0x540 + 0x20 + + + CORE_1_WORLD_TRIGGER_ADDR + This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1 + 0 + 32 + read-write + + + + + Core_1_World_PREPARE + Core_1 prepare world configuration Register + 0x544 + 0x20 + + + CORE_1_WORLD_PREPARE + This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1 + 0 + 2 + read-write + + + + + Core_1_World_UPDATE + Core_1 configuration update register + 0x548 + 0x20 + + + CORE_1_UPDATE + This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_1_World_Cancel + Core_1 configuration cancel register + 0x54C + 0x20 + + + CORE_1_WORLD_CANCEL + This field is used to cancel switch world configuration,if the trigger address and update configuration complete,can use this register to cancel world switch. can write any value, the hardware only checks the write operation of this register and does not case about its value + 0 + 32 + write-only + + + + + Core_1_World_IRam0 + Core_1 Iram0 world register + 0x550 + 0x20 + + + CORE_1_WORLD_IRAM0 + this field is used to read current world of Iram0 bus + 0 + 2 + read-write + + + + + Core_1_World_DRam0_PIF + Core_1 dram0 and PIF world register + 0x554 + 0x20 + + + CORE_1_WORLD_DRAM0_PIF + this field is used to read current world of Dram0 bus and PIF bus + 0 + 2 + read-write + + + + + Core_1_World_Phase + Core_0 world status register + 0x558 + 0x20 + + + CORE_1_WORLD_PHASE + This bit indicates whether is preparing to switch to WORLD1,1 means value. + 0 + 1 + read-only + + + + + Core_1_NMI_MASK_ENABLE + Core_1 NMI mask enable register + 0x580 + 0x20 + + + CORE_1_NMI_MASK_ENABLE + this field is used to set NMI mask, it can write any value, when write this register,the hardware start masking NMI interrupt + 0 + 32 + write-only + + + + + Core_1_NMI_MASK_TRIGGER_ADDR + Core_1 NMI mask trigger addr register + 0x584 + 0x20 + + + CORE_1_NMI_MASK_TRIGGER_ADDR + this field to used to set trigger address + 0 + 32 + read-write + + + + + Core_1_NMI_MASK_DISABLE + Core_1 NMI mask disable register + 0x588 + 0x20 + + + CORE_1_NMI_MASK_DISABLE + this field is used to disable NMI mask, it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask + 0 + 32 + write-only + + + + + Core_1_NMI_MASK_CANCLE + Core_1 NMI mask disable register + 0x58C + 0x20 + + + CORE_1_NMI_MASK_CANCEL + this field is used to cancel NMI mask disable function. + 0 + 32 + write-only + + + + + Core_1_NMI_MASK + Core_1 NMI mask register + 0x590 + 0x20 + + + CORE_1_NMI_MASK + this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + 0 + 1 + read-write + + + + + Core_1_NMI_MASK_PHASE + Core_1 NMI mask phase register + 0x594 + 0x20 + + + CORE_1_NMI_MASK_PHASE + this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked + 0 + 1 + read-only + + + + + + + XTS_AES + XTS-AES-128 Flash Encryption + XTS_AES + 0x600CC000 + + 0x0 + 0x60 + registers + + + + 16 + 0x4 + PLAIN_%s + Plaintext register %s + 0x0 + 0x20 + + + PLAIN_0 + Stores the nth 32-bit piece of plaintext. + 0 + 32 + read-write + + + + + LINESIZE + XTS-AES line-size register + 0x40 + 0x20 + + + LINESIZE + Configures the data size of one encryption. + 0 + 1 + read-write + + + + + DESTINATION + XTS-AES destination register + 0x44 + 0x20 + + + DESTINATION + Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM. + 0 + 1 + read-write + + + + + PHYSICAL_ADDRESS + physical address + 0x48 + 0x20 + + + PHYSICAL_ADDRESS + Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes. + 0 + 30 + read-write + + + + + TRIGGER + XTS-AES trigger register + 0x4C + 0x20 + + + TRIGGER + Write 1 to activate manual encryption. + 0 + 1 + write-only + + + + + RELEASE + XTS-AES release control register + 0x50 + 0x20 + + + RELEASE + Write 1 to grant SPI1 access to encrypted result. + 0 + 1 + write-only + + + + + DESTROY + XTS-AES destroy control register + 0x54 + 0x20 + + + DESTROY + Write 1 to destroy encrypted result. + 0 + 1 + write-only + + + + + STATE + XTS-AES status register + 0x58 + 0x20 + + + STATE + Those bits indicates the status of the Manual Encryption block. 0X0 (XTS_AES_IDLE): idle. 0X1 (XTS_AES_BUSY): busy with encryption. 0X2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_AVAILABLE) encrypted result is accessible and available to SPI. + 0 + 2 + read-only + + + + + DATE + XTS-AES version control register + 0x5C + 0x20 + 0x20200111 + + + DATE + Manual Encryption block version information. + 0 + 30 + read-write + + + + + + + \ No newline at end of file diff --git a/Software/fab-reader2-c/gdbinit b/Software/fab-reader2-c/gdbinit new file mode 100644 index 0000000..11d978e --- /dev/null +++ b/Software/fab-reader2-c/gdbinit @@ -0,0 +1,6 @@ +target remote :3333 +set remote hardware-watchpoint-limit 2 +mon reset halt +flushregs +thb app_main +c diff --git a/Software/fab-reader2-c/main/CMakeLists.txt b/Software/fab-reader2-c/main/CMakeLists.txt new file mode 100644 index 0000000..7e585fa --- /dev/null +++ b/Software/fab-reader2-c/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "fab-reader2.c" "pollingtagdetect.c" + INCLUDE_DIRS "." + REQUIRES "rfal") diff --git a/Software/fab-reader2-c/main/fab-reader2.c b/Software/fab-reader2-c/main/fab-reader2.c new file mode 100644 index 0000000..2d0c591 --- /dev/null +++ b/Software/fab-reader2-c/main/fab-reader2.c @@ -0,0 +1,102 @@ +#include +#include +#include + +#include "platform.h" +#include "st25R3911_interrupt.h" + +#include "pollingtagdetect.h" + +#define SPI_CLK 5 +#define SPI_MOSI 6 +#define SPI_MISO 7 + +#define ESP_INTR_FLAG_DEFAULT 0 + +portMUX_TYPE CommProtectLock = portMUX_INITIALIZER_UNLOCKED; + +static void gpio_isr_handler(void *arg) { + st25r3911Isr(); +} + +esp_err_t init_gpio(void) { + gpio_config_t io_conf = {}; + //disable interrupt + io_conf.intr_type = GPIO_INTR_DISABLE; + //set as output mode + io_conf.mode = GPIO_MODE_INPUT_OUTPUT; + //bit mask of the pins that you want to set,e.g.GPIO18/19 + io_conf.pin_bit_mask = (1ULL << ST25R391X_SS_PIN); + //disable pull-down mode + io_conf.pull_down_en = 0; + //disable pull-up mode + io_conf.pull_up_en = 0; + //configure GPIO with the given settings + esp_err_t ret = gpio_config(&io_conf); + ESP_ERROR_CHECK(ret); + + + //interrupt of rising edge + io_conf.intr_type = GPIO_INTR_POSEDGE; + //bit mask of the pins, use GPIO4/5 here + io_conf.pin_bit_mask = (1ULL << ST25R391X_INT_PIN); + //set as input mode + io_conf.mode = GPIO_MODE_INPUT; + //enable pull-up mode +// io_conf.pull_up_en = 1; + ret = gpio_config(&io_conf); + ESP_ERROR_CHECK(ret); + + + ret = gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT); + ESP_ERROR_CHECK(ret); + //hook isr handler for specific gpio pin + ret = gpio_isr_handler_add(ST25R391X_INT_PIN, gpio_isr_handler, NULL); + ESP_ERROR_CHECK(ret); + + return ret; +} + +esp_err_t init_spi(void) { + spi_bus_config_t buscfg = { + .miso_io_num=SPI_MISO, + .mosi_io_num=SPI_MOSI, + .sclk_io_num=SPI_CLK, + .quadwp_io_num=-1, + .quadhd_io_num=-1, + }; + esp_err_t ret = spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_CH_AUTO); + ESP_ERROR_CHECK(ret); + + spi_device_interface_config_t devcfg = { + .clock_speed_hz=SPI_MASTER_FREQ_8M, //Clock out at 4 MHz + .mode=1, //SPI mode 1 + .spics_io_num=-1, //CS pin + .queue_size=1, //We want to be able to queue 7 transactions at a time + }; + + spi_device_handle_t spi; + ret = spi_bus_add_device(SPI2_HOST, &devcfg, &spi); + ESP_ERROR_CHECK(ret); + st25r3911_spi_init(spi); + + return ret; +} + +_Noreturn static void cycle_task(void *arg) { + while (1) { + TagDetectCycle(); +// ESP_LOGI("cycle_task", "running tag detect cycle_task"); + } +} + +void app_main(void) { + ESP_ERROR_CHECK(init_gpio()); + ESP_LOGI("main", "init_gpio done"); + ESP_ERROR_CHECK(init_spi()); + ESP_LOGI("main", "init_spi done"); + ESP_ERROR_CHECK(TagDetectInit()); + ESP_LOGI("main", "TagDetectInit done"); + xTaskCreate(cycle_task, "cycle_task", 4096, NULL, tskIDLE_PRIORITY, NULL); + ESP_LOGI("main", "cycle_task sheduled"); +} diff --git a/Software/fab-reader2-c/main/idf_component.yml b/Software/fab-reader2-c/main/idf_component.yml new file mode 100644 index 0000000..4af0b4c --- /dev/null +++ b/Software/fab-reader2-c/main/idf_component.yml @@ -0,0 +1,17 @@ +## IDF Component Manager Manifest File +dependencies: +# espressif/esp-idf-cxx: "^1.0.0-beta" + ## Required IDF version + idf: + version: ">=4.4.0" + # # Put list of dependencies here + # # For components maintained by Espressif: + # component: "~1.0.0" + # # For 3rd party components: + # username/component: ">=1.0.0,<2.0.0" + # username2/component2: + # version: "~1.0.0" + # # For transient dependencies `public` flag can be set. + # # `public` flag doesn't have an effect dependencies of the `main` component. + # # All dependencies of `main` are public by default. + # public: true diff --git a/Software/fab-reader2-c/main/pollingtagdetect.c b/Software/fab-reader2-c/main/pollingtagdetect.c new file mode 100644 index 0000000..73d1838 --- /dev/null +++ b/Software/fab-reader2-c/main/pollingtagdetect.c @@ -0,0 +1,264 @@ +// +// Created by Kai Jan Kriegel on 17.10.22. +// + +#include "pollingtagdetect.h" +#include "rfal_nfc.h" +#include "utils.h" + + +/* P2P communication data */ +static uint8_t NFCID3[] = {0x01, 0xFE, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A}; +static uint8_t GB[] = {0x46, 0x66, 0x6d, 0x01, 0x01, 0x11, 0x02, 0x02, 0x07, 0x80, 0x03, 0x02, 0x00, 0x03, 0x04, 0x01, + 0x32, 0x07, 0x01, 0x03}; + +/* APDUs communication data */ +static uint8_t ndefSelectApp[] = {0x00, 0xA4, 0x04, 0x00, 0x07, 0xD2, 0x76, 0x00, 0x00, 0x85, 0x01, 0x01, 0x00}; +static uint8_t ccSelectFile[] = {0x00, 0xA4, 0x00, 0x0C, 0x02, 0xE1, 0x03}; +static uint8_t readBinary[] = {0x00, 0xB0, 0x00, 0x00, 0x0F}; + +typedef enum { + NOT_INIT = 0, /*!< Demo State: Not initialized */ + START_DISCOVERY = 1, /*!< Demo State: Start Discovery */ + DISCOVERY = 2 /*!< Demo State: Discovery */ +} TagDetectState; + + +static rfalNfcDiscoverParam discParam; +static TagDetectState state = NOT_INIT; + +void TagDetectAPDU(void); + +ReturnCode TagDetectTransceiveBlocking(uint8_t *txBuf, uint16_t txBufSize, uint8_t **rxData, uint16_t **rcvLen, uint32_t fwt); + +static void TagDetectNotify(rfalNfcState st) { + uint8_t devCnt; + rfalNfcDevice *dev; + + + if (st == RFAL_NFC_STATE_WAKEUP_MODE) { + platformLog("Wake Up mode started \r\n"); + } else if (st == RFAL_NFC_STATE_POLL_TECHDETECT) { + platformLog("Wake Up mode terminated. Polling for devices \r\n"); + } else if (st == RFAL_NFC_STATE_POLL_SELECT) { + /* Multiple devices were found, activate first of them */ + rfalNfcGetDevicesFound(&dev, &devCnt); + rfalNfcSelect(0); + + platformLog("Multiple Tags detected: %d \r\n", devCnt); + } +} + +esp_err_t TagDetectInit(void) { + ReturnCode err = rfalNfcInitialize(); + if (err == ERR_NONE) { + discParam.compMode = RFAL_COMPLIANCE_MODE_NFC; + discParam.devLimit = 1U; + + ST_MEMCPY(&discParam.nfcid3, NFCID3, sizeof(NFCID3)); + ST_MEMCPY(&discParam.GB, GB, sizeof(GB)); + discParam.GBLen = sizeof(GB); + + discParam.notifyCb = TagDetectNotify; + discParam.totalDuration = 1000U; + discParam.wakeupEnabled = false; + discParam.wakeupConfigDefault = true; + discParam.techs2Find = (RFAL_NFC_POLL_TECH_A | RFAL_NFC_POLL_TECH_B); + +#if defined(ST25R3911) || defined(ST25R3916) + discParam.techs2Find |= RFAL_NFC_POLL_TECH_AP2P; +#endif /* ST25R95 */ + state = START_DISCOVERY; + return ESP_OK; + } + return err; +} + + +/*! + ***************************************************************************** + * \brief Demo Cycle + * + * This function executes the demo state machine. + * It must be called periodically + ***************************************************************************** + */ +void TagDetectCycle(void) { + static rfalNfcDevice *nfcDevice; + + rfalNfcWorker(); /* Run RFAL worker periodically */ + + /*******************************************************************************/ + /* Check if USER button is pressed */ +// if (platformGpioIsLow(PLATFORM_USER_BUTTON_PORT, PLATFORM_USER_BUTTON_PIN)) { +// discParam.wakeupEnabled = !discParam.wakeupEnabled; /* enable/disable wakeup */ +// state = START_DISCOVERY; /* restart loop */ +// platformLog("Toggling Wake Up mode %s\r\n", discParam.wakeupEnabled ? "ON" : "OFF"); +// +// /* Debounce button */ +// while (platformGpioIsLow(PLATFORM_USER_BUTTON_PORT, PLATFORM_USER_BUTTON_PIN)); +// } + + + switch (state) { + /*******************************************************************************/ + case START_DISCOVERY: + +// platformLedOff(PLATFORM_LED_A_PORT, PLATFORM_LED_A_PIN); +// platformLedOff(PLATFORM_LED_B_PORT, PLATFORM_LED_B_PIN); +// platformLedOff(PLATFORM_LED_F_PORT, PLATFORM_LED_F_PIN); +// platformLedOff(PLATFORM_LED_V_PORT, PLATFORM_LED_V_PIN); +// platformLedOff(PLATFORM_LED_AP2P_PORT, PLATFORM_LED_AP2P_PIN); +// platformLedOff(PLATFORM_LED_FIELD_PORT, PLATFORM_LED_FIELD_PIN); + + rfalNfcDeactivate(false); + rfalNfcDiscover(&discParam); + platformLog("Discovery started \r\n"); + + state = DISCOVERY; + break; + + /*******************************************************************************/ + case DISCOVERY: + + if (rfalNfcIsDevActivated(rfalNfcGetState())) { + rfalNfcGetActiveDevice(&nfcDevice); + platformLog("Device activated. \r\n"); + switch (nfcDevice->type) { + /*******************************************************************************/ + case RFAL_NFC_LISTEN_TYPE_NFCA: + +// platformLedOn(PLATFORM_LED_A_PORT, PLATFORM_LED_A_PIN); + switch (nfcDevice->dev.nfca.type) { + case RFAL_NFCA_T1T: + platformLog("ISO14443A/Topaz (NFC-A T1T) TAG found. UID: %s\r\n", + hex2Str(nfcDevice->nfcid, nfcDevice->nfcidLen)); + break; + + case RFAL_NFCA_T4T: + platformLog("NFCA Passive ISO-DEP device found. UID: %s\r\n", + hex2Str(nfcDevice->nfcid, nfcDevice->nfcidLen)); + + TagDetectAPDU(); + break; + + case RFAL_NFCA_T4T_NFCDEP: + case RFAL_NFCA_NFCDEP: + platformLog("NFCA Passive P2P device found. NFCID: %s\r\n", + hex2Str(nfcDevice->nfcid, nfcDevice->nfcidLen)); + +// demoP2P(); + break; + + default: + platformLog("ISO14443A/NFC-A card found. UID: %s\r\n", + hex2Str(nfcDevice->nfcid, nfcDevice->nfcidLen)); + break; + } + break; + + /*******************************************************************************/ + case RFAL_NFC_LISTEN_TYPE_NFCB: + + platformLog("ISO14443B/NFC-B card found. UID: %s\r\n", + hex2Str(nfcDevice->nfcid, nfcDevice->nfcidLen)); +// platformLedOn(PLATFORM_LED_B_PORT, PLATFORM_LED_B_PIN); + + if (rfalNfcbIsIsoDepSupported(&nfcDevice->dev.nfcb)) { + TagDetectAPDU(); + } + break; + + /*******************************************************************************/ + default: + break; + } + + rfalNfcDeactivate(false); + platformLog("Device deactivated. \r\n"); + platformDelay(500); + state = START_DISCOVERY; + } + break; + + /*******************************************************************************/ + case NOT_INIT: + default: + platformLog("ERROR: Demo not initialized \r\n"); + break; + } +} + +/*! + ***************************************************************************** + * \brief Demo APDUs Exchange + * + * Example how to exchange a set of predefined APDUs with PICC. The NDEF + * application will be selected and then CC will be selected and read. + * + ***************************************************************************** + */ +void TagDetectAPDU(void) { + ReturnCode err; + uint16_t *rxLen; + uint8_t *rxData; + + + /* Exchange APDU: NDEF Tag Application Select command */ + err = TagDetectTransceiveBlocking(ndefSelectApp, sizeof(ndefSelectApp), &rxData, &rxLen, RFAL_FWT_NONE); + platformLog(" Select NDEF Application: %s Data: %s\r\n", (err != ERR_NONE) ? "FAIL" : "OK", + hex2Str(rxData, *rxLen)); + + if ((err == ERR_NONE) && rxData[0] == 0x90 && rxData[1] == 0x00) { + /* Exchange APDU: Select Capability Container File */ + err = TagDetectTransceiveBlocking(ccSelectFile, sizeof(ccSelectFile), &rxData, &rxLen, RFAL_FWT_NONE); + platformLog(" Select CC: %s Data: %s\r\n", (err != ERR_NONE) ? "FAIL" : "OK", hex2Str(rxData, *rxLen)); + + /* Exchange APDU: Read Capability Container File */ + err = TagDetectTransceiveBlocking(readBinary, sizeof(readBinary), &rxData, &rxLen, RFAL_FWT_NONE); + platformLog(" Read CC: %s Data: %s\r\n", (err != ERR_NONE) ? "FAIL" : "OK", hex2Str(rxData, *rxLen)); + } +} + + +/*! + ***************************************************************************** + * \brief Demo Blocking Transceive + * + * Helper function to send data in a blocking manner via the rfalNfc module + * + * \warning A protocol transceive handles long timeouts (several seconds), + * transmission errors and retransmissions which may lead to a long period of + * time where the MCU/CPU is blocked in this method. + * This is a demo implementation, for a non-blocking usage example please + * refer to the Examples available with RFAL + * + * \param[in] txBuf : data to be transmitted + * \param[in] txBufSize : size of the data to be transmited + * \param[out] rxData : location where the received data has been placed + * \param[out] rcvLen : number of data bytes received + * \param[in] fwt : FWT to be used (only for RF frame interface, + * otherwise use RFAL_FWT_NONE) + * + * + * \return ERR_PARAM : Invalid parameters + * \return ERR_TIMEOUT : Timeout error + * \return ERR_FRAMING : Framing error detected + * \return ERR_PROTO : Protocol error detected + * \return ERR_NONE : No error, activation successful + * + ***************************************************************************** + */ +ReturnCode +TagDetectTransceiveBlocking(uint8_t *txBuf, uint16_t txBufSize, uint8_t **rxData, uint16_t **rcvLen, uint32_t fwt) { + ReturnCode err; + + err = rfalNfcDataExchangeStart(txBuf, txBufSize, rxData, rcvLen, fwt); + if (err == ERR_NONE) { + do { + rfalNfcWorker(); + err = rfalNfcDataExchangeGetStatus(); + } while (err == ERR_BUSY); + } + return err; +} diff --git a/Software/fab-reader2-c/main/pollingtagdetect.h b/Software/fab-reader2-c/main/pollingtagdetect.h new file mode 100644 index 0000000..84cbe35 --- /dev/null +++ b/Software/fab-reader2-c/main/pollingtagdetect.h @@ -0,0 +1,21 @@ +// +// Created by Kai Jan Kriegel on 17.10.22. +// + +#ifndef FAB_READER2_C_POLLINGTAGDETECT_H +#define FAB_READER2_C_POLLINGTAGDETECT_H + +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +esp_err_t TagDetectInit(void); +void TagDetectCycle(void); + +#ifdef __cplusplus +} +#endif + +#endif //FAB_READER2_C_POLLINGTAGDETECT_H diff --git a/Software/fab-reader2-c/sdkconfig b/Software/fab-reader2-c/sdkconfig new file mode 100644 index 0000000..8def02d --- /dev/null +++ b/Software/fab-reader2-c/sdkconfig @@ -0,0 +1,1401 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET_ARCH_XTENSA=y +CONFIG_IDF_TARGET="esp32s3" +CONFIG_IDF_TARGET_ESP32S3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009 + +# +# SDK tool configuration +# +CONFIG_SDK_TOOLPREFIX="xtensa-esp32s3-elf-" +# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set +# end of SDK tool configuration + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# end of Build type + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=3 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_SUPPORTS_RSA=y +CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +# end of Security features + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_OCT_FLASH is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_120M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y +# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +# CONFIG_PARTITION_TABLE_CUSTOM is not set +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +CONFIG_COMPILER_CXX_EXCEPTIONS=y +CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE=0 +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# ESP-ASIO +# +# CONFIG_ASIO_SSL_SUPPORT is not set +# end of ESP-ASIO + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +# end of Bluetooth + +# +# CoAP Configuration +# +CONFIG_COAP_MBEDTLS_PSK=y +# CONFIG_COAP_MBEDTLS_PKI is not set +# CONFIG_COAP_MBEDTLS_DEBUG is not set +CONFIG_COAP_LOG_DEFAULT_LEVEL=0 +# end of CoAP Configuration + +# +# Driver configurations +# + +# +# ADC configuration +# +# CONFIG_ADC_FORCE_XPD_FSM is not set +CONFIG_ADC_DISABLE_DAC=y +# end of ADC configuration + +# +# MCPWM configuration +# +# CONFIG_MCPWM_ISR_IN_IRAM is not set +# end of MCPWM configuration + +# +# SPI configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI configuration + +# +# TWAI configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# end of TWAI configuration + +# +# UART configuration +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of UART configuration + +# +# GDMA Configuration +# +# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# end of GDMA Configuration +# end of Driver configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ESP32S3-Specific +# +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160 + +# +# Cache config +# +CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y +# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y +CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP is not set +# CONFIG_ESP32S3_DATA_CACHE_16KB is not set +CONFIG_ESP32S3_DATA_CACHE_32KB=y +# CONFIG_ESP32S3_DATA_CACHE_64KB is not set +CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000 +# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set +CONFIG_ESP32S3_DATA_CACHE_8WAYS=y +CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32 +# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set +# end of Cache config + +# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set +# CONFIG_ESP32S3_TRAX is not set +CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set +CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32S3_DEBUG_OCDAWARE=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP32S3_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000 +# CONFIG_ESP32S3_NO_BLOBS is not set +# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set +# end of ESP32S3-Specific + +# +# ADC-Calibration +# +# end of ADC-Calibration + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_SPI_ETHERNET_W5500 is not set +# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set +# CONFIG_ETH_USE_OPENETH is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +# CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4 +# end of MAC Config + +# +# Sleep Config +# +# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set +CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y +CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU=y +# end of Sleep Config + +# +# RTC Clock Config +# +CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB=y +# end of RTC Clock Config +# end of Hardware Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1536 +CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y +CONFIG_ESP_IPC_ISR_ENABLE=y +# end of IPC (Inter-Processor Call) + +# +# LCD and Touch Panel +# + +# +# LCD Peripheral Configuration +# +CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32 +# CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set +# end of LCD Peripheral Configuration +# end of LCD and Touch Panel + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y +# end of ESP NETIF Adapter + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +CONFIG_ESP_PHY_ENABLE_USB=y +# end of PHY + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y +CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y +# end of Power Management + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP System Settings +# +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y + +# +# Memory protection +# +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_USB_CDC is not set +# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_MULTIPLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_INT_WDT_CHECK_CPU1=y +CONFIG_ESP_TASK_WDT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y +# end of ESP System Settings + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_ENABLED=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set +# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set +CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y +# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set +CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 +# end of Wi-Fi + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +# end of FAT Filesystem support + +# +# Modbus configuration +# +CONFIG_FMB_COMM_MODE_TCP_EN=y +CONFIG_FMB_TCP_PORT_DEFAULT=502 +CONFIG_FMB_TCP_PORT_MAX_CONN=5 +CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20 +CONFIG_FMB_COMM_MODE_RTU_EN=y +CONFIG_FMB_COMM_MODE_ASCII_EN=y +CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_FMB_QUEUE_LENGTH=20 +CONFIG_FMB_PORT_TASK_STACK_SIZE=4096 +CONFIG_FMB_SERIAL_BUF_SIZE=256 +CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 +CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 +CONFIG_FMB_PORT_TASK_PRIO=10 +# CONFIG_FMB_PORT_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_FMB_PORT_TASK_AFFINITY_CPU0=y +# CONFIG_FMB_PORT_TASK_AFFINITY_CPU1 is not set +CONFIG_FMB_PORT_TASK_AFFINITY=0x0 +CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y +CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233 +CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_FMB_CONTROLLER_STACK_SIZE=4096 +CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20 +# CONFIG_FMB_TIMER_PORT_ENABLED is not set +# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set +# end of Modbus configuration + +# +# FreeRTOS +# +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +CONFIG_FREERTOS_HZ=1000 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set +# CONFIG_FREERTOS_ASSERT_DISABLE is not set +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +# CONFIG_FREERTOS_LEGACY_HOOKS is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +# CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +# CONFIG_HAL_ASSERTION_SILIENT is not set +# CONFIG_HAL_ASSERTION_ENABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# end of Heap memory debugging + +# +# jsmn +# +# CONFIG_JSMN_PARENT_LINKS is not set +# CONFIG_JSMN_STRICT is not set +# end of jsmn + +# +# libsodium +# +# end of libsodium + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +# CONFIG_LWIP_NETIF_API is not set +# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV6=y +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v2.28.x related +# +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +# end of mbedTLS v2.28.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +# CONFIG_MBEDTLS_CMAC_C is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y +CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +CONFIG_MBEDTLS_RC4_DISABLED=y +# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set +# CONFIG_MBEDTLS_RC4_ENABLED is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 +CONFIG_MDNS_TASK_PRIORITY=1 +CONFIG_MDNS_TASK_STACK_SIZE=4096 +# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_MDNS_TASK_AFFINITY_CPU0=y +# CONFIG_MDNS_TASK_AFFINITY_CPU1 is not set +CONFIG_MDNS_TASK_AFFINITY=0x0 +CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000 +# CONFIG_MDNS_STRICT_MODE is not set +CONFIG_MDNS_TIMER_PERIOD_MS=100 +# CONFIG_MDNS_NETWORKING_SOCKET is not set +CONFIG_MDNS_MULTIPLE_INSTANCE=y +# end of mDNS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +# end of Newlib + +# +# NVS +# +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# end of NVS + +# +# OpenSSL +# +# CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ERROR_STACK=y +# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set +CONFIG_OPENSSL_ASSERT_EXIT=y +# end of OpenSSL + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set +# end of OpenThread + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y +# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set +# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +# CONFIG_SPI_FLASH_ROM_IMPL is not set +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set +# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# end of Websocket +# end of TCP Transport + +# +# TinyUSB Stack +# +# CONFIG_TINYUSB is not set +# end of TinyUSB Stack + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# USB-OTG +# +CONFIG_USB_OTG_SUPPORTED=y +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256 +CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y +# CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set +# CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set +# end of USB-OTG + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y +# end of Wi-Fi Provisioning Manager + +# +# Supplicant +# +CONFIG_WPA_MBEDTLS_CRYPTO=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_SUITE_B_192 is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# CONFIG_WPA_MBO_SUPPORT is not set +# CONFIG_WPA_DPP_SUPPORT is not set +# end of Supplicant +# end of Component config + +# +# Compatibility options +# +# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set +# end of Compatibility options + +# Deprecated options for backward compatibility +CONFIG_TOOLPREFIX="xtensa-esp32s3-elf-" +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +# CONFIG_MONITOR_BAUD_9600B is not set +# CONFIG_MONITOR_BAUD_57600B is not set +CONFIG_MONITOR_BAUD_115200B=y +# CONFIG_MONITOR_BAUD_230400B is not set +# CONFIG_MONITOR_BAUD_921600B is not set +# CONFIG_MONITOR_BAUD_2MB is not set +# CONFIG_MONITOR_BAUD_OTHER is not set +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 +CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 +CONFIG_CXX_EXCEPTIONS=y +CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE=0 +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_DISABLE_GCC8_WARNINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +CONFIG_ADC2_DISABLE_DAC=y +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +# CONFIG_ESP_SYSTEM_PD_FLASH is not set +CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y +CONFIG_IPC_TASK_STACK_SIZE=1536 +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y +# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set +CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y +# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP32S2_PANIC_GDBSTUB is not set +CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART=y +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set +CONFIG_TIMER_TASK_STACK_SIZE=3584 +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_MB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y +CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233 +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +# CONFIG_MB_TIMER_PORT_ENABLED is not set +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_L2_TO_L3_COPY is not set +# CONFIG_USE_ONLY_LWIP_SELECT is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=12 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +# CONFIG_USB_ENABLED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# End of deprecated options diff --git a/Software/fab-reader2-c/sdkconfig.old b/Software/fab-reader2-c/sdkconfig.old new file mode 100644 index 0000000..ff98e11 --- /dev/null +++ b/Software/fab-reader2-c/sdkconfig.old @@ -0,0 +1,1602 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y +CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_LEDC_CHANNEL_NUM=8 +CONFIG_SOC_LEDC_TIMER_BIT_WIDE_NUM=14 +CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y +CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 +CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 +CONFIG_SOC_ADC_SUPPORTED=y +CONFIG_SOC_PCNT_SUPPORTED=y +CONFIG_SOC_WIFI_SUPPORTED=y +CONFIG_SOC_TWAI_SUPPORTED=y +CONFIG_SOC_GDMA_SUPPORTED=y +CONFIG_SOC_LCDCAM_SUPPORTED=y +CONFIG_SOC_MCPWM_SUPPORTED=y +CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y +CONFIG_SOC_CACHE_SUPPORT_WRAP=y +CONFIG_SOC_ULP_SUPPORTED=y +CONFIG_SOC_RISCV_COPROC_SUPPORTED=y +CONFIG_SOC_BT_SUPPORTED=y +CONFIG_SOC_USB_OTG_SUPPORTED=y +CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y +CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y +CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y +CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y +CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y +CONFIG_SOC_SDMMC_HOST_SUPPORTED=y +CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y +CONFIG_SOC_RTC_MEM_SUPPORTED=y +CONFIG_SOC_PSRAM_DMA_CAPABLE=y +CONFIG_SOC_XT_WDT_SUPPORTED=y +CONFIG_SOC_I2S_SUPPORTED=y +CONFIG_SOC_RMT_SUPPORTED=y +CONFIG_SOC_SDM_SUPPORTED=y +CONFIG_SOC_SYSTIMER_SUPPORTED=y +CONFIG_SOC_SUPPORT_COEXISTENCE=y +CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y +CONFIG_SOC_AES_SUPPORTED=y +CONFIG_SOC_MPI_SUPPORTED=y +CONFIG_SOC_SHA_SUPPORTED=y +CONFIG_SOC_HMAC_SUPPORTED=y +CONFIG_SOC_DIG_SIGN_SUPPORTED=y +CONFIG_SOC_FLASH_ENC_SUPPORTED=y +CONFIG_SOC_SECURE_BOOT_SUPPORTED=y +CONFIG_SOC_MEMPROT_SUPPORTED=y +CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y +CONFIG_SOC_XTAL_SUPPORT_40M=y +CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG=y +CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_ARBITER_SUPPORTED=y +CONFIG_SOC_ADC_FILTER_SUPPORTED=y +CONFIG_SOC_ADC_MONITOR_SUPPORTED=y +CONFIG_SOC_ADC_DMA_SUPPORTED=y +CONFIG_SOC_ADC_PERIPH_NUM=2 +CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10 +CONFIG_SOC_ADC_ATTEN_NUM=4 +CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2 +CONFIG_SOC_ADC_PATT_LEN_MAX=24 +CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 +CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 +CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 +CONFIG_SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256=y +CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y +CONFIG_SOC_APB_BACKUP_DMA=y +CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y +CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 +CONFIG_SOC_CPU_CORES_NUM=2 +CONFIG_SOC_CPU_INTR_NUM=32 +CONFIG_SOC_CPU_HAS_FPU=y +CONFIG_SOC_CPU_BREAKPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINT_SIZE=64 +CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=4096 +CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 +CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 +CONFIG_SOC_GDMA_GROUPS=y +CONFIG_SOC_GDMA_PAIRS_PER_GROUP=5 +CONFIG_SOC_GDMA_SUPPORT_PSRAM=y +CONFIG_SOC_GDMA_PSRAM_MIN_ALIGN=16 +CONFIG_SOC_GPIO_PORT=1 +CONFIG_SOC_GPIO_PIN_COUNT=49 +CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y +CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y +CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x1FFFFFFFFFFFF +CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x0001FFFFFC000000 +CONFIG_SOC_GPIO_SUPPORT_SLP_SWITCH=y +CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE=y +CONFIG_SOC_I2C_NUM=2 +CONFIG_SOC_I2C_FIFO_LEN=32 +CONFIG_SOC_I2C_SUPPORT_SLAVE=y +CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y +CONFIG_SOC_I2C_SUPPORT_XTAL=y +CONFIG_SOC_I2C_SUPPORT_RTC=y +CONFIG_SOC_I2S_NUM=2 +CONFIG_SOC_I2S_HW_VERSION_2=y +CONFIG_SOC_I2S_SUPPORTS_PCM=y +CONFIG_SOC_I2S_SUPPORTS_PDM=y +CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y +CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y +CONFIG_SOC_I2S_SUPPORTS_PDM_CODEC=y +CONFIG_SOC_I2S_SUPPORTS_TDM=y +CONFIG_SOC_MCPWM_GROUPS=2 +CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3 +CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3 +CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3 +CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y +CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3 +CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3 +CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y +CONFIG_SOC_PCNT_GROUPS=y +CONFIG_SOC_PCNT_UNITS_PER_GROUP=4 +CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2 +CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2 +CONFIG_SOC_RMT_GROUPS=1 +CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8 +CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 +CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y +CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y +CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y +CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y +CONFIG_SOC_RMT_SUPPORT_XTAL=y +CONFIG_SOC_RMT_SUPPORT_RC_FAST=y +CONFIG_SOC_RMT_SUPPORT_APB=y +CONFIG_SOC_RMT_SUPPORT_DMA=y +CONFIG_SOC_LCD_I80_SUPPORTED=y +CONFIG_SOC_LCD_RGB_SUPPORTED=y +CONFIG_SOC_LCD_I80_BUSES=1 +CONFIG_SOC_LCD_RGB_PANELS=1 +CONFIG_SOC_LCD_I80_BUS_WIDTH=16 +CONFIG_SOC_LCD_RGB_DATA_WIDTH=16 +CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV=y +CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=549 +CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTCIO_PIN_COUNT=22 +CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y +CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y +CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y +CONFIG_SOC_SDM_GROUPS=y +CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8 +CONFIG_SOC_SPI_PERIPH_NUM=3 +CONFIG_SOC_SPI_MAX_CS_NUM=6 +CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPI_SUPPORT_DDRCLK=y +CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y +CONFIG_SOC_SPI_SUPPORT_CD_SIG=y +CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y +CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y +CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y +CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y +CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 +CONFIG_SOC_SPI_SUPPORT_OCT=y +CONFIG_SOC_MEMSPI_SRC_FREQ_120M=y +CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y +CONFIG_SOC_SPIRAM_SUPPORTED=y +CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 +CONFIG_SOC_SYSTIMER_ALARM_NUM=3 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 +CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y +CONFIG_SOC_SYSTIMER_INT_LEVEL=y +CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y +CONFIG_SOC_TIMER_GROUPS=2 +CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2 +CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 +CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y +CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y +CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4 +CONFIG_SOC_TOUCH_VERSION_2=y +CONFIG_SOC_TOUCH_SENSOR_NUM=15 +CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3 +CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED=y +CONFIG_SOC_TOUCH_PAD_THRESHOLD_MAX=0x1FFFFF +CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF +CONFIG_SOC_UART_NUM=3 +CONFIG_SOC_UART_FIFO_LEN=128 +CONFIG_SOC_UART_BITRATE_MAX=5000000 +CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y +CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y +CONFIG_SOC_UART_SUPPORT_APB_CLK=y +CONFIG_SOC_UART_SUPPORT_RTC_CLK=y +CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y +CONFIG_SOC_UART_REQUIRE_CORE_RESET=y +CONFIG_SOC_USB_PERIPH_NUM=y +CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 +CONFIG_SOC_SHA_SUPPORT_DMA=y +CONFIG_SOC_SHA_SUPPORT_RESUME=y +CONFIG_SOC_SHA_GDMA=y +CONFIG_SOC_SHA_SUPPORT_SHA1=y +CONFIG_SOC_SHA_SUPPORT_SHA224=y +CONFIG_SOC_SHA_SUPPORT_SHA256=y +CONFIG_SOC_SHA_SUPPORT_SHA384=y +CONFIG_SOC_SHA_SUPPORT_SHA512=y +CONFIG_SOC_SHA_SUPPORT_SHA512_224=y +CONFIG_SOC_SHA_SUPPORT_SHA512_256=y +CONFIG_SOC_SHA_SUPPORT_SHA512_T=y +CONFIG_SOC_RSA_MAX_BIT_LEN=4096 +CONFIG_SOC_AES_SUPPORT_DMA=y +CONFIG_SOC_AES_GDMA=y +CONFIG_SOC_AES_SUPPORT_AES_128=y +CONFIG_SOC_AES_SUPPORT_AES_256=y +CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_CPU_PD=y +CONFIG_SOC_PM_SUPPORT_TAGMEM_PD=y +CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y +CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y +CONFIG_SOC_SECURE_BOOT_V2_RSA=y +CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 +CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y +CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y +CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64 +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y +CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16 +CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=256 +CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 +CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 +CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y +CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE=y +CONFIG_SOC_SPI_MEM_SUPPORT_TIME_TUNING=y +CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y +CONFIG_SOC_COEX_HW_PTI=y +CONFIG_SOC_SDMMC_USE_GPIO_MATRIX=y +CONFIG_SOC_SDMMC_NUM_SLOTS=2 +CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y +CONFIG_SOC_WIFI_HW_TSF=y +CONFIG_SOC_WIFI_FTM_SUPPORT=y +CONFIG_SOC_WIFI_GCMP_SUPPORT=y +CONFIG_SOC_WIFI_WAPI_SUPPORT=y +CONFIG_SOC_WIFI_CSI_SUPPORT=y +CONFIG_SOC_WIFI_MESH_SUPPORT=y +CONFIG_SOC_BLE_SUPPORTED=y +CONFIG_SOC_BLE_MESH_SUPPORTED=y +CONFIG_SOC_TWAI_BRP_MIN=2 +CONFIG_SOC_TWAI_BRP_MAX=16384 +CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET_ARCH_XTENSA=y +CONFIG_IDF_TARGET_ARCH="xtensa" +CONFIG_IDF_TARGET="esp32s3" +CONFIG_IDF_TARGET_ESP32S3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009 + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# CONFIG_APP_REPRODUCIBLE_BUILD is not set +# CONFIG_APP_NO_BLOBS is not set +# end of Build type + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=3 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_PREFERRED=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +CONFIG_SECURE_ROM_DL_MODE_ENABLED=y +# end of Security features + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +CONFIG_ESP_ROM_HAS_CRC_LE=y +CONFIG_ESP_ROM_HAS_CRC_BE=y +CONFIG_ESP_ROM_HAS_MZ_CRC32=y +CONFIG_ESP_ROM_HAS_JPEG_DECODE=y +CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y +CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y +CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=4 +CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y +CONFIG_ESP_ROM_GET_CLK_FREQ=y +CONFIG_ESP_ROM_HAS_HAL_WDT=y +CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y +CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_OCT_FLASH is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_120M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +# CONFIG_PARTITION_TABLE_CUSTOM is not set +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +# CONFIG_APPTRACE_DEST_UART1 is not set +# CONFIG_APPTRACE_DEST_UART2 is not set +# CONFIG_APPTRACE_DEST_USB_CDC is not set +CONFIG_APPTRACE_DEST_UART_NONE=y +CONFIG_APPTRACE_UART_TASK_PRIO=1 +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +# end of Bluetooth + +# +# Driver Configurations +# + +# +# Legacy ADC Configuration +# +# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set + +# +# Legacy ADC Calibration Configuration +# +# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy ADC Calibration Configuration +# end of Legacy ADC Configuration + +# +# SPI Configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI Configuration + +# +# TWAI Configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# end of TWAI Configuration + +# +# Temperature sensor Configuration +# +# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set +# end of Temperature sensor Configuration + +# +# UART Configuration +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of UART Configuration + +# +# GPIO Configuration +# +# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set +# end of GPIO Configuration + +# +# Sigma Delta Modulator Configuration +# +# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_SDM_ENABLE_DEBUG_LOG is not set +# end of Sigma Delta Modulator Configuration + +# +# GPTimer Configuration +# +# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set +# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set +# end of GPTimer Configuration + +# +# PCNT Configuration +# +# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_PCNT_ISR_IRAM_SAFE is not set +# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set +# end of PCNT Configuration + +# +# RMT Configuration +# +# CONFIG_RMT_ISR_IRAM_SAFE is not set +# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_RMT_ENABLE_DEBUG_LOG is not set +# end of RMT Configuration + +# +# MCPWM Configuration +# +# CONFIG_MCPWM_ISR_IRAM_SAFE is not set +# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set +# end of MCPWM Configuration + +# +# I2S Configuration +# +# CONFIG_I2S_ISR_IRAM_SAFE is not set +# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_I2S_ENABLE_DEBUG_LOG is not set +# end of I2S Configuration +# end of Driver Configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ADC and ADC Calibration +# +# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set +# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set +# end of ADC and ADC Calibration + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_SPI_ETHERNET_W5500 is not set +# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set +# CONFIG_ETH_USE_OPENETH is not set +# CONFIG_ETH_TRANSMIT_MUTEX is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set +# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +# CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4 +# end of MAC Config + +# +# Sleep Config +# +# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set +CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y +CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU=y +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000 +# end of Sleep Config + +# +# RTC Clock Config +# +CONFIG_RTC_CLK_SRC_INT_RC=y +# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_RTC_CLK_CAL_CYCLES=1024 +CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB=y +# end of RTC Clock Config + +# +# Peripheral Control +# +# CONFIG_PERIPH_CTRL_FUNC_IN_IRAM is not set +# end of Peripheral Control + +# +# MMU Config +# +CONFIG_MMU_PAGE_SIZE_64KB=y +CONFIG_MMU_PAGE_MODE="64KB" +CONFIG_MMU_PAGE_SIZE=0x10000 +# end of MMU Config + +# +# GDMA Configuration +# +# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# end of GDMA Configuration + +# +# Main XTAL Config +# +CONFIG_XTAL_FREQ_40=y +CONFIG_XTAL_FREQ=40 +# end of Main XTAL Config +# end of Hardware Settings + +# +# LCD and Touch Panel +# + +# +# LCD Touch Drivers are maintained in the IDF Component Registry +# + +# +# LCD Peripheral Configuration +# +CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32 +# CONFIG_LCD_ENABLE_DEBUG_LOG is not set +# CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set +# CONFIG_LCD_RGB_RESTART_IN_VSYNC is not set +# end of LCD Peripheral Configuration +# end of LCD and Touch Panel + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +# CONFIG_ESP_NETIF_L2_TAP is not set +# CONFIG_ESP_NETIF_BRIDGE_EN is not set +# end of ESP NETIF Adapter + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +CONFIG_ESP_PHY_REDUCE_TX_POWER=y +CONFIG_ESP_PHY_ENABLE_USB=y +# end of PHY + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y +CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y +# end of Power Management + +# +# ESP PSRAM +# +# CONFIG_SPIRAM is not set +# end of ESP PSRAM + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP System Settings +# +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160 + +# +# Cache config +# +CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y +# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y +CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32 +# CONFIG_ESP32S3_DATA_CACHE_16KB is not set +CONFIG_ESP32S3_DATA_CACHE_32KB=y +# CONFIG_ESP32S3_DATA_CACHE_64KB is not set +CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000 +# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set +CONFIG_ESP32S3_DATA_CACHE_8WAYS=y +CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32 +# end of Cache config + +# +# Memory +# +# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set +# end of Memory + +# +# Trace memory +# +# CONFIG_ESP32S3_TRAX is not set +CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0 +# end of Trace memory + +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_USB_CDC is not set +# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_MULTIPLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_INT_WDT_CHECK_CPU1=y +CONFIG_ESP_TASK_WDT_EN=y +CONFIG_ESP_TASK_WDT_INIT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_DEBUG_OCDAWARE=y +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y + +# +# Brownout Detector +# +CONFIG_ESP_BROWNOUT_DET=y +CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP_BROWNOUT_DET_LVL=7 +# end of Brownout Detector + +CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y +# end of ESP System Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1536 +CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y +CONFIG_ESP_IPC_ISR_ENABLE=y +# end of IPC (Inter-Processor Call) + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_ENABLED=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set +# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set +CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y +# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set +CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 +# end of Wi-Fi + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +CONFIG_FATFS_VOLUME_COUNT=2 +# CONFIG_FATFS_SECTOR_512 is not set +# CONFIG_FATFS_SECTOR_1024 is not set +# CONFIG_FATFS_SECTOR_2048 is not set +CONFIG_FATFS_SECTOR_4096=y +CONFIG_FATFS_SECTORS_PER_CLUSTER_1=y +# CONFIG_FATFS_SECTORS_PER_CLUSTER_2 is not set +# CONFIG_FATFS_SECTORS_PER_CLUSTER_4 is not set +# CONFIG_FATFS_SECTORS_PER_CLUSTER_8 is not set +# CONFIG_FATFS_SECTORS_PER_CLUSTER_16 is not set +# CONFIG_FATFS_SECTORS_PER_CLUSTER_32 is not set +# CONFIG_FATFS_SECTORS_PER_CLUSTER_64 is not set +# CONFIG_FATFS_SECTORS_PER_CLUSTER_128 is not set +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_AUTO_TYPE=y +# CONFIG_FATFS_FAT12 is not set +# CONFIG_FATFS_FAT16 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +# end of FAT Filesystem support + +# +# FreeRTOS +# + +# +# Kernel +# +# CONFIG_FREERTOS_SMP is not set +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_HZ=1000 +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +# CONFIG_FREERTOS_USE_IDLE_HOOK is not set +# CONFIG_FREERTOS_USE_TICK_HOOK is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +# end of Kernel + +# +# Port +# +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +# end of Port + +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +# CONFIG_HAL_ASSERTION_SILENT is not set +# CONFIG_HAL_ASSERTION_ENABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 +CONFIG_HAL_WDT_USE_ROM_IMPL=y +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# end of Heap memory debugging + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +# CONFIG_LWIP_NETIF_API is not set +# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV6=y +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y +# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v3.x related +# +# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +# end of mbedTLS v3.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +# CONFIG_MBEDTLS_CMAC_C is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +# CONFIG_MBEDTLS_DHM_C is not set +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +# CONFIG_MQTT_PROTOCOL_5 is not set +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y +# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set +# end of Newlib + +# +# NVS +# +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# end of NVS + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set +# end of OpenThread + +# +# Protocomm +# +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y +# end of Protocomm + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y +# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set +# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_HAS_ROM_IMPL=y +# CONFIG_SPI_FLASH_ROM_IMPL is not set +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# SPI Flash behavior when brownout +# +CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y +CONFIG_SPI_FLASH_BROWNOUT_RESET=y +# end of SPI Flash behavior when brownout + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# CONFIG_WS_DYNAMIC_BUFFER is not set +# end of Websocket +# end of TCP Transport + +# +# Ultra Low Power (ULP) Co-processor +# +# CONFIG_ULP_COPROC_ENABLED is not set +# end of Ultra Low Power (ULP) Co-processor + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# USB-OTG +# +CONFIG_USB_OTG_SUPPORTED=y +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256 +CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y +# CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set +# CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set +# end of USB-OTG + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y +# end of Wi-Fi Provisioning Manager + +# +# Supplicant +# +CONFIG_WPA_MBEDTLS_CRYPTO=y +CONFIG_WPA_MBEDTLS_TLS_CLIENT=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_SUITE_B_192 is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# CONFIG_WPA_MBO_SUPPORT is not set +# CONFIG_WPA_DPP_SUPPORT is not set +# CONFIG_WPA_11R_SUPPORT is not set +# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# end of Supplicant +# end of Component config diff --git a/Software/fab-reader2/out.bin b/Software/fab-reader2/out.bin new file mode 100644 index 0000000000000000000000000000000000000000..185435947e204c422256707ea4aee3f8e204a2a5 GIT binary patch literal 490256 zcmd2^31E}u`Tue>P10~FLXhhNQHwyE9+XlG4RQ!t0Xe)to3u&Wj5Mi93dM^c4Bdv; zbc*xB$#gn5adYY>)1t!MR!W)Hg7KDEs523YMoK5Ep|~0d zcE*A&{zNcvrrH$`s`Ene&ai*|yzMTp9c)=ayEfRpGPWn}UYad5DGi(9Zr89*vGjJy`&3fQ>C!UWk zwtK7LK8)v9&l)9euZZo_js+}Fds56^B;ALwb29d;hjQqTe5UXX(K zp&%cq#UBm_1FCO{mW6e7U6FM$e`o1rpBjy*e$}@)8VUN;wf=AyGF5lFEEw+!C$gPJ zRNwqq%y6nG0V&t}YdOQ|p zo&JMaO~c?8pT{PGw<$F1xC>@3i{T1pCbcF!`URRNahX%)(*Q z#-!plZS2$Bx#=$4VA@2p>;83E8Q-VqW`j1_deZJZaA!IUvoOqz@Mxy&8?@y&wMr^p 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z+TX+^_P@b`Uh;V;zw9Xc=^5j*teI(1y|>!Cr#n3|DdTNe_F(&o+6Xik5>T|)& z!gzZf+fIv`V+n5?Tk%;2YaYJA9_z1EHyRsRK}H{gK) literal 0 HcmV?d00001 diff --git a/Software/fab-reader2/src/main.rs b/Software/fab-reader2/src/main.rs index d6c2834..8d2ebd2 100644 --- a/Software/fab-reader2/src/main.rs +++ b/Software/fab-reader2/src/main.rs @@ -8,22 +8,22 @@ use embedded_hal::digital::v2::OutputPin; use esp_idf_sys::esp_sleep_pd_domain_t_ESP_PD_DOMAIN_VDDSDIO; use esp_idf_sys::EspError; -use esp_idf_hal::{delay, gpio}; use esp_idf_hal::gpio::{GpioPin, Unknown}; use esp_idf_hal::prelude::*; use esp_idf_hal::spi; +use esp_idf_hal::{delay, gpio}; use anyhow::Result; -use embedded_graphics::{Drawable, mono_font}; use embedded_graphics::mono_font::iso_8859_15::FONT_10X20; use embedded_graphics::mono_font::MonoTextStyle; use embedded_graphics::pixelcolor::BinaryColor; use embedded_graphics::prelude::Point; use embedded_graphics::text::Text; +use embedded_graphics::{mono_font, Drawable}; -use pervasive_epd::E2266CS0Cx; use pervasive_epd::graphics::{Display, VarDisplay}; use pervasive_epd::prelude::*; +use pervasive_epd::E2266CS0Cx; fn main() -> Result<()> { // Temporary. Will disappear once ESP-IDF 4.4 is released, but for now it is necessary to call this function once, @@ -33,6 +33,10 @@ fn main() -> Result<()> { let peripherals = Peripherals::take().unwrap(); let pins = peripherals.pins; + // NFC related pins + let nfc_cs = pins.gpio4.into_output()?; + let nfc_irq = pins.gpio15.into_input()?; + // EPD related pins let epd_cs = pins.gpio38.into_output()?; let epd_busy = pins.gpio41.into_input()?; @@ -76,7 +80,7 @@ fn main() -> Result<()> { epd_rst, &mut delay::Ets, ) - .unwrap(); + .unwrap(); // Use display graphics from embedded-graphics let mut buffer = vec![ E2266CS0Cx::DEFAULT_BACKGROUND_COLOR.get_byte_value(); diff --git a/Software/fab-reader2/st25r3911b/Cargo.toml b/Software/fab-reader2/st25r3911b/Cargo.toml index 3246593..6430023 100644 --- a/Software/fab-reader2/st25r3911b/Cargo.toml +++ b/Software/fab-reader2/st25r3911b/Cargo.toml @@ -8,9 +8,8 @@ edition = "2021" [dependencies] embedded-hal = { version ="0.2.7", features = ["unproven"] } embedded-svc = "0.22.1" -esp-idf-svc = { version = "0.42.1", features = ["alloc" ] } -esp-idf-hal = "0.38.1" anyhow = "1.0.65" +array-concat = "0.5.1" [build-dependencies] anyhow = "1.0.65" diff --git a/Software/fab-reader2/st25r3911b/src/analogConfig.rs b/Software/fab-reader2/st25r3911b/src/analogConfig.rs deleted file mode 100644 index bbe3443..0000000 --- a/Software/fab-reader2/st25r3911b/src/analogConfig.rs +++ /dev/null @@ -1,143 +0,0 @@ -use crate::constants::*; -use crate::Register; - -/* Helpers */ -// Register Helpers for 1 to 13 sets -const fn MODE_ENTRY_1_REG(mode: u32, r0: u32, m0: u8, v0: u8) -> [u8; 7] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 1, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0] -} - -const fn MODE_ENTRY_2_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8) -> [u8; 11] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 2, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1] -} - -const fn MODE_ENTRY_3_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8) -> [u8; 15] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 3, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2] -} - -const fn MODE_ENTRY_4_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8) -> [u8; 19] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 4, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3] -} - -const fn MODE_ENTRY_5_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8) -> [u8; 23] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 5, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4] -} - -const fn MODE_ENTRY_6_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8) -> [u8; 27] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 6, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5] -} - -const fn MODE_ENTRY_7_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8) -> [u8; 31] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 7, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6] -} - -const fn MODE_ENTRY_8_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8) -> [u8; 35] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 8, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7] -} - -const fn MODE_ENTRY_9_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8) -> [u8; 39] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 9, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8] -} - -const fn MODE_ENTRY_10_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8) -> [u8; 43] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 10, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9] -} - -const fn MODE_ENTRY_11_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8) -> [u8; 47] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 11, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10] -} - -const fn MODE_ENTRY_12_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8, r11: u32, m11: u8, v11: u8) -> [u8; 51] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 12, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10, (r11 << 8) as u8, (r11 & 0xFF) as u8, m11, v11] -} - -const fn MODE_ENTRY_13_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8, r11: u32, m11: u8, v11: u8, r12: u32, m12: u8, v12: u8) -> [u8; 55] { - [(mode << 8) as u8, (mode & 0xFF) as u8, 13, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10, (r11 << 8) as u8, (r11 & 0xFF) as u8, m11, v11, (r12 << 8) as u8, (r12 & 0xFF) as u8, m12, v12] -} - -const AM_MOD_DRIVER_LEVEL_DEFAULT: u8 = 0xb9; - -const ANALOG_CONFIG_LUT_SIZE: u32 = 87; /*!< Maximum number of Configuration IDs in the Loop Up Table */ -const ANALOG_CONFIG_LUT_NOT_FOUND: u32 = 0xFF; /*!< Index value indicating no Configuration IDs found */ - -const ANALOG_CONFIG_TBL_SIZE: u32 = 1024; /*!< Maximum number of Register-Mask-Value in the Setting List */ - - -const ANALOG_CONFIG_POLL_LISTEN_MODE_MASK: u32 = 0x8000; /*!< Mask bit of Poll Mode in Analog Configuration ID */ -const ANALOG_CONFIG_TECH_MASK: u32 = 0x7F00; /*!< Mask bits for Technology in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_MASK: u32 = 0x00F0; /*!< Mask bits for Bit rate in Analog Configuration ID */ -const ANALOG_CONFIG_DIRECTION_MASK: u32 = 0x0003; /*!< Mask bits for Direction in Analog Configuration ID */ -const ANALOG_CONFIG_CHIP_SPECIFIC_MASK: u32 = 0x00FF; /*!< Mask bits for Chip Specific Technology */ - -const ANALOG_CONFIG_POLL_LISTEN_MODE_SHIFT: u32 = 15; /*!< Shift value of Poll Mode in Analog Configuration ID */ -const ANALOG_CONFIG_TECH_SHIFT: u32 = 8; /*!< Shift value for Technology in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_SHIFT: u32 = 4; /*!< Shift value for Technology in Analog Configuration ID */ -const ANALOG_CONFIG_DIRECTION_SHIFT: u32 = 0; /*!< Shift value for Direction in Analog Configuration ID */ - -const ANALOG_CONFIG_POLL: u32 = 0x0000; /*!< Poll Mode bit setting in Analog Configuration ID */ -const ANALOG_CONFIG_LISTEN: u32 = 0x8000; /*!< Listen Mode bit setting in Analog Configuration ID */ - -const ANALOG_CONFIG_TECH_CHIP: u32 = 0x0000; /*!< Chip-Specific bit setting in Analog Configuration ID */ -const ANALOG_CONFIG_TECH_NFCA: u32 = 0x0100; /*!< NFC-A Technology bits setting in Analog Configuration ID */ -const ANALOG_CONFIG_TECH_NFCB: u32 = 0x0200; /*!< NFC-B Technology bits setting in Analog Configuration ID */ -const ANALOG_CONFIG_TECH_NFCF: u32 = 0x0400; /*!< NFC-F Technology bits setting in Analog Configuration ID */ -const ANALOG_CONFIG_TECH_AP2P: u32 = 0x0800; /*!< AP2P Technology bits setting in Analog Configuration ID */ -const ANALOG_CONFIG_TECH_NFCV: u32 = 0x1000; /*!< NFC-V Technology bits setting in Analog Configuration ID */ -const ANALOG_CONFIG_TECH_RFU: u32 = 0x2000; /*!< RFU for Technology bits */ - -const ANALOG_CONFIG_BITRATE_COMMON: u32 = 0x0000; /*!< Common settings for all bit rates in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_106: u32 = 0x0010; /*!< 106kbits/s settings in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_212: u32 = 0x0020; /*!< 212kbits/s settings in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_424: u32 = 0x0030; /*!< 424kbits/s settings in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_848: u32 = 0x0040; /*!< 848kbits/s settings in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_1695: u32 = 0x0050; /*!< 1695kbits/s settings in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_3390: u32 = 0x0060; /*!< 3390kbits/s settings in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_6780: u32 = 0x0070; /*!< 6780kbits/s settings in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_1OF4: u32 = 0x00C0; /*!< 1 out of 4 for NFC-V setting in Analog Configuration ID */ -const ANALOG_CONFIG_BITRATE_1OF256: u32 = 0x00D0; /*!< 1 out of 256 for NFC-V setting in Analog Configuration ID */ - -const ANALOG_CONFIG_NO_DIRECTION: u32 = 0x0000; /*!< No direction setting in Analog Conf ID (Chip Specific only) */ -const ANALOG_CONFIG_TX: u32 = 0x0001; /*!< Transmission bit setting in Analog Configuration ID */ -const ANALOG_CONFIG_RX: u32 = 0x0002; /*!< Reception bit setting in Analog Configuration ID */ -const ANALOG_CONFIG_ANTICOL: u32 = 0x0003; /*!< Anticollision setting in Analog Configuration ID */ - -const ANALOG_CONFIG_CHIP_INIT: u32 = 0x0000; /*!< Chip-Specific event: Startup;Reset;Initialize */ -const ANALOG_CONFIG_CHIP_DEINIT: u32 = 0x0001; /*!< Chip-Specific event: Deinitialize */ -const ANALOG_CONFIG_CHIP_FIELD_ON: u32 = 0x0002; /*!< Chip-Specific event: Field On */ -const ANALOG_CONFIG_CHIP_FIELD_OFF: u32 = 0x0003; /*!< Chip-Specific event: Field Off */ -const ANALOG_CONFIG_CHIP_WAKEUP_ON: u32 = 0x0004; /*!< Chip-Specific event: Wake-up On */ -const ANALOG_CONFIG_CHIP_WAKEUP_OFF: u32 = 0x0005; /*!< Chip-Specific event: Wake-up Off */ -const ANALOG_CONFIG_CHIP_LISTEN_ON: u32 = 0x0006; /*!< Chip-Specific event: Listen On */ -const ANALOG_CONFIG_CHIP_LISTEN_OFF: u32 = 0x0007; /*!< Chip-Specific event: Listen Off */ -const ANALOG_CONFIG_CHIP_POLL_COMMON: u32 = 0x0008; /*!< Chip-Specific event: Poll common */ -const ANALOG_CONFIG_CHIP_LISTEN_COMMON: u32 = 0x0009; /*!< Chip-Specific event: Listen common */ - -const ANALOG_CONFIG_UPDATE_LAST: u32 = 0x00; /*!< Value indicating Last configuration set during update */ -const ANALOG_CONFIG_UPDATE_MORE: u32 = 0x01; /*!< Value indicating More configuration set coming during update */ - -const DEFAULT_ANALOG_CONFIG: Vec = MODE_ENTRY_10_REG(ANALOG_CONFIG_TECH_CHIP | ANALOG_CONFIG_CHIP_INIT, - Register::OperationControl as u32, 0x30, 0x10, //Default to AM - Register::IOConfiguration1 as u32, 0x06, 0x06, //MCUCLK: HF clk off - Register::IOConfiguration1 as u32, IOConfiguration1Bits::mask_out_cl as u8 | IOConfiguration1Bits::lf_clk_off as u8, 0x07, // MCUCLK: LF clk off - Register::IOConfiguration2 as u32, 0x18, 0x18, // pull downs - Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::mask_rg2_pm as u8, 0x1 << ReceiverConfiguration4Mask::shift_rg2_pm as u8, //increase digitizer windows for PM - Register::AnntenaCalibrationTarget as u32, 0xFF, 0x80, // 90 deg, - Register::AnntenaCalibrationControl as u32, 0xF8, 0x00, // trim value from calibrate antenna - Register::AMModulationDepthControl as u32, AMModulationDepthControlConstans::am_s as u8, AMModulationDepthControlConstans::am_s as u8, // AM modulated level is defined by RFO AM Modulated Level Def Reg, fixed setting, no automatic adjustment - Register::ExternalFieldDetectorThreshold as u32, EXT_FIELD_DET_TRG_MASK, ExternalFieldDetectorThresholdTrgVoltage::trg_75mV as u8, - Register::ExternalFieldDetectorThreshold as u32, EXT_FIELD_DET_RFE_MASK, ExternalFieldDetectorThresholdRfeVoltage::rfe_75mV as u8 -).into_iter().collect(); - -pub(crate) struct AnalogConfigMgmt { - config_tbl: Box<[u8]>, - ready: bool, -} - -impl AnalogConfigMgmt { - pub fn new_default() -> Self { - Self { - config_tbl: DEFAULT_ANALOG_CONFIG.into_boxed_slice(), - ready: true, - } - } -} \ No newline at end of file diff --git a/Software/fab-reader2/st25r3911b/src/analog_config.rs b/Software/fab-reader2/st25r3911b/src/analog_config.rs new file mode 100644 index 0000000..88f4b6b --- /dev/null +++ b/Software/fab-reader2/st25r3911b/src/analog_config.rs @@ -0,0 +1,437 @@ +use array_concat::*; + +use crate::constants::*; +use crate::Register; + +/* Helpers */ +// Register Helpers for 1 to 13 sets +const fn mode_entry_1_reg(mode: u32, r0: u32, m0: u8, v0: u8) -> [u8; 7] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 1, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0] +} + +const fn mode_entry_2_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8) -> [u8; 11] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 2, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1] +} + +const fn mode_entry_3_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8) -> [u8; 15] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 3, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2] +} + +const fn mode_entry_4_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8) -> [u8; 19] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 4, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3] +} + +const fn mode_entry_5_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8) -> [u8; 23] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 5, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4] +} + +const fn mode_entry_6_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8) -> [u8; 27] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 6, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5] +} + +const fn mode_entry_7_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8) -> [u8; 31] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 7, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6] +} + +const fn mode_entry_8_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8) -> [u8; 35] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 8, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7] +} + +const fn mode_entry_9_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8) -> [u8; 39] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 9, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8] +} + +const fn mode_entry_10_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8) -> [u8; 43] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 10, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9] +} + +const fn mode_entry_11_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8) -> [u8; 47] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 11, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10] +} + +const fn mode_entry_12_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8, r11: u32, m11: u8, v11: u8) -> [u8; 51] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 12, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10, (r11 << 8) as u8, (r11 & 0xFF) as u8, m11, v11] +} + +const fn mode_entry_13_reg(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8, r11: u32, m11: u8, v11: u8, r12: u32, m12: u8, v12: u8) -> [u8; 55] { + [(mode << 8) as u8, (mode & 0xFF) as u8, 13, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10, (r11 << 8) as u8, (r11 & 0xFF) as u8, m11, v11, (r12 << 8) as u8, (r12 & 0xFF) as u8, m12, v12] +} + +const AM_MOD_DRIVER_LEVEL_DEFAULT: u8 = 0xb9; + +const ANALOG_CONFIG_LUT_SIZE: u32 = 87; /* Maximum number of Configuration IDs in the Loop Up Table */ +const ANALOG_CONFIG_LUT_NOT_FOUND: u32 = 0xFF; /* Index value indicating no Configuration IDs found */ + +const ANALOG_CONFIG_TBL_SIZE: u32 = 1024; /* Maximum number of Register-Mask-Value in the Setting List */ + + +const ANALOG_CONFIG_POLL_LISTEN_MODE_MASK: u32 = 0x8000; /* Mask bit of Poll Mode in Analog Configuration ID */ +const ANALOG_CONFIG_TECH_MASK: u32 = 0x7F00; /* Mask bits for Technology in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_MASK: u32 = 0x00F0; /* Mask bits for Bit rate in Analog Configuration ID */ +const ANALOG_CONFIG_DIRECTION_MASK: u32 = 0x0003; /* Mask bits for Direction in Analog Configuration ID */ +const ANALOG_CONFIG_CHIP_SPECIFIC_MASK: u32 = 0x00FF; /* Mask bits for Chip Specific Technology */ + +const ANALOG_CONFIG_POLL_LISTEN_MODE_SHIFT: u32 = 15; /* Shift value of Poll Mode in Analog Configuration ID */ +const ANALOG_CONFIG_TECH_SHIFT: u32 = 8; /* Shift value for Technology in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_SHIFT: u32 = 4; /* Shift value for Technology in Analog Configuration ID */ +const ANALOG_CONFIG_DIRECTION_SHIFT: u32 = 0; /* Shift value for Direction in Analog Configuration ID */ + +const ANALOG_CONFIG_POLL: u32 = 0x0000; /* Poll Mode bit setting in Analog Configuration ID */ +const ANALOG_CONFIG_LISTEN: u32 = 0x8000; /* Listen Mode bit setting in Analog Configuration ID */ + +const ANALOG_CONFIG_TECH_CHIP: u32 = 0x0000; /* Chip-Specific bit setting in Analog Configuration ID */ +const ANALOG_CONFIG_TECH_NFCA: u32 = 0x0100; /* NFC-A Technology bits setting in Analog Configuration ID */ +const ANALOG_CONFIG_TECH_NFCB: u32 = 0x0200; /* NFC-B Technology bits setting in Analog Configuration ID */ +const ANALOG_CONFIG_TECH_NFCF: u32 = 0x0400; /* NFC-F Technology bits setting in Analog Configuration ID */ +const ANALOG_CONFIG_TECH_AP2P: u32 = 0x0800; /* AP2P Technology bits setting in Analog Configuration ID */ +const ANALOG_CONFIG_TECH_NFCV: u32 = 0x1000; /* NFC-V Technology bits setting in Analog Configuration ID */ +const ANALOG_CONFIG_TECH_RFU: u32 = 0x2000; /* RFU for Technology bits */ + +const ANALOG_CONFIG_BITRATE_COMMON: u32 = 0x0000; /* Common settings for all bit rates in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_106: u32 = 0x0010; /* 106kbits/s settings in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_212: u32 = 0x0020; /* 212kbits/s settings in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_424: u32 = 0x0030; /* 424kbits/s settings in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_848: u32 = 0x0040; /* 848kbits/s settings in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_1695: u32 = 0x0050; /* 1695kbits/s settings in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_3390: u32 = 0x0060; /* 3390kbits/s settings in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_6780: u32 = 0x0070; /* 6780kbits/s settings in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_1OF4: u32 = 0x00C0; /* 1 out of 4 for NFC-V setting in Analog Configuration ID */ +const ANALOG_CONFIG_BITRATE_1OF256: u32 = 0x00D0; /* 1 out of 256 for NFC-V setting in Analog Configuration ID */ + +const ANALOG_CONFIG_NO_DIRECTION: u32 = 0x0000; /* No direction setting in Analog Conf ID (Chip Specific only) */ +const ANALOG_CONFIG_TX: u32 = 0x0001; /* Transmission bit setting in Analog Configuration ID */ +const ANALOG_CONFIG_RX: u32 = 0x0002; /* Reception bit setting in Analog Configuration ID */ +const ANALOG_CONFIG_ANTICOL: u32 = 0x0003; /* Anticollision setting in Analog Configuration ID */ + +const ANALOG_CONFIG_CHIP_INIT: u32 = 0x0000; /* Chip-Specific event: Startup;Reset;Initialize */ +const ANALOG_CONFIG_CHIP_DEINIT: u32 = 0x0001; /* Chip-Specific event: Deinitialize */ +const ANALOG_CONFIG_CHIP_FIELD_ON: u32 = 0x0002; /* Chip-Specific event: Field On */ +const ANALOG_CONFIG_CHIP_FIELD_OFF: u32 = 0x0003; /* Chip-Specific event: Field Off */ +const ANALOG_CONFIG_CHIP_WAKEUP_ON: u32 = 0x0004; /* Chip-Specific event: Wake-up On */ +const ANALOG_CONFIG_CHIP_WAKEUP_OFF: u32 = 0x0005; /* Chip-Specific event: Wake-up Off */ +const ANALOG_CONFIG_CHIP_LISTEN_ON: u32 = 0x0006; /* Chip-Specific event: Listen On */ +const ANALOG_CONFIG_CHIP_LISTEN_OFF: u32 = 0x0007; /* Chip-Specific event: Listen Off */ +const ANALOG_CONFIG_CHIP_POLL_COMMON: u32 = 0x0008; /* Chip-Specific event: Poll common */ +const ANALOG_CONFIG_CHIP_LISTEN_COMMON: u32 = 0x0009; /* Chip-Specific event: Listen common */ + +const ANALOG_CONFIG_UPDATE_LAST: u32 = 0x00; /* Value indicating Last configuration set during update */ +const ANALOG_CONFIG_UPDATE_MORE: u32 = 0x01; /* Value indicating More configuration set coming during update */ + +//****** Default Analog Configuration for Chip-Specific Reset. ******/ +const RESET_INIT: [u8; 43] = mode_entry_10_reg( + ANALOG_CONFIG_TECH_CHIP | ANALOG_CONFIG_CHIP_INIT, + Register::OperationControl as u32, 0x30, 0x10, //Default to AM + Register::IOConfiguration1 as u32, 0x06, 0x06, //MCUCLK: HF clk off + Register::IOConfiguration1 as u32, IOConfiguration1Bits::MaskOutCl as u8 | IOConfiguration1Bits::LfClkOff as u8, 0x07, // MCUCLK: LF clk off + Register::IOConfiguration2 as u32, 0x18, 0x18, // pull downs + Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::MaskRg2Pm as u8, 0x1 << ReceiverConfiguration4Mask::ShiftRg2Pm as u8, //increase digitizer windows for PM + Register::AnntenaCalibrationTarget as u32, 0xFF, 0x80, // 90 deg, + Register::AnntenaCalibrationControl as u32, 0xF8, 0x00, // trim value from calibrate antenna + Register::AMModulationDepthControl as u32, AMModulationDepthControlConstans::AmS as u8, AMModulationDepthControlConstans::AmS as u8, // AM modulated level is defined by RFO AM Modulated Level Def Reg, fixed setting, no automatic adjustment + Register::ExternalFieldDetectorThreshold as u32, EXT_FIELD_DET_TRG_MASK, ExternalFieldDetectorThresholdTrgVoltage::Trg75mV as u8, + Register::ExternalFieldDetectorThreshold as u32, EXT_FIELD_DET_RFE_MASK, ExternalFieldDetectorThresholdRfeVoltage::Rfe75mV as u8, +); + +//****** Default Analog Configuration for Poll NFC-A Rx. ******/ +const NFCA_TX_COMMON: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_TX, + Register::RFOAMModulationLevelDefinition as u32, 0xff, 0xf0, // Used for 848 TX: very high AM to keep wave shapes +); +const NFCA_TX_106: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_106 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, 0x00, // OOK +); +const NFCA_TX_212: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_212 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, 0x00, // OOK +); +const NFCA_TX_424: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_424 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, 0x00, // OOK +); +const NFCA_TX_848: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_848 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, 0x00, // OOK +); +const NFCA_TX_848_AUX: [u8; 11] = mode_entry_2_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_848 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, AuxDefinitionBits::TrAm as u8, // AM + Register::RFOAMModulationLevelDefinition as u32, 0xff, 0x00, // Used for 848 TX: very high AM to keep wave shapes +); + +//****** Default Analog Configuration for Poll NFC-A Rx. ******/ +const NFCA_RX_COMMON: [u8; 15] = mode_entry_3_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, 0xff, 0x18, + Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::MaskRg2Am as u8, 0x2 << ReceiverConfiguration4Mask::ShiftRg2Am as u8, //increase digitizer windows for AM + Register::AuxDefinition as u32, AuxDefinitionBits::RxTol as u8, 0x00, //rx_tol off +); +const NFCA_RX_106: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_106 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x00, +); +const NFCA_RX_212: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_212 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x04, +); +const NFCA_RX_424: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_424 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x22, +); +const NFCA_RX_848: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCA | ANALOG_CONFIG_BITRATE_848 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x22, +); + +//****** Default Analog Configuration for Poll NFC-B Tx. ******/ +const NFCB_TX_COMMON: [u8; 11] = mode_entry_2_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCB | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, AuxDefinitionBits::TrAm as u8, // AM + Register::RFOAMModulationLevelDefinition as u32, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT, //Fixed driver for AM level: -14% +); + +//****** Default Analog Configuration for Poll NFC-B Rx. ******/ +const NFCB_RX_COMMON: [u8; 15] = mode_entry_3_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCB | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, 0xff, 0x18, + Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::MaskRg2Am as u8, 0x2 << ReceiverConfiguration4Mask::ShiftRg2Am as u8, //increase digitizer windows for AM + Register::AuxDefinition as u32, AuxDefinitionBits::RxTol as u8, 0x00, //rx_tol off +); +const NFCB_RX_106: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCB | ANALOG_CONFIG_BITRATE_106 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x00, +); +const NFCB_RX_212: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCB | ANALOG_CONFIG_BITRATE_212 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x04, +); +const NFCB_RX_424: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCB | ANALOG_CONFIG_BITRATE_424 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x22, +); +const NFCB_RX_848: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCB | ANALOG_CONFIG_BITRATE_848 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x22, +); + +//****** Default Analog Configuration for Poll NFC-F Tx. ******/ +const NFCF_TX_COMMON: [u8; 11] = mode_entry_2_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCF | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, AuxDefinitionBits::TrAm as u8, // AM + Register::RFOAMModulationLevelDefinition as u32, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT, //Fixed driver for AM level: -14% +); + +//****** Default Analog Configuration for Poll NFC-F Rx. ******/ +const NFCF_RX_COMMON: [u8; 15] = mode_entry_3_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCF | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, 0xff, 0x18, + Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::MaskRg2Am as u8, 0x1 << ReceiverConfiguration4Mask::ShiftRg2Am as u8, //increase digitizer windows for AM + Register::AuxDefinition as u32, AuxDefinitionBits::RxTol as u8, AuxDefinitionBits::RxTol as u8, //rx_tol On as default +); +const NFCF_RX_212: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCF | ANALOG_CONFIG_BITRATE_212 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x13, /* dev. from data sheet: lp 300kKz */ +); +const NFCF_RX_424: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCF | ANALOG_CONFIG_BITRATE_424 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x0b, /* dev. from data sheet: lp 600kKz */ +); + +//****** Default Analog Configuration for Poll NFC-V Tx. ******/ +const NFCV_TX_COMMON: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCV | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, 0x00, // AM +); + +//****** Default Analog Configuration for Poll NFC-V Rx. ******/ +const NFCV_RX_COMMON: [u8; 19] = mode_entry_4_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_NFCV | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x0c, /* use filter settings from table 9: "Recommended for 424/484 kHz sub-carrier" */ + Register::ReceiverConfiguration3 as u32, 0xff, 0x18, + Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::MaskRg2Am as u8, 0x1 << ReceiverConfiguration4Mask::ShiftRg2Am as u8, //increase digitizer windows for AM + Register::AuxDefinition as u32, AuxDefinitionBits::RxTol as u8, AuxDefinitionBits::RxTol as u8, //rx_tol On as default +); + +//****** Default Analog Configuration for Poll AP2P Tx. ******/ +const AP2P_TX_COMMON: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_TX, + Register::RFOAMModulationLevelDefinition as u32, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT, +); +const AP2P_TX_106: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_106 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, 0x00, // OOK +); +const AP2P_TX_212: [u8; 11] = mode_entry_2_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_212 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, AuxDefinitionBits::TrAm as u8, // AM + Register::RFOAMModulationLevelDefinition as u32, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT, //Fixed driver for AM level: -14% +); +const AP2P_TX_424: [u8; 11] = mode_entry_2_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_424 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, AuxDefinitionBits::TrAm as u8, // AM + Register::RFOAMModulationLevelDefinition as u32, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT, //Fixed driver for AM level: -14% +); + +//****** Default Analog Configuration for Poll AP2P Rx. ******/ +const AP2P_RX_TECH: [u8; 19] = mode_entry_4_reg( + ANALOG_CONFIG_TECH_CHIP | ANALOG_CONFIG_CHIP_LISTEN_ON, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x45, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Bits::Lim as u8 | ReceiverConfiguration3Bits::RgNfc as u8, ReceiverConfiguration3Bits::Lim as u8 | ReceiverConfiguration3Bits::RgNfc as u8, + Register::AuxDefinition as u32, AuxDefinitionBits::RxTol as u8, AuxDefinitionBits::RxTol as u8, //rx_tol On as default + Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::MaskRg2Am as u8, 0x1 << ReceiverConfiguration4Mask::ShiftRg2Am as u8, //increase digitizer windows for AM +); +const AP2P_RX_COMMON: [u8; 19] = mode_entry_4_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x45, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Bits::Lim as u8 | ReceiverConfiguration3Bits::RgNfc as u8, ReceiverConfiguration3Bits::Lim as u8 | ReceiverConfiguration3Bits::RgNfc as u8, + Register::AuxDefinition as u32, AuxDefinitionBits::RxTol as u8, AuxDefinitionBits::RxTol as u8, //rx_tol On as default + Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::MaskRg2Am as u8, 0x1 << ReceiverConfiguration4Mask::ShiftRg2Am as u8, //increase digitizer windows for AM +); +const AP2P_RX_106: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_106 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Mask::MaskRg1Am as u8, 0xc0, +); +const AP2P_RX_212: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_212 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Mask::MaskRg1Am as u8, 0x00, +); +const AP2P_RX_424: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_POLL | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_424 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Mask::MaskRg1Am as u8, 0x00, +); + +//****** Default Analog Configuration for Listen AP2P Tx. ******/ +const AP2P_LTX_COMMON: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_LISTEN | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_TX, + Register::RFOAMModulationLevelDefinition as u32, 0xff, AM_MOD_DRIVER_LEVEL_DEFAULT, //Fixed driver for AM level: -14% +); +const AP2P_LTX_106: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_LISTEN | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_106 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, 0x00, // OOK +); +const AP2P_LTX_212: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_LISTEN | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_212 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, AuxDefinitionBits::TrAm as u8, // AM +); +const AP2P_LTX_424: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_LISTEN | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_424 | ANALOG_CONFIG_TX, + Register::AuxDefinition as u32, AuxDefinitionBits::TrAm as u8, AuxDefinitionBits::TrAm as u8, // AM +); + +//****** Default Analog Configuration for Listen AP2P Rx. ******/ +const AP2P_LRX_COMMON: [u8; 15] = mode_entry_3_reg( + ANALOG_CONFIG_LISTEN | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_COMMON | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration1 as u32, 0x7f, 0x45, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Bits::Lim as u8 | ReceiverConfiguration3Bits::RgNfc as u8, ReceiverConfiguration3Bits::Lim as u8 | ReceiverConfiguration3Bits::RgNfc as u8, + Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::MaskRg2Am as u8, 0x1 << ReceiverConfiguration4Mask::ShiftRg2Am as u8, //increase digitizer windows for AM +); +const AP2P_LRX_106: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_LISTEN | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_106 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Mask::MaskRg1Am as u8, 0xc0, +); +const AP2P_LRX_212: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_LISTEN | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_212 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Mask::MaskRg1Am as u8, 0x00, +); +const AP2P_LRX_424: [u8; 7] = mode_entry_1_reg( + ANALOG_CONFIG_LISTEN | ANALOG_CONFIG_TECH_AP2P | ANALOG_CONFIG_BITRATE_424 | ANALOG_CONFIG_RX, + Register::ReceiverConfiguration3 as u32, ReceiverConfiguration3Mask::MaskRg1Am as u8, 0x00, +); + +static DEFAULT_ANALOG_CONFIG: [u8; concat_arrays_size!( + RESET_INIT, + NFCA_TX_COMMON, + NFCA_TX_106, + NFCA_TX_212, + NFCA_TX_424, + NFCA_TX_848, + NFCA_TX_848_AUX, + NFCA_RX_COMMON, + NFCA_RX_106, + NFCA_RX_212, + NFCA_RX_424, + NFCA_RX_848, + NFCB_TX_COMMON, + NFCB_RX_COMMON, + NFCB_RX_106, + NFCB_RX_212, + NFCB_RX_424, + NFCB_RX_848, + NFCF_TX_COMMON, + NFCF_RX_COMMON, + NFCF_RX_212, + NFCF_RX_424, + NFCV_TX_COMMON, + NFCV_RX_COMMON, + AP2P_TX_COMMON, + AP2P_TX_106, + AP2P_TX_212, + AP2P_TX_424, + AP2P_RX_TECH, + AP2P_RX_COMMON, + AP2P_RX_106, + AP2P_RX_212, + AP2P_RX_424, + AP2P_LTX_COMMON, + AP2P_LTX_106, + AP2P_LTX_212, + AP2P_LTX_424, + AP2P_LRX_COMMON, + AP2P_LRX_106, + AP2P_LRX_212, + AP2P_LRX_424 +)] = concat_arrays!( + RESET_INIT, + NFCA_TX_COMMON, + NFCA_TX_106, + NFCA_TX_212, + NFCA_TX_424, + NFCA_TX_848, + NFCA_TX_848_AUX, + NFCA_RX_COMMON, + NFCA_RX_106, + NFCA_RX_212, + NFCA_RX_424, + NFCA_RX_848, + NFCB_TX_COMMON, + NFCB_RX_COMMON, + NFCB_RX_106, + NFCB_RX_212, + NFCB_RX_424, + NFCB_RX_848, + NFCF_TX_COMMON, + NFCF_RX_COMMON, + NFCF_RX_212, + NFCF_RX_424, + NFCV_TX_COMMON, + NFCV_RX_COMMON, + AP2P_TX_COMMON, + AP2P_TX_106, + AP2P_TX_212, + AP2P_TX_424, + AP2P_RX_TECH, + AP2P_RX_COMMON, + AP2P_RX_106, + AP2P_RX_212, + AP2P_RX_424, + AP2P_LTX_COMMON, + AP2P_LTX_106, + AP2P_LTX_212, + AP2P_LTX_424, + AP2P_LRX_COMMON, + AP2P_LRX_106, + AP2P_LRX_212, + AP2P_LRX_424 +); + +pub(crate) struct AnalogConfigMgmt { + config_tbl: Box<[u8]>, +} + +impl AnalogConfigMgmt { + pub fn new_default() -> Self { + Self { + config_tbl: Box::new(DEFAULT_ANALOG_CONFIG), + } + } +} \ No newline at end of file diff --git a/Software/fab-reader2/st25r3911b/src/constants.rs b/Software/fab-reader2/st25r3911b/src/constants.rs index 1f4d670..4acb68a 100644 --- a/Software/fab-reader2/st25r3911b/src/constants.rs +++ b/Software/fab-reader2/st25r3911b/src/constants.rs @@ -175,6 +175,20 @@ pub enum RegulatorControlMask { Rege = 0xf << 3, } +#[repr(u8)] +#[derive(PartialEq, Clone, Copy, Debug)] +pub enum AuxDefinitionBits { + MaskNfcN = 3 << 0, + NfcN0 = 1 << 0, + NfcN1 = 1 << 1, + RxTol = 1 << 2, + OokHr = 1 << 3, + EnFd = 1 << 4, + TrAm = 1 << 5, + Crc2Fifo = 1 << 6, + NoCrcRx = 1 << 7, +} + #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum IOConfiguration2Bits { @@ -189,13 +203,13 @@ pub enum IOConfiguration2Bits { #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum IOConfiguration1Bits { - lf_clk_off = 1 << 0, - out_cl0 = 1 << 1, - out_cl1 = 1 << 2, - mask_out_cl = 3 << 1, - osc = 1 << 3, - rfo2 = 1 << 6, - single = 1 << 7, + LfClkOff = 1 << 0, + OutCl0 = 1 << 1, + OutCl1 = 1 << 2, + MaskOutCl = 3 << 1, + Osc = 1 << 3, + Rfo2 = 1 << 6, + Single = 1 << 7, } const FIFO_LT: u8 = 1 << 4; @@ -203,8 +217,8 @@ const FIFO_LT: u8 = 1 << 4; #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum IOConfiguration1FIFOLt { - fifo_lt_32bytes = 0 << 4, - fifo_lt_16bytes = 1 << 4, + FifoLt32bytes = 0 << 4, + FifoLt16bytes = 1 << 4, } const FIFO_LR: u8 = 1 << 5; @@ -212,30 +226,52 @@ const FIFO_LR: u8 = 1 << 5; #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum IOConfiguration1FIFOLr { - fifo_lr_64bytes = 0 << 5, - fifo_lr_80bytes = 1 << 5, + FifoLr64bytes = 0 << 5, + FifoLr80bytes = 1 << 5, +} + +#[repr(u8)] +#[derive(PartialEq, Clone, Copy, Debug)] +pub enum ReceiverConfiguration3Mask { + ShiftRg1Pm = 2, + MaskRg1Pm = 0x7 << 2, + ShiftRg1Am = 5, + MaskRg1Am = 0x7 << 5, +} + +#[repr(u8)] +#[derive(PartialEq, Clone, Copy, Debug)] +pub enum ReceiverConfiguration3Bits { + RgNfc = 1 << 0, + Lim = 1 << 1, + Rg1Pm0 = 1 << 2, + Rg1Pm1 = 1 << 3, + Rg1Pm2 = 1 << 4, + Rg1Am0 = 1 << 5, + Rg1Am1 = 1 << 6, + Rg1Am2 = 1 << 7, } #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum ReceiverConfiguration4Mask { - shift_rg2_pm = 0, - mask_rg2_pm = 0xf << 0, - shift_rg2_am = 4, - mask_rg2_am = 0xf << 4, + ShiftRg2Pm = 0, + MaskRg2Pm = 0xf << 0, + ShiftRg2Am = 4, + MaskRg2Am = 0xf << 4, } #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum ReceiverConfiguration4Bits { - rg2_pm0 = 1 << 0, - rg2_pm1 = 1 << 1, - rg2_pm2 = 1 << 2, - rg2_pm3 = 1 << 3, - rg2_am0 = 1 << 4, - rg2_am1 = 1 << 5, - rg2_am2 = 1 << 6, - rg2_am3 = 1 << 7, + Rg2Pm0 = 1 << 0, + Rg2Pm1 = 1 << 1, + Rg2Pm2 = 1 << 2, + Rg2Pm3 = 1 << 3, + Rg2Am0 = 1 << 4, + Rg2Am1 = 1 << 5, + Rg2Am2 = 1 << 6, + Rg2Am3 = 1 << 7, } const AM_MOD_DEPTH_CONTROL_MASK: u8 = 0x3f << 1; @@ -244,14 +280,14 @@ const AM_MOD_DEPTH_CONTROL_SHIFT: u8 = 1; #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum AMModulationDepthControlConstans { - mod_8percent = 0xb << 1, - mod_10percent = 0xe << 1, - mod_14percent = 0x14 << 1, - mod_20percent = 0x20 << 1, - mod_25percent = 0x2a << 1, - mod_30percent = 0x37 << 1, - mod_33percent = 0x3f << 1, - am_s = 1 << 7, + Mod8percent = 0xb << 1, + Mod10percent = 0xe << 1, + Mod14percent = 0x14 << 1, + Mod20percent = 0x20 << 1, + Mod25percent = 0x2a << 1, + Mod30percent = 0x37 << 1, + Mod33percent = 0x3f << 1, + AmS = 1 << 7, } pub const EXT_FIELD_DET_RFE_MASK: u8 = 0x0f; @@ -259,54 +295,54 @@ pub const EXT_FIELD_DET_RFE_MASK: u8 = 0x0f; #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum ExternalFieldDetectorThresholdRfe { -rfe_t0 = 1<<0 , -rfe_t1 = 1<<1 , -rfe_t2 = 1<<2 , -rfe_t3 = 1<<3 , + RfeT0 = 1 << 0, + RfeT1 = 1 << 1, + RfeT2 = 1 << 2, + RfeT3 = 1 << 3, } #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum ExternalFieldDetectorThresholdRfeVoltage { - rfe_75mV = 0x00<<0 , - rfe_105mV = 0x01<<0 , - rfe_150mV = 0x02<<0 , - rfe_205mV = 0x03<<0 , - rfe_290mV = 0x04<<0 , - rfe_400mV = 0x05<<0 , - rfe_560mV = 0x06<<0 , - rfe_800mV = 0x07<<0 , - rfe_25mV = 0x08<<0 , - rfe_33mV = 0x09<<0 , - rfe_47mV = 0x0A<<0 , - rfe_64mV = 0x0B<<0 , - rfe_90mV = 0x0C<<0 , - rfe_125mV = 0x0D<<0 , - rfe_175mV = 0x0E<<0 , - rfe_250mV = 0x0F<<0 , + Rfe75mV = 0x00 << 0, + Rfe105mV = 0x01 << 0, + Rfe150mV = 0x02 << 0, + Rfe205mV = 0x03 << 0, + Rfe290mV = 0x04 << 0, + Rfe400mV = 0x05 << 0, + Rfe560mV = 0x06 << 0, + Rfe800mV = 0x07 << 0, + Rfe25mV = 0x08 << 0, + Rfe33mV = 0x09 << 0, + Rfe47mV = 0x0A << 0, + Rfe64mV = 0x0B << 0, + Rfe90mV = 0x0C << 0, + Rfe125mV = 0x0D << 0, + Rfe175mV = 0x0E << 0, + Rfe250mV = 0x0F << 0, } -pub const EXT_FIELD_DET_TRG_MASK: u8 = 0x07<<4; +pub const EXT_FIELD_DET_TRG_MASK: u8 = 0x07 << 4; #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum ExternalFieldDetectorThresholdTrg { - trg_l0 = 1<<4 , - trg_l1 = 1<<5 , - trg_l2 = 1<<6 , + TrgL0 = 1 << 4, + TrgL1 = 1 << 5, + TrgL2 = 1 << 6, } #[repr(u8)] #[derive(PartialEq, Clone, Copy, Debug)] pub enum ExternalFieldDetectorThresholdTrgVoltage { - trg_75mV = 0x00<<4 , - trg_105mV = 0x01<<4 , - trg_150mV = 0x02<<4 , - trg_205mV = 0x03<<4 , - trg_290mV = 0x04<<4 , - trg_400mV = 0x05<<4 , - trg_560mV = 0x06<<4 , - trg_800mV = 0x07<<4 , + Trg75mV = 0x00 << 4, + Trg105mV = 0x01 << 4, + Trg150mV = 0x02 << 4, + Trg205mV = 0x03 << 4, + Trg290mV = 0x04 << 4, + Trg400mV = 0x05 << 4, + Trg560mV = 0x06 << 4, + Trg800mV = 0x07 << 4, } #[repr(u8)] @@ -410,6 +446,89 @@ pub(crate) enum OperationMode { CmdMode = 3u32 << 6, } +#[repr(u8)] +#[derive(PartialEq, Clone, Copy, Debug)] +pub(crate) enum NfcState { + NotInit = 0, + Idle = 1, + StartDiscovery = 2, + WakeUpMode = 3, + PollTechDetect = 10, + PollColAvoidance = 11, + PollSelect = 12, + PollActivation = 13, + ListenTechDetect = 20, + ListenColAvoidance = 21, + ListenActivation = 22, + ListenSleep = 23, + Activated = 30, + DataExchange = 31, + DataExchangeDone = 33, + Deactivation = 34, +} + +/* RFAL Bit rates */ +#[derive(PartialEq, Clone, Copy, Debug)] +pub(crate) enum BitRate { + Br106 = 0, + /* Bit Rate 106 kbit/s (fc/128) */ + Br212 = 1, + /* Bit Rate 212 kbit/s (fc/64) */ + Br424 = 2, + /* Bit Rate 424 kbit/s (fc/32) */ + Br848 = 3, + /* Bit Rate 848 kbit/s (fc/16) */ + Br1695 = 4, + /* Bit Rate 1695 kbit/s (fc/8) */ + Br3390 = 5, + /* Bit Rate 3390 kbit/s (fc/4) */ + Br6780 = 6, + /* Bit Rate 6780 kbit/s (fc/2) */ + Br13560 = 7, + /* Bit Rate 13560 kbit/s (fc) */ + Br52p97 = 0xEB, + /* Bit Rate 52.97 kbit/s (fc/256) Fast Mode VICC->VCD */ + Br26p48 = 0xEC, + /* Bit Rate 26,48 kbit/s (fc/512) NFCV VICC->VCD & VCD->VICC 1of4 */ + Br1p66 = 0xED, + /* Bit Rate 1,66 kbit/s (fc/8192) NFCV VCD->VICC 1of256 */ + BrKeep = 0xFF, + /* Value indicating to keep the same previous bit rate */ +} + +/// Compliance modes for upper modules +#[repr(u8)] +#[derive(PartialEq, Clone, Copy, Debug)] +pub(crate) enum ComplianceMode { + /// Perform with NFC Forum 1.1 compliance + Nfc, + /// Perform with EMVCo compliance + EmvCo, + /// Perform with ISO10373 compliance + Iso, +} + +#[repr(u8)] +#[derive(Debug, Copy, Clone)] +pub(crate) enum WakeUpPeriod { + Period10ms = 0x00, + Period20ms = 0x01, + Period30ms = 0x02, + Period40ms = 0x03, + Period50ms = 0x04, + Period60ms = 0x05, + Period70ms = 0x06, + Period80ms = 0x07, + Period100ms = 0x10, + Period200ms = 0x11, + Period300ms = 0x12, + Period400ms = 0x13, + Period500ms = 0x14, + Period600ms = 0x15, + Period700ms = 0x16, + Period800ms = 0x17, +} + pub(crate) const FifoDepth: u32 = 96; pub(crate) const CmdLen: u32 = 1; pub(crate) const BufLen: u32 = CmdLen + FifoDepth; diff --git a/Software/fab-reader2/st25r3911b/src/device/iso_dep.rs b/Software/fab-reader2/st25r3911b/src/device/iso_dep.rs new file mode 100644 index 0000000..cf79603 --- /dev/null +++ b/Software/fab-reader2/st25r3911b/src/device/iso_dep.rs @@ -0,0 +1,3 @@ +struct IsoDep { + +} \ No newline at end of file diff --git a/Software/fab-reader2/st25r3911b/src/device/mod.rs b/Software/fab-reader2/st25r3911b/src/device/mod.rs new file mode 100644 index 0000000..2c8fa14 --- /dev/null +++ b/Software/fab-reader2/st25r3911b/src/device/mod.rs @@ -0,0 +1,94 @@ +use std::time::Duration; +use crate::{BitRate, NfcState}; +use crate::constants::ComplianceMode; +use crate::rf::{LmConfPA, LmConfPF}; + +// TODO: Implement NFC-B, NFC-F, NFC-V, ST25TB, AP2P +mod nfca; +mod iso_dep; + +/// NFCID1 +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct NfcId1 { + /// NFCID1 + pub nfcid1: [u8; 10], + /// Length of NFCID1 + pub len: u8, +} + + + +// TODO: Have th enum contain the device +#[derive(Debug, Copy, Clone, PartialEq)] +pub(crate) enum DeviceType { + ListenTypeNfcA = 0, /* NFC-A Listener device type */ + ListenTypeNfcB = 1, /* NFC-B Listener device type */ + ListenTypeNfcF = 2, /* NFC-F Listener device type */ + ListenTypeNfcV = 3, /* NFC-V Listener device type */ + ListenTypeST25TB = 4, /* ST25TB Listener device type */ + ListenTypeAp2p = 5, /* AP2P Listener device type */ + PollTypeNfcA = 10, /* NFC-A Poller device type */ + PollTypeNfcB = 11, /* NFC-B Poller device type */ + PollTypeNfcF = 12, /* NFC-F Poller device type */ + PollTypeNfcV = 13, /* NFC-V Poller device type */ + PollTypeAp2p = 15 /* AP2P Poller device type */ +} + +#[derive(Debug, Copy, Clone)] +pub(crate) enum RfInterface { + Rf = 0, /* RF Frame interface */ + IsoDep = 1, /* ISO-DEP interface */ + NfcDep = 2, /* NFC-DEP interface */ +} + +/// Device struct containing all its details +#[derive(Debug, Clone)] +pub(crate) struct Device { + /// Device type + pub device_type: DeviceType, // TODO: enum should wrap the device + /// NFCID1 + pub nfcid1: NfcId1, + /// RF interface + pub rf_interface: RfInterface, + // Protocol + // TODO: add enum for proto and implement isodep and nfcdep +} + +// TODO: Implement Wakeup Config + +/// Discovery Parameters + +#[derive(Debug, Copy, Clone)] +pub(crate) struct DiscoveryParams { + /// Compliance mode to be used + compliance_mode: ComplianceMode, + /// Number of Technologies to search for + techs_2_find: u16, + /// Duration of whole Poll + Listen Cycle + total_duration: Duration, + /// Max Number of devices + dev_limit: u8, + /// Bit rate to poll for NFC-F + poll_br: BitRate, + /// NFCID3 to be used on the ATR_REQ/ATR_RES + nfcid3: NfcId1, + /// General bytes to be used on the ATR-REQ + gb: [u8; 48], + /// Bit rate to poll for AP2P + ap2p_br: BitRate, + + /// Configuration for Passive Listen mode NFC-A + lm_conf_pa: LmConfPA, + /// Configuration for Passive Listen mode NFC-F + lm_conf_pf: LmConfPF, + + /// Callback to notify upper layer + notify_cb: fn(NfcState), + + /// Eanble Wake-Up mode before polling + wakeup_enable: bool, + /// Wake-Up mode default configuration + wakeup_cfg_default: bool, + /// Wake-Up mode configuration + wakeup_cfg: Wake +} diff --git a/Software/fab-reader2/st25r3911b/src/device/nfca.rs b/Software/fab-reader2/st25r3911b/src/device/nfca.rs new file mode 100644 index 0000000..1f5ca15 --- /dev/null +++ b/Software/fab-reader2/st25r3911b/src/device/nfca.rs @@ -0,0 +1,58 @@ +use super::NfcId1; + +/// NFC-A Listen device types +#[repr(u8)] +#[derive(Copy, Clone, Debug, PartialEq)] +enum ListenDeviceType { + T1T = 0x01, + T2T = 0x00, + T4T = 0x20, + NfcDep = 0x40, + T4tNfcDep = 0x60, +} + +/// SENS_RES (ATQA) format Digital 1.1 6.6.3 & Table 7 +#[derive(Copy, Clone, Debug, PartialEq)] +struct SensRes { + anti_collision_info: u8, + platform_info: u8, +} + +/// SDD_REQ (Anticollision) format Digital 1.1 6.7.1 & Table 11 +#[derive(Copy, Clone, Debug, PartialEq)] +struct SddReq { + sel_cmd: u8, + sel_par: u8, +} + +/// SDD_RES (UID CLn) format Digital 1.1 6.7.2 & Table 15 +#[derive(Copy, Clone, Debug, PartialEq)] +struct SddRes { + uid: NfcId1, + bcc: u8, +} + +/// SEL_REQ (Select) format Digital 1.1 6.8.1 & Table 17 +#[derive(Copy, Clone, Debug, PartialEq)] +struct SelReq { + sel_cmd: u8, + sel_par: u8, + uid: NfcId1, + bcc: u8, +} + +/// SEL_RES (SAK) format Digital 1.1 6.8.2 & Table 19 +#[derive(Copy, Clone, Debug, PartialEq)] +struct SelRes { + sak: u8, +} + +/// NFC-A listener device (PICC) struct +pub(crate) struct NFCAListenDevice { + device_type: ListenDeviceType, + sens_res: SensRes, + sel_res: SelRes, + nfcid1: NfcId1, + // FIXME: T1T not implemented + is_sleeping: bool, +} \ No newline at end of file diff --git a/Software/fab-reader2/st25r3911b/src/interrupts.rs b/Software/fab-reader2/st25r3911b/src/interrupts.rs index a58bc1d..616b41c 100644 --- a/Software/fab-reader2/st25r3911b/src/interrupts.rs +++ b/Software/fab-reader2/st25r3911b/src/interrupts.rs @@ -1,3 +1,6 @@ +use embedded_hal::digital::v2::InputPin; +use crate::{Interface, Register}; + #[repr(u32)] pub enum IRQMask { /* Main interrupt register. */ @@ -64,7 +67,19 @@ pub enum IRQMask { Err = 0x01, } -type InterruptCallback = fn(); +type InterruptCallback = fn(&mut Interrupt); + +const INT_REGS_LEN: u8 = Register::ErrorWakeUpInterruptStatus as u8 - Register::MainInterruptStatus as u8 + 1; +//FIXME: Finish this +pub(crate) fn default_callback(interrupt: &mut Interrupt, interface: &mut Interface, irq_pin: IRQ) { + let mut iregs: [u8; INT_REGS_LEN as usize] = interface.read_register_range(Register::MainInterruptStatus, INT_REGS_LEN).unwrap(); + while irq_pin.is_high() { + iregs = interface.read_multiple_registers(Register::MainInterruptStatus, INT_REGS_LEN).unwrap().into(); + } + + // FIXME: Protect IRQ status + interrupt.status = (iregs[0] as u32) | (iregs[1] as u32) << 8 | iregs[2] << 16 as u32; +} pub struct Interrupt { prevCallback: Option, diff --git a/Software/fab-reader2/st25r3911b/src/lib.rs b/Software/fab-reader2/st25r3911b/src/lib.rs index f6ade36..b137a40 100644 --- a/Software/fab-reader2/st25r3911b/src/lib.rs +++ b/Software/fab-reader2/st25r3911b/src/lib.rs @@ -8,11 +8,13 @@ use embedded_svc::timer::*; mod interface; mod interrupts; mod constants; -mod analogConfig; +mod analog_config; +mod device; +mod rf; use crate::interface::Interface; use crate::interrupts::{Interrupt, IRQMask}; -use crate::constants::{DirectCmd, ICIdentityBits, IOConfiguration2Bits, OperationControlBits, OscStableTimeout, Register, RegulatorControlBits, RegulatorControlMask}; +use crate::constants::{BitRate, DirectCmd, ICIdentityBits, IOConfiguration2Bits, NfcState, OperationControlBits, OscStableTimeout, Register, RegulatorControlBits, RegulatorControlMask}; /// Error #[derive(Debug)] @@ -29,10 +31,20 @@ impl From for Error { } } + +/// ST25R3911B driver struct ST25R3911B { + // Low level interface interface: Interface, interrupt: Interrupt, timer: TIMER, + // internal state + state: NfcState, + techs_found: u16, + techs_2_do: u16, + ap2p_bitrate: BitRate, + discovery_params: + } impl ST25R3911B @@ -47,6 +59,10 @@ impl ST25R3911BrzsYA6ZgXkxQ3l6N_@ot*gzV(nTrhqGA2ymhwlXjUpAL zVkxBCZc8q!Y)lifNhOUg(tW0y|FoCi&;E9I$W}A+JfC^Jyi7gMJm-Ah=QQV;Gv`7G z8BH|ECgMak5L;p+c)pITC0hjlG|8m@JnzNj3}f#i9$}SPllv3WPdeg@#QOGS=cNY? zB6vUm0uX=zZ3UjD#nSq5g0>}(z##wu2tWV=5TK(#W`Up02ttO-7$kamZk2Q1sKTHl z17d~%1ZX9|tT{#NPrYmKMo+8yj$k1G0SM4oARjG0jY}V)zpKDOADv4K!dy%0Jx#(B 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a/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/command.rs b/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/command.rs index 552ed43..d67edb8 100644 --- a/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/command.rs +++ b/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/command.rs @@ -36,4 +36,4 @@ impl traits::Command for Command { fn address(self) -> u8 { self as u8 } -} \ No newline at end of file +} diff --git a/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/graphics.rs b/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/graphics.rs index 7c03e5b..f9d723e 100644 --- a/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/graphics.rs +++ b/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/graphics.rs @@ -1,5 +1,5 @@ -use crate::E2266CS0Cx::{DEFAULT_BACKGROUND_COLOR, HEIGHT, WIDTH}; use crate::graphics::{Display, DisplayRotation}; +use crate::E2266CS0Cx::{DEFAULT_BACKGROUND_COLOR, HEIGHT, WIDTH}; use embedded_graphics_core::pixelcolor::BinaryColor; use embedded_graphics_core::prelude::*; @@ -27,8 +27,8 @@ impl DrawTarget for DisplayE2266CS0Cx { type Error = core::convert::Infallible; fn draw_iter(&mut self, pixels: I) -> Result<(), Self::Error> - where - I: IntoIterator>, + where + I: IntoIterator>, { for pixel in pixels { self.draw_helper(WIDTH, HEIGHT, pixel)?; @@ -59,4 +59,4 @@ impl Display for DisplayE2266CS0Cx { fn rotation(&self) -> DisplayRotation { self.rotation } -} \ No newline at end of file +} diff --git a/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/mod.rs b/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/mod.rs index 2fb3573..99f5096 100644 --- a/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/mod.rs +++ b/Software/fab-reader2/pervasive_epd/src/E2266CS0Cx/mod.rs @@ -8,12 +8,12 @@ pub const HEIGHT: u32 = 296; pub const DEFAULT_BACKGROUND_COLOR: Color = Color::White; const IS_BUSY_LOW: bool = true; -use std::io::repeat; +use crate::buffer_len; use embedded_hal::{ blocking::{delay::*, spi::Write}, digital::v2::*, }; -use crate::buffer_len; +use std::io::repeat; use command::Command; @@ -35,13 +35,13 @@ pub struct E2266CS0Cx { } impl E2266CS0Cx - where - SPI: Write, - CS: OutputPin, - BUSY: InputPin, - DC: OutputPin, - RST: OutputPin, - DELAY: DelayMs, +where + SPI: Write, + CS: OutputPin, + BUSY: InputPin, + DC: OutputPin, + RST: OutputPin, + DELAY: DelayMs, { fn init(&mut self, spi: &mut SPI, delay: &mut DELAY) -> Result<(), SPI::Error> { self.interface.reset(delay, 10); @@ -70,14 +70,14 @@ impl E2266CS0Cx } impl PervasiveDisplay -for E2266CS0Cx - where - SPI: Write, - CS: OutputPin, - BUSY: InputPin, - DC: OutputPin, - RST: OutputPin, - DELAY: DelayMs, + for E2266CS0Cx +where + SPI: Write, + CS: OutputPin, + BUSY: InputPin, + DC: OutputPin, + RST: OutputPin, + DELAY: DelayMs, { type DisplayColor = Color; fn width(&self) -> u32 { @@ -110,8 +110,7 @@ for E2266CS0Cx fn power_off(&mut self, spi: &mut SPI, _delay: &mut DELAY) -> Result<(), SPI::Error> { self.wait_until_idle(); - self.interface - .cmd(spi, Command::PowerOff)?; + self.interface.cmd(spi, Command::PowerOff)?; Ok(()) } @@ -134,10 +133,12 @@ for E2266CS0Cx .cmd_with_data(spi, Command::DataTransmission1, buffer)?; // Transmit WIDTH * HEIGHT bytes of 0x00 - self.interface - .cmd(spi, Command::DataTransmission2)?; - self.interface - .data_x_times(spi, 0x00, buffer_len(WIDTH as usize, HEIGHT as usize) as u32)?; + self.interface.cmd(spi, Command::DataTransmission2)?; + self.interface.data_x_times( + spi, + 0x00, + buffer_len(WIDTH as usize, HEIGHT as usize) as u32, + )?; Ok(()) } @@ -172,7 +173,11 @@ for E2266CS0Cx // clear the ram with the background color let color = self.background_color.get_byte_value(); - self.update_frame(spi, &[0x00; buffer_len(WIDTH as usize, HEIGHT as usize)], _delay)?; + self.update_frame( + spi, + &[0x00; buffer_len(WIDTH as usize, HEIGHT as usize)], + _delay, + )?; Ok(()) } @@ -190,15 +195,15 @@ for E2266CS0Cx } impl E2266CS0Cx - where - SPI: Write, - CS: OutputPin, - BUSY: InputPin, - DC: OutputPin, - RST: OutputPin, - DELAY: DelayMs, +where + SPI: Write, + CS: OutputPin, + BUSY: InputPin, + DC: OutputPin, + RST: OutputPin, + DELAY: DelayMs, { fn wait_until_idle(&mut self) { let _ = self.interface.wait_until_idle(IS_BUSY_LOW); } -} \ No newline at end of file +} diff --git a/Software/fab-reader2/pervasive_epd/src/color.rs b/Software/fab-reader2/pervasive_epd/src/color.rs index cf6cb26..34f0526 100644 --- a/Software/fab-reader2/pervasive_epd/src/color.rs +++ b/Software/fab-reader2/pervasive_epd/src/color.rs @@ -76,4 +76,4 @@ impl From for Color { fn from(value: u8) -> Self { Color::from_u8(value) } -} \ No newline at end of file +} diff --git a/Software/fab-reader2/pervasive_epd/src/graphics.rs b/Software/fab-reader2/pervasive_epd/src/graphics.rs index 269bad7..9eaabc3 100644 --- a/Software/fab-reader2/pervasive_epd/src/graphics.rs +++ b/Software/fab-reader2/pervasive_epd/src/graphics.rs @@ -24,7 +24,6 @@ impl Default for DisplayRotation { } } - /// Necessary traits for all displays to implement for drawing /// /// Adds support for: @@ -87,7 +86,6 @@ pub trait Display: DrawTarget { } } - /// A variable Display without a predefined buffer /// /// The buffer can be created as following: @@ -142,8 +140,8 @@ impl<'a> DrawTarget for VarDisplay<'a> { type Error = core::convert::Infallible; fn draw_iter(&mut self, pixels: I) -> Result<(), Self::Error> - where - I: IntoIterator>, + where + I: IntoIterator>, { for pixel in pixels { self.draw_helper(self.width, self.height, pixel)?; @@ -241,4 +239,4 @@ fn find_position(x: u32, y: u32, width: u32, height: u32, rotation: DisplayRotat nx / 8 + ((width + 7) / 8) * ny, 0x80 >> (nx % 8), ) -} \ No newline at end of file +} diff --git a/Software/fab-reader2/pervasive_epd/src/interface.rs b/Software/fab-reader2/pervasive_epd/src/interface.rs index 55e5351..6a15f9d 100644 --- a/Software/fab-reader2/pervasive_epd/src/interface.rs +++ b/Software/fab-reader2/pervasive_epd/src/interface.rs @@ -23,13 +23,13 @@ pub(crate) struct DisplayInterface { } impl DisplayInterface - where - SPI: Write, - CS: OutputPin, - BUSY: InputPin, - DC: OutputPin, - RST: OutputPin, - DELAY: DelayMs, +where + SPI: Write, + CS: OutputPin, + BUSY: InputPin, + DC: OutputPin, + RST: OutputPin, + DELAY: DelayMs, { pub fn new(cs: CS, busy: BUSY, dc: DC, rst: RST) -> Self { DisplayInterface { diff --git a/Software/fab-reader2/pervasive_epd/src/lib.rs b/Software/fab-reader2/pervasive_epd/src/lib.rs index a7f7879..1e4862c 100644 --- a/Software/fab-reader2/pervasive_epd/src/lib.rs +++ b/Software/fab-reader2/pervasive_epd/src/lib.rs @@ -1,7 +1,7 @@ -mod interface; -mod traits; pub mod color; pub mod graphics; +mod interface; +mod traits; pub mod E2266CS0Cx; @@ -14,7 +14,6 @@ pub mod prelude { pub use crate::graphics::{Display, DisplayRotation}; } - /// Computes the needed buffer length. Takes care of rounding up in case width /// is not divisible by 8. /// @@ -35,4 +34,4 @@ use embedded_hal::spi::{Mode, Phase, Polarity}; pub const SPI_MODE: Mode = Mode { phase: Phase::CaptureOnFirstTransition, polarity: Polarity::IdleLow, -}; \ No newline at end of file +}; diff --git a/Software/fab-reader2/pervasive_epd/src/traits.rs b/Software/fab-reader2/pervasive_epd/src/traits.rs index b509681..0799fc5 100644 --- a/Software/fab-reader2/pervasive_epd/src/traits.rs +++ b/Software/fab-reader2/pervasive_epd/src/traits.rs @@ -10,13 +10,13 @@ pub(crate) trait Command { } pub trait PervasiveDisplay - where - SPI: Write, - CS: OutputPin, - BUSY: InputPin, - DC: OutputPin, - RST: OutputPin, - DELAY: DelayMs, +where + SPI: Write, + CS: OutputPin, + BUSY: InputPin, + DC: OutputPin, + RST: OutputPin, + DELAY: DelayMs, { /// The Color Type used by the Display type DisplayColor; @@ -31,8 +31,8 @@ pub trait PervasiveDisplay rst: RST, delay: &mut DELAY, ) -> Result - where - Self: Sized; + where + Self: Sized; /// Let the device enter deep-sleep mode to save power. /// @@ -64,7 +64,6 @@ pub trait PervasiveDisplay delay: &mut DELAY, ) -> Result<(), SPI::Error>; - /// Displays the frame data from SRAM /// /// This function waits until the device isn`t busy anymore @@ -89,4 +88,4 @@ pub trait PervasiveDisplay /// but in the case you send data and commands directly you might need to check /// if the device is still busy fn is_busy(&self) -> bool; -} \ No newline at end of file +} diff --git a/Software/fab-reader2/rout.bin b/Software/fab-reader2/rout.bin new file mode 100644 index 0000000000000000000000000000000000000000..c33d30be3a36903cafe20be711f94a0863f24ae2 GIT binary patch literal 395712 zcmc$n3t(JTo&WDV@|a2b07^+|X>SX(DYVHXY11^6X3{*GNScH^DCISo&P$@Vt|MNTd-kCc|S^~t~ zX}|g1-+8~!@BGfW=l(Lsxg@s1>HoE+X&zwy9J;2}j2An!@~-cE$}$vMW@n~&jzzae zl0(sO?-X`oTp9VQdV`hgPUPG2^}k1-zcAk)1J{8& zLAX8N-wy5pPk@)eDA)k@gL}a-p#Q$W?Squ}w#O~5iJP}c*$>BulP;huSk{B#W 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