FabInfra-Mirror/fabhardware.FabReader2
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move analog constants

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This commit is contained in:
Kai Jan Kriegel 2022-09-24 05:11:30 +02:00
parent abd2ae5932
commit be5431a4cd
2 changed files with 34 additions and 31 deletions
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52
Software/fab-reader2/st25r3911b/src/analogConfig.rs
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@ -7,51 +7,51 @@ const fn MODE_ENTRY_1_REG(mode: u32, r0: u32, m0: u8, v0: u8) -> [u8; 7] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 1, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0] [(mode << 8) as u8, (mode & 0xFF) as u8, 1, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0]
} }
const fn MODE_ENTRY_2_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8) -> [u8; 9] { const fn MODE_ENTRY_2_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8) -> [u8; 11] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 2, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1] [(mode << 8) as u8, (mode & 0xFF) as u8, 2, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1]
} }
const fn MODE_ENTRY_3_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8) -> [u8; 11] { const fn MODE_ENTRY_3_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8) -> [u8; 15] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 3, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2] [(mode << 8) as u8, (mode & 0xFF) as u8, 3, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2]
} }
const fn MODE_ENTRY_4_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8) -> [u8; 13] { const fn MODE_ENTRY_4_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8) -> [u8; 19] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 4, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3] [(mode << 8) as u8, (mode & 0xFF) as u8, 4, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3]
} }
const fn MODE_ENTRY_5_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8) -> [u8; 15] { const fn MODE_ENTRY_5_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8) -> [u8; 23] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 5, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4] [(mode << 8) as u8, (mode & 0xFF) as u8, 5, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4]
} }
const fn MODE_ENTRY_6_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8) -> [u8; 17] { const fn MODE_ENTRY_6_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8) -> [u8; 27] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 6, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5] [(mode << 8) as u8, (mode & 0xFF) as u8, 6, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5]
} }
const fn MODE_ENTRY_7_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8) -> [u8; 19] { const fn MODE_ENTRY_7_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8) -> [u8; 31] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 7, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6] [(mode << 8) as u8, (mode & 0xFF) as u8, 7, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6]
} }
const fn MODE_ENTRY_8_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8) -> [u8; 21] { const fn MODE_ENTRY_8_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8) -> [u8; 35] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 8, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7] [(mode << 8) as u8, (mode & 0xFF) as u8, 8, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7]
} }
const fn MODE_ENTRY_9_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8) -> [u8; 23] { const fn MODE_ENTRY_9_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8) -> [u8; 39] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 9, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8] [(mode << 8) as u8, (mode & 0xFF) as u8, 9, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8]
} }
const fn MODE_ENTRY_10_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8) -> [u8; 25] { const fn MODE_ENTRY_10_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8) -> [u8; 43] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 10, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9] [(mode << 8) as u8, (mode & 0xFF) as u8, 10, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9]
} }
const fn MODE_ENTRY_11_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8) -> [u8; 27] { const fn MODE_ENTRY_11_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8) -> [u8; 47] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 11, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10] [(mode << 8) as u8, (mode & 0xFF) as u8, 11, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10]
} }
const fn MODE_ENTRY_12_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8, r11: u32, m11: u8, v11: u8) -> [u8; 29] { const fn MODE_ENTRY_12_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8, r11: u32, m11: u8, v11: u8) -> [u8; 51] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 12, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10, (r11 << 8) as u8, (r11 & 0xFF) as u8, m11, v11] [(mode << 8) as u8, (mode & 0xFF) as u8, 12, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10, (r11 << 8) as u8, (r11 & 0xFF) as u8, m11, v11]
} }
const fn MODE_ENTRY_13_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8, r11: u32, m11: u8, v11: u8, r12: u32, m12: u8, v12: u8) -> [u8; 31] { const fn MODE_ENTRY_13_REG(mode: u32, r0: u32, m0: u8, v0: u8, r1: u32, m1: u8, v1: u8, r2: u32, m2: u8, v2: u8, r3: u32, m3: u8, v3: u8, r4: u32, m4: u8, v4: u8, r5: u32, m5: u8, v5: u8, r6: u32, m6: u8, v6: u8, r7: u32, m7: u8, v7: u8, r8: u32, m8: u8, v8: u8, r9: u32, m9: u8, v9: u8, r10: u32, m10: u8, v10: u8, r11: u32, m11: u8, v11: u8, r12: u32, m12: u8, v12: u8) -> [u8; 55] {
[(mode << 8) as u8, (mode & 0xFF) as u8, 13, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10, (r11 << 8) as u8, (r11 & 0xFF) as u8, m11, v11, (r12 << 8) as u8, (r12 & 0xFF) as u8, m12, v12] [(mode << 8) as u8, (mode & 0xFF) as u8, 13, (r0 << 8) as u8, (r0 & 0xFF) as u8, m0, v0, (r1 << 8) as u8, (r1 & 0xFF) as u8, m1, v1, (r2 << 8) as u8, (r2 & 0xFF) as u8, m2, v2, (r3 << 8) as u8, (r3 & 0xFF) as u8, m3, v3, (r4 << 8) as u8, (r4 & 0xFF) as u8, m4, v4, (r5 << 8) as u8, (r5 & 0xFF) as u8, m5, v5, (r6 << 8) as u8, (r6 & 0xFF) as u8, m6, v6, (r7 << 8) as u8, (r7 & 0xFF) as u8, m7, v7, (r8 << 8) as u8, (r8 & 0xFF) as u8, m8, v8, (r9 << 8) as u8, (r9 & 0xFF) as u8, m9, v9, (r10 << 8) as u8, (r10 & 0xFF) as u8, m10, v10, (r11 << 8) as u8, (r11 & 0xFF) as u8, m11, v11, (r12 << 8) as u8, (r12 & 0xFF) as u8, m12, v12]
} }
@ -115,6 +115,18 @@ const ANALOG_CONFIG_CHIP_LISTEN_COMMON: u32 = 0x0009; /*!< Chip-Specific event:
const ANALOG_CONFIG_UPDATE_LAST: u32 = 0x00; /*!< Value indicating Last configuration set during update */ const ANALOG_CONFIG_UPDATE_LAST: u32 = 0x00; /*!< Value indicating Last configuration set during update */
const ANALOG_CONFIG_UPDATE_MORE: u32 = 0x01; /*!< Value indicating More configuration set coming during update */ const ANALOG_CONFIG_UPDATE_MORE: u32 = 0x01; /*!< Value indicating More configuration set coming during update */
const DEFAULT_ANALOG_CONFIG: Vec<u8> = MODE_ENTRY_10_REG(ANALOG_CONFIG_TECH_CHIP | ANALOG_CONFIG_CHIP_INIT,
Register::OperationControl as u32, 0x30, 0x10, //Default to AM
Register::IOConfiguration1 as u32, 0x06, 0x06, //MCUCLK: HF clk off
Register::IOConfiguration1 as u32, IOConfiguration1Bits::mask_out_cl as u8 | IOConfiguration1Bits::lf_clk_off as u8, 0x07, // MCUCLK: LF clk off
Register::IOConfiguration2 as u32, 0x18, 0x18, // pull downs
Register::ReceiverConfiguration4 as u32, ReceiverConfiguration4Mask::mask_rg2_pm as u8, 0x1 << ReceiverConfiguration4Mask::shift_rg2_pm as u8, //increase digitizer windows for PM
Register::AnntenaCalibrationTarget as u32, 0xFF, 0x80, // 90 deg,
Register::AnntenaCalibrationControl as u32, 0xF8, 0x00, // trim value from calibrate antenna
Register::AMModulationDepthControl as u32, AMModulationDepthControlConstans::am_s as u8, AMModulationDepthControlConstans::am_s as u8, // AM modulated level is defined by RFO AM Modulated Level Def Reg, fixed setting, no automatic adjustment
Register::ExternalFieldDetectorThreshold as u32, EXT_FIELD_DET_TRG_MASK, ExternalFieldDetectorThresholdTrgVoltage::trg_75mV as u8,
Register::ExternalFieldDetectorThreshold as u32, EXT_FIELD_DET_RFE_MASK, ExternalFieldDetectorThresholdRfeVoltage::rfe_75mV as u8
).into_iter().collect();
pub(crate) struct AnalogConfigMgmt { pub(crate) struct AnalogConfigMgmt {
config_tbl: Box<[u8]>, config_tbl: Box<[u8]>,
@ -124,21 +136,7 @@ pub(crate) struct AnalogConfigMgmt {
impl AnalogConfigMgmt { impl AnalogConfigMgmt {
pub fn new_default() -> Self { pub fn new_default() -> Self {
Self { Self {
config_tbl: vec![ config_tbl: DEFAULT_ANALOG_CONFIG.into_boxed_slice(),
//****** Default Analog Configuration for Chip-Specific Reset. ******/
MODE_ENTRY_10_REG(ANALOG_CONFIG_TECH_CHIP | ANALOG_CONFIG_CHIP_INIT,
Register::OperationControl, 0x30, 0x10, //Default to AM
Register::IOConfiguration1, 0x06, 0x06, //MCUCLK: HF clk off
Register::IOConfiguration1, IOConfiguration1Bits::mask_out_cl | IOConfiguration1Bits::lf_clk_off, 0x07, // MCUCLK: LF clk off
Register::IOConfiguration2, 0x18, 0x18, // pull downs
Register::ReceiverConfiguration4, ReceiverConfiguration4Bits::mask_rg2_pm, 0x1 << ReceiverConfiguration4Bits::shift_rg2_pm, //increase digitizer windows for PM
Register::AnntenaCalibrationTarget, 0xFF, 0x80, // 90 deg,
Register::AnntenaCalibrationControl, 0xF8, 0x00, // trim value from calibrate antenna
Register::AMModulationDepthControl, AMModulationDepthControlConstans::am_s, AMModulationDepthControlConstans::am_s, // AM modulated level is defined by RFO AM Modulated Level Def Reg, fixed setting, no automatic adjustment
Register::ExternalFieldDetectorThreshold, EXT_FIELD_DET_TRG_MASK, ExternalFieldDetectorThresholdTrgVoltage::trg_75mV,
Register::ExternalFieldDetectorThreshold, EXT_FIELD_DET_RFE_MASK, ExternalFieldDetectorThresholdRfeVoltage::rfe_75mV
)
].into_boxed_slice(),
ready: true, ready: true,
} }
} }

13
Software/fab-reader2/st25r3911b/src/constants.rs
View File

@ -218,15 +218,20 @@ pub enum IOConfiguration1FIFOLr {
#[repr(u8)] #[repr(u8)]
#[derive(PartialEq, Clone, Copy, Debug)] #[derive(PartialEq, Clone, Copy, Debug)]
pub enum ReceiverConfiguration4Bits { pub enum ReceiverConfiguration4Mask {
shift_rg2_pm = 0, shift_rg2_pm = 0,
mask_rg2_pm = 0xf < 0, mask_rg2_pm = 0xf << 0,
shift_rg2_am = 4,
mask_rg2_am = 0xf << 4,
}
#[repr(u8)]
#[derive(PartialEq, Clone, Copy, Debug)]
pub enum ReceiverConfiguration4Bits {
rg2_pm0 = 1 << 0, rg2_pm0 = 1 << 0,
rg2_pm1 = 1 << 1, rg2_pm1 = 1 << 1,
rg2_pm2 = 1 << 2, rg2_pm2 = 1 << 2,
rg2_pm3 = 1 << 3, rg2_pm3 = 1 << 3,
shift_rg2_am = 4,
mask_rg2_am = 0xf << 4,
rg2_am0 = 1 << 4, rg2_am0 = 1 << 4,
rg2_am1 = 1 << 5, rg2_am1 = 1 << 5,
rg2_am2 = 1 << 6, rg2_am2 = 1 << 6,