89 lines
4.6 KiB
C
89 lines
4.6 KiB
C
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#ifndef __FASTPIN_ARM_KL26_H
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#define __FASTPIN_ARM_KL26_H
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FASTLED_NAMESPACE_BEGIN
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#if defined(FASTLED_FORCE_SOFTWARE_PINS)
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#warning "Software pin support forced, pin access will be sloightly slower."
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#define NO_HARDWARE_PIN_SUPPORT
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#undef HAS_HARDWARE_PIN_SUPPORT
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#else
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/// Template definition for teensy LC style ARM pins, providing direct access to the various GPIO registers. Note that this
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/// uses the full port GPIO registers. In theory, in some way, bit-band register access -should- be faster, however I have found
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/// that something about the way gcc does register allocation results in the bit-band code being slower. It will need more fine tuning.
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/// The registers are data output, set output, clear output, toggle output, input, and direction
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template<uint8_t PIN, uint32_t _MASK, typename _PDOR, typename _PSOR, typename _PCOR, typename _PTOR, typename _PDIR, typename _PDDR> class _ARMPIN {
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public:
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typedef volatile uint32_t * port_ptr_t;
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typedef uint32_t port_t;
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inline static void setOutput() { pinMode(PIN, OUTPUT); } // TODO: perform MUX config { _PDDR::r() |= _MASK; }
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inline static void setInput() { pinMode(PIN, INPUT); } // TODO: preform MUX config { _PDDR::r() &= ~_MASK; }
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inline static void hi() __attribute__ ((always_inline)) { _PSOR::r() = _MASK; }
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inline static void lo() __attribute__ ((always_inline)) { _PCOR::r() = _MASK; }
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inline static void set(register port_t val) __attribute__ ((always_inline)) { _PDOR::r() = val; }
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inline static void strobe() __attribute__ ((always_inline)) { toggle(); toggle(); }
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inline static void toggle() __attribute__ ((always_inline)) { _PTOR::r() = _MASK; }
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inline static void hi(register port_ptr_t port) __attribute__ ((always_inline)) { hi(); }
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inline static void lo(register port_ptr_t port) __attribute__ ((always_inline)) { lo(); }
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inline static void fastset(register port_ptr_t port, register port_t val) __attribute__ ((always_inline)) { *port = val; }
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inline static port_t hival() __attribute__ ((always_inline)) { return _PDOR::r() | _MASK; }
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inline static port_t loval() __attribute__ ((always_inline)) { return _PDOR::r() & ~_MASK; }
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inline static port_ptr_t port() __attribute__ ((always_inline)) { return &_PDOR::r(); }
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inline static port_ptr_t sport() __attribute__ ((always_inline)) { return &_PSOR::r(); }
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inline static port_ptr_t cport() __attribute__ ((always_inline)) { return &_PCOR::r(); }
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inline static port_t mask() __attribute__ ((always_inline)) { return _MASK; }
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};
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// Macros for kl26 pin access/definition
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#define GPIO_BITBAND_ADDR(reg, bit) (((uint32_t)&(reg) - 0x40000000) * 32 + (bit) * 4 + 0x42000000)
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#define GPIO_BITBAND_PTR(reg, bit) ((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)))
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#define _R(T) struct __gen_struct_ ## T
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#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline reg32_t r() { return T; } \
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template<int BIT> static __attribute__((always_inline)) inline ptr_reg32_t rx() { return GPIO_BITBAND_PTR(T, BIT); } };
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#define _IO32(L) _RD32(FGPIO ## L ## _PDOR); _RD32(FGPIO ## L ## _PSOR); _RD32(FGPIO ## L ## _PCOR); _RD32(GPIO ## L ## _PTOR); _RD32(FGPIO ## L ## _PDIR); _RD32(FGPIO ## L ## _PDDR);
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#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, 1 << BIT, _R(FGPIO ## L ## _PDOR), _R(FGPIO ## L ## _PSOR), _R(FGPIO ## L ## _PCOR), \
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_R(GPIO ## L ## _PTOR), _R(FGPIO ## L ## _PDIR), _R(FGPIO ## L ## _PDDR)> {}; \
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/* template<> class FastPinBB<PIN> : public _ARMPIN_BITBAND<PIN, BIT, _R(GPIO ## L ## _PDOR), _R(GPIO ## L ## _PSOR), _R(GPIO ## L ## _PCOR), \
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_R(GPIO ## L ## _PTOR), _R(GPIO ## L ## _PDIR), _R(GPIO ## L ## _PDDR)> {}; */
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// Actual pin definitions
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#if defined(FASTLED_TEENSYLC) && defined(CORE_TEENSY)
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_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E);
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#define MAX_PIN 26
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_DEFPIN_ARM(0, 16, B); _DEFPIN_ARM(1, 17, B); _DEFPIN_ARM(2, 0, D); _DEFPIN_ARM(3, 1, A);
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_DEFPIN_ARM(4, 2, A); _DEFPIN_ARM(5, 7, D); _DEFPIN_ARM(6, 4, D); _DEFPIN_ARM(7, 2, D);
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_DEFPIN_ARM(8, 3, D); _DEFPIN_ARM(9, 3, C); _DEFPIN_ARM(10, 4, C); _DEFPIN_ARM(11, 6, C);
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_DEFPIN_ARM(12, 7, C); _DEFPIN_ARM(13, 5, C); _DEFPIN_ARM(14, 1, D); _DEFPIN_ARM(15, 0, C);
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_DEFPIN_ARM(16, 0, B); _DEFPIN_ARM(17, 1, B); _DEFPIN_ARM(18, 3, B); _DEFPIN_ARM(19, 2, B);
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_DEFPIN_ARM(20, 5, D); _DEFPIN_ARM(21, 6, D); _DEFPIN_ARM(22, 1, C); _DEFPIN_ARM(23, 2, C);
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_DEFPIN_ARM(24, 20, E); _DEFPIN_ARM(25, 21, E); _DEFPIN_ARM(26, 30, E);
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#define SPI_DATA 11
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#define SPI_CLOCK 13
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// #define SPI1 (*(SPI_t *)0x4002D000)
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#define SPI2_DATA 0
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#define SPI2_CLOCK 20
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#define HAS_HARDWARE_PIN_SUPPORT
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#endif
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#endif // FASTLED_FORCE_SOFTWARE_PINS
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FASTLED_NAMESPACE_END
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#endif // __INC_FASTPIN_ARM_K20
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