159 lines
5.3 KiB
C++
159 lines
5.3 KiB
C++
#ifndef __FASTPIN_ARM_STM32_H
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#define __FASTPIN_ARM_STM32_H
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FASTLED_NAMESPACE_BEGIN
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#if defined(FASTLED_FORCE_SOFTWARE_PINS)
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#warning "Software pin support forced, pin access will be sloightly slower."
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#define NO_HARDWARE_PIN_SUPPORT
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#undef HAS_HARDWARE_PIN_SUPPORT
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#else
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/// Template definition for STM32 style ARM pins, providing direct access to the various GPIO registers. Note that this
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/// uses the full port GPIO registers. In theory, in some way, bit-band register access -should- be faster, however I have found
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/// that something about the way gcc does register allocation results in the bit-band code being slower. It will need more fine tuning.
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/// The registers are data output, set output, clear output, toggle output, input, and direction
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template<uint8_t PIN, uint8_t _BIT, uint32_t _MASK, typename _GPIO> class _ARMPIN {
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public:
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typedef volatile uint32_t * port_ptr_t;
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typedef uint32_t port_t;
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#if 0
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inline static void setOutput() {
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if(_BIT<8) {
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_CRL::r() = (_CRL::r() & (0xF << (_BIT*4)) | (0x1 << (_BIT*4));
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} else {
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_CRH::r() = (_CRH::r() & (0xF << ((_BIT-8)*4))) | (0x1 << ((_BIT-8)*4));
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}
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}
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inline static void setInput() { /* TODO */ } // TODO: preform MUX config { _PDDR::r() &= ~_MASK; }
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#endif
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inline static void setOutput() { pinMode(PIN, OUTPUT); } // TODO: perform MUX config { _PDDR::r() |= _MASK; }
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inline static void setInput() { pinMode(PIN, INPUT); } // TODO: preform MUX config { _PDDR::r() &= ~_MASK; }
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inline static void hi() __attribute__ ((always_inline)) { _GPIO::r()->BSRR = _MASK; }
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inline static void lo() __attribute__ ((always_inline)) { _GPIO::r()->BRR = _MASK; }
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// inline static void lo() __attribute__ ((always_inline)) { _GPIO::r()->BSRR = (_MASK<<16); }
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inline static void set(register port_t val) __attribute__ ((always_inline)) { _GPIO::r()->ODR = val; }
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inline static void strobe() __attribute__ ((always_inline)) { toggle(); toggle(); }
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inline static void toggle() __attribute__ ((always_inline)) { if(_GPIO::r()->ODR & _MASK) { lo(); } else { hi(); } }
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inline static void hi(register port_ptr_t port) __attribute__ ((always_inline)) { hi(); }
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inline static void lo(register port_ptr_t port) __attribute__ ((always_inline)) { lo(); }
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inline static void fastset(register port_ptr_t port, register port_t val) __attribute__ ((always_inline)) { *port = val; }
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inline static port_t hival() __attribute__ ((always_inline)) { return _GPIO::r()->ODR | _MASK; }
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inline static port_t loval() __attribute__ ((always_inline)) { return _GPIO::r()->ODR & ~_MASK; }
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inline static port_ptr_t port() __attribute__ ((always_inline)) { return &_GPIO::r()->ODR; }
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inline static port_ptr_t sport() __attribute__ ((always_inline)) { return &_GPIO::r()->BSRR; }
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inline static port_ptr_t cport() __attribute__ ((always_inline)) { return &_GPIO::r()->BRR; }
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inline static port_t mask() __attribute__ ((always_inline)) { return _MASK; }
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};
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#if defined(STM32F10X_MD)
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#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline volatile GPIO_TypeDef * r() { return T; } };
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#define _IO32(L) _RD32(GPIO ## L)
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#elif defined(__STM32F1__)
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#define _RD32(T) struct __gen_struct_ ## T { static __attribute__((always_inline)) inline gpio_reg_map* r() { return T->regs; } };
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#define _IO32(L) _RD32(GPIO ## L)
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#else
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#error "Platform not supported"
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#endif
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#define _R(T) struct __gen_struct_ ## T
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#define _DEFPIN_ARM(PIN, BIT, L) template<> class FastPin<PIN> : public _ARMPIN<PIN, BIT, 1 << BIT, _R(GPIO ## L)> {};
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// Actual pin definitions
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#if defined(SPARK) // Sparkfun STM32F103 based board
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_IO32(A); _IO32(B); _IO32(C); _IO32(D); _IO32(E); _IO32(F); _IO32(G);
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#define MAX_PIN 19
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_DEFPIN_ARM(0, 7, B);
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_DEFPIN_ARM(1, 6, B);
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_DEFPIN_ARM(2, 5, B);
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_DEFPIN_ARM(3, 4, B);
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_DEFPIN_ARM(4, 3, B);
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_DEFPIN_ARM(5, 15, A);
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_DEFPIN_ARM(6, 14, A);
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_DEFPIN_ARM(7, 13, A);
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_DEFPIN_ARM(8, 8, A);
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_DEFPIN_ARM(9, 9, A);
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_DEFPIN_ARM(10, 0, A);
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_DEFPIN_ARM(11, 1, A);
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_DEFPIN_ARM(12, 4, A);
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_DEFPIN_ARM(13, 5, A);
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_DEFPIN_ARM(14, 6, A);
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_DEFPIN_ARM(15, 7, A);
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_DEFPIN_ARM(16, 0, B);
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_DEFPIN_ARM(17, 1, B);
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_DEFPIN_ARM(18, 3, A);
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_DEFPIN_ARM(19, 2, A);
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#define SPI_DATA 15
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#define SPI_CLOCK 13
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#define HAS_HARDWARE_PIN_SUPPORT
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#endif // SPARK
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#if defined(__STM32F1__) // Generic STM32F103 aka "Blue Pill"
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_IO32(A); _IO32(B); _IO32(C);
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#define MAX_PIN 46
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_DEFPIN_ARM(10, 0, A); // PA0 - PA7
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_DEFPIN_ARM(11, 1, A);
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_DEFPIN_ARM(12, 2, A);
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_DEFPIN_ARM(13, 3, A);
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_DEFPIN_ARM(14, 4, A);
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_DEFPIN_ARM(15, 5, A);
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_DEFPIN_ARM(16, 6, A);
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_DEFPIN_ARM(17, 7, A);
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_DEFPIN_ARM(29, 8, A); // PA8 - PA15
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_DEFPIN_ARM(30, 9, A);
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_DEFPIN_ARM(31, 10, A);
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_DEFPIN_ARM(32, 11, A);
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_DEFPIN_ARM(33, 12, A);
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_DEFPIN_ARM(34, 13, A);
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_DEFPIN_ARM(37, 14, A);
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_DEFPIN_ARM(38, 15, A);
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_DEFPIN_ARM(18, 0, B); // PB0 - PB11
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_DEFPIN_ARM(19, 1, B);
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_DEFPIN_ARM(20, 2, B);
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_DEFPIN_ARM(39, 3, B);
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_DEFPIN_ARM(40, 4, B);
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_DEFPIN_ARM(41, 5, B);
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_DEFPIN_ARM(42, 6, B);
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_DEFPIN_ARM(43, 7, B);
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_DEFPIN_ARM(45, 8, B);
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_DEFPIN_ARM(46, 9, B);
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_DEFPIN_ARM(21, 10, B);
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_DEFPIN_ARM(22, 11, B);
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_DEFPIN_ARM(2, 13, C); // PC13 - PC15
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_DEFPIN_ARM(3, 14, C);
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_DEFPIN_ARM(4, 15, C);
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#define SPI_DATA BOARD_SPI1_MOSI_PIN
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#define SPI_CLOCK BOARD_SPI1_SCK_PIN
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#define HAS_HARDWARE_PIN_SUPPORT
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#endif // __STM32F1__
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#endif // FASTLED_FORCE_SOFTWARE_PINS
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FASTLED_NAMESPACE_END
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#endif // __INC_FASTPIN_ARM_STM32
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