467 lines
16 KiB
C++
467 lines
16 KiB
C++
#ifndef __INC_FASTSPI_ARM_H
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#define __INC_FASTSPI_ARM_H
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FASTLED_NAMESPACE_BEGIN
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#if defined(FASTLED_TEENSY3) && defined(CORE_TEENSY)
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// Version 1.20 renamed SPI_t to KINETISK_SPI_t
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#if TEENSYDUINO >= 120
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#define SPI_t KINETISK_SPI_t
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#endif
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#ifndef KINETISK_SPI0
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#define KINETISK_SPI0 SPI0
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#endif
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#ifndef SPI_PUSHR_CONT
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#define SPI_PUSHR_CONT SPIX.PUSHR_CONT
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#define SPI_PUSHR_CTAS(X) SPIX.PUSHR_CTAS(X)
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#define SPI_PUSHR_EOQ SPIX.PUSHR_EOQ
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#define SPI_PUSHR_CTCNT SPIX.PUSHR_CTCNT
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#define SPI_PUSHR_PCS(X) SPIX.PUSHR_PCS(X)
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#endif
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// Template function that, on compilation, expands to a constant representing the highest bit set in a byte. Right now,
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// if no bits are set (value is 0), it returns 0, which is also the value returned if the lowest bit is the only bit
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// set (the zero-th bit). Unclear if I will want this to change at some point.
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template<int VAL, int BIT> class BitWork {
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public:
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static int highestBit() __attribute__((always_inline)) { return (VAL & 1 << BIT) ? BIT : BitWork<VAL, BIT-1>::highestBit(); }
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};
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template<int VAL> class BitWork<VAL, 0> {
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public:
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static int highestBit() __attribute__((always_inline)) { return 0; }
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};
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#define MAX(A, B) (( (A) > (B) ) ? (A) : (B))
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#define USE_CONT 0
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// intra-frame backup data
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struct SPIState {
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uint32_t _ctar0,_ctar1;
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uint32_t pins[4];
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};
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// extern SPIState gState;
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// Templated function to translate a clock divider value into the prescalar, scalar, and clock doubling setting for the world.
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template <int VAL> void getScalars(uint32_t & preScalar, uint32_t & scalar, uint32_t & dbl) {
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switch(VAL) {
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// Handle the dbl clock cases
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case 0: case 1:
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case 2: preScalar = 0; scalar = 0; dbl = 1; break;
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case 3: preScalar = 1; scalar = 0; dbl = 1; break;
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case 5: preScalar = 2; scalar = 0; dbl = 1; break;
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case 7: preScalar = 3; scalar = 0; dbl = 1; break;
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// Handle the scalar value 6 cases (since it's not a power of two, it won't get caught
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// below)
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case 9: preScalar = 1; scalar = 2; dbl = 1; break;
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case 18: case 19: preScalar = 1; scalar = 2; dbl = 0; break;
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case 15: preScalar = 2; scalar = 2; dbl = 1; break;
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case 30: case 31: preScalar = 2; scalar = 2; dbl = 0; break;
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case 21: case 22: case 23: preScalar = 3; scalar = 2; dbl = 1; break;
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case 42: case 43: case 44: case 45: case 46: case 47: preScalar = 3; scalar = 2; dbl = 0; break;
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default: {
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int p2 = BitWork<VAL/2, 15>::highestBit();
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int p3 = BitWork<VAL/3, 15>::highestBit();
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int p5 = BitWork<VAL/5, 15>::highestBit();
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int p7 = BitWork<VAL/7, 15>::highestBit();
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int w2 = 2 * (1 << p2);
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int w3 = (VAL/3) > 0 ? 3 * (1 << p3) : 0;
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int w5 = (VAL/5) > 0 ? 5 * (1 << p5) : 0;
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int w7 = (VAL/7) > 0 ? 7 * (1 << p7) : 0;
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int maxval = MAX(MAX(w2, w3), MAX(w5, w7));
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if(w2 == maxval) { preScalar = 0; scalar = p2; }
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else if(w3 == maxval) { preScalar = 1; scalar = p3; }
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else if(w5 == maxval) { preScalar = 2; scalar = p5; }
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else if(w7 == maxval) { preScalar = 3; scalar = p7; }
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dbl = 0;
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if(scalar == 0) { dbl = 1; }
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else if(scalar < 3) { scalar--; }
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}
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}
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return;
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}
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#define SPIX (*(SPI_t*)pSPIX)
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template <uint8_t _DATA_PIN, uint8_t _CLOCK_PIN, uint8_t _SPI_CLOCK_DIVIDER, uint32_t pSPIX>
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class ARMHardwareSPIOutput {
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Selectable *m_pSelect;
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SPIState gState;
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// Borrowed from the teensy3 SPSR emulation code -- note, enabling pin 7 disables pin 11 (and vice versa),
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// and likewise enabling pin 14 disables pin 13 (and vice versa)
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inline void enable_pins(void) __attribute__((always_inline)) {
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//serial_print("enable_pins\n");
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switch(_DATA_PIN) {
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case 7:
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CORE_PIN7_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
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CORE_PIN11_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
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break;
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case 11:
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CORE_PIN11_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
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CORE_PIN7_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
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break;
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}
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switch(_CLOCK_PIN) {
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case 13:
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CORE_PIN13_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
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CORE_PIN14_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
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break;
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case 14:
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CORE_PIN14_CONFIG = PORT_PCR_DSE | PORT_PCR_MUX(2);
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CORE_PIN13_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
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break;
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}
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}
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// Borrowed from the teensy3 SPSR emulation code. We disable the pins that we're using, and restore the state on the pins that we aren't using
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inline void disable_pins(void) __attribute__((always_inline)) {
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switch(_DATA_PIN) {
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case 7: CORE_PIN7_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); CORE_PIN11_CONFIG = gState.pins[1]; break;
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case 11: CORE_PIN11_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); CORE_PIN7_CONFIG = gState.pins[0]; break;
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}
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switch(_CLOCK_PIN) {
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case 13: CORE_PIN13_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); CORE_PIN14_CONFIG = gState.pins[3]; break;
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case 14: CORE_PIN14_CONFIG = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); CORE_PIN13_CONFIG = gState.pins[2]; break;
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}
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}
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static inline void update_ctars(uint32_t ctar0, uint32_t ctar1) __attribute__((always_inline)) {
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if(SPIX.CTAR0 == ctar0 && SPIX.CTAR1 == ctar1) return;
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uint32_t mcr = SPIX.MCR;
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if(mcr & SPI_MCR_MDIS) {
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SPIX.CTAR0 = ctar0;
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SPIX.CTAR1 = ctar1;
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} else {
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SPIX.MCR = mcr | SPI_MCR_MDIS | SPI_MCR_HALT;
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SPIX.CTAR0 = ctar0;
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SPIX.CTAR1 = ctar1;
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SPIX.MCR = mcr;
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}
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}
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static inline void update_ctar0(uint32_t ctar) __attribute__((always_inline)) {
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if (SPIX.CTAR0 == ctar) return;
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uint32_t mcr = SPIX.MCR;
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if (mcr & SPI_MCR_MDIS) {
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SPIX.CTAR0 = ctar;
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} else {
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SPIX.MCR = mcr | SPI_MCR_MDIS | SPI_MCR_HALT;
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SPIX.CTAR0 = ctar;
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SPIX.MCR = mcr;
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}
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}
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static inline void update_ctar1(uint32_t ctar) __attribute__((always_inline)) {
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if (SPIX.CTAR1 == ctar) return;
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uint32_t mcr = SPIX.MCR;
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if (mcr & SPI_MCR_MDIS) {
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SPIX.CTAR1 = ctar;
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} else {
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SPIX.MCR = mcr | SPI_MCR_MDIS | SPI_MCR_HALT;
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SPIX.CTAR1 = ctar;
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SPIX.MCR = mcr;
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}
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}
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void setSPIRate() {
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// Configure CTAR0, defaulting to 8 bits and CTAR1, defaulting to 16 bits
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uint32_t _PBR = 0;
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uint32_t _BR = 0;
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uint32_t _CSSCK = 0;
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uint32_t _DBR = 0;
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// if(_SPI_CLOCK_DIVIDER >= 256) { _PBR = 0; _BR = _CSSCK = 7; _DBR = 0; } // osc/256
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// else if(_SPI_CLOCK_DIVIDER >= 128) { _PBR = 0; _BR = _CSSCK = 6; _DBR = 0; } // osc/128
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// else if(_SPI_CLOCK_DIVIDER >= 64) { _PBR = 0; _BR = _CSSCK = 5; _DBR = 0; } // osc/64
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// else if(_SPI_CLOCK_DIVIDER >= 32) { _PBR = 0; _BR = _CSSCK = 4; _DBR = 0; } // osc/32
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// else if(_SPI_CLOCK_DIVIDER >= 16) { _PBR = 0; _BR = _CSSCK = 3; _DBR = 0; } // osc/16
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// else if(_SPI_CLOCK_DIVIDER >= 8) { _PBR = 0; _BR = _CSSCK = 1; _DBR = 0; } // osc/8
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// else if(_SPI_CLOCK_DIVIDER >= 7) { _PBR = 3; _BR = _CSSCK = 0; _DBR = 1; } // osc/7
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// else if(_SPI_CLOCK_DIVIDER >= 5) { _PBR = 2; _BR = _CSSCK = 0; _DBR = 1; } // osc/5
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// else if(_SPI_CLOCK_DIVIDER >= 4) { _PBR = 0; _BR = _CSSCK = 0; _DBR = 0; } // osc/4
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// else if(_SPI_CLOCK_DIVIDER >= 3) { _PBR = 1; _BR = _CSSCK = 0; _DBR = 1; } // osc/3
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// else { _PBR = 0; _BR = _CSSCK = 0; _DBR = 1; } // osc/2
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getScalars<_SPI_CLOCK_DIVIDER>(_PBR, _BR, _DBR);
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_CSSCK = _BR;
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uint32_t ctar0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(_PBR) | SPI_CTAR_BR(_BR) | SPI_CTAR_CSSCK(_CSSCK);
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uint32_t ctar1 = SPI_CTAR_FMSZ(15) | SPI_CTAR_PBR(_PBR) | SPI_CTAR_BR(_BR) | SPI_CTAR_CSSCK(_CSSCK);
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#if USE_CONT == 1
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ctar0 |= SPI_CTAR_CPHA | SPI_CTAR_CPOL;
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ctar1 |= SPI_CTAR_CPHA | SPI_CTAR_CPOL;
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#endif
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if(_DBR) {
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ctar0 |= SPI_CTAR_DBR;
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ctar1 |= SPI_CTAR_DBR;
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}
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update_ctars(ctar0,ctar1);
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}
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void inline save_spi_state() __attribute__ ((always_inline)) {
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// save ctar data
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gState._ctar0 = SPIX.CTAR0;
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gState._ctar1 = SPIX.CTAR1;
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// save data for the not-us pins
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gState.pins[0] = CORE_PIN7_CONFIG;
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gState.pins[1] = CORE_PIN11_CONFIG;
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gState.pins[2] = CORE_PIN13_CONFIG;
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gState.pins[3] = CORE_PIN14_CONFIG;
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}
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void inline restore_spi_state() __attribute__ ((always_inline)) {
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// restore ctar data
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update_ctars(gState._ctar0,gState._ctar1);
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// restore data for the not-us pins (not necessary because disable_pins will do this)
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// CORE_PIN7_CONFIG = gState.pins[0];
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// CORE_PIN11_CONFIG = gState.pins[1];
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// CORE_PIN13_CONFIG = gState.pins[2];
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// CORE_PIN14_CONFIG = gState.pins[3];
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}
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public:
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ARMHardwareSPIOutput() { m_pSelect = NULL; }
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ARMHardwareSPIOutput(Selectable *pSelect) { m_pSelect = pSelect; }
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void setSelect(Selectable *pSelect) { m_pSelect = pSelect; }
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void init() {
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// set the pins to output
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FastPin<_DATA_PIN>::setOutput();
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FastPin<_CLOCK_PIN>::setOutput();
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// Enable SPI0 clock
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uint32_t sim6 = SIM_SCGC6;
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if((SPI_t*)pSPIX == &KINETISK_SPI0) {
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if (!(sim6 & SIM_SCGC6_SPI0)) {
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//serial_print("init1\n");
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SIM_SCGC6 = sim6 | SIM_SCGC6_SPI0;
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SPIX.CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1);
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}
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} else if((SPI_t*)pSPIX == &SPI1) {
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if (!(sim6 & SIM_SCGC6_SPI1)) {
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//serial_print("init1\n");
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SIM_SCGC6 = sim6 | SIM_SCGC6_SPI1;
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SPIX.CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(1) | SPI_CTAR_BR(1);
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}
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}
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// Configure SPI as the master and enable
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SPIX.MCR |= SPI_MCR_MSTR; // | SPI_MCR_CONT_SCKE);
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SPIX.MCR &= ~(SPI_MCR_MDIS | SPI_MCR_HALT);
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// pin/spi configuration happens on select
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}
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static void waitFully() __attribute__((always_inline)) {
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// Wait for the last byte to get shifted into the register
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bool empty = false;
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do {
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cli();
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if ((SPIX.SR & 0xF000) > 0) {
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// reset the TCF flag
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SPIX.SR |= SPI_SR_TCF;
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} else {
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empty = true;
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}
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sei();
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} while (!empty);
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// wait for the TCF flag to get set
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while (!(SPIX.SR & SPI_SR_TCF));
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SPIX.SR |= (SPI_SR_TCF | SPI_SR_EOQF);
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}
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static bool needwait() __attribute__((always_inline)) { return (SPIX.SR & 0x4000); }
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static void wait() __attribute__((always_inline)) { while( (SPIX.SR & 0x4000) ); }
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static void wait1() __attribute__((always_inline)) { while( (SPIX.SR & 0xF000) >= 0x2000); }
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enum ECont { CONT, NOCONT };
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enum EWait { PRE, POST, NONE };
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enum ELast { NOTLAST, LAST };
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#if USE_CONT == 1
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#define CM CONT
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#else
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#define CM NOCONT
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#endif
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#define WM PRE
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template<ECont CONT_STATE, EWait WAIT_STATE, ELast LAST_STATE> class Write {
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public:
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static void writeWord(uint16_t w) __attribute__((always_inline)) {
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if(WAIT_STATE == PRE) { wait(); }
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cli();
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SPIX.PUSHR = ((LAST_STATE == LAST) ? SPI_PUSHR_EOQ : 0) |
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((CONT_STATE == CONT) ? SPI_PUSHR_CONT : 0) |
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SPI_PUSHR_CTAS(1) | (w & 0xFFFF);
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SPIX.SR |= SPI_SR_TCF;
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sei();
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if(WAIT_STATE == POST) { wait(); }
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}
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static void writeByte(uint8_t b) __attribute__((always_inline)) {
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if(WAIT_STATE == PRE) { wait(); }
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cli();
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SPIX.PUSHR = ((LAST_STATE == LAST) ? SPI_PUSHR_EOQ : 0) |
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((CONT_STATE == CONT) ? SPI_PUSHR_CONT : 0) |
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SPI_PUSHR_CTAS(0) | (b & 0xFF);
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SPIX.SR |= SPI_SR_TCF;
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sei();
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if(WAIT_STATE == POST) { wait(); }
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}
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};
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static void writeWord(uint16_t w) __attribute__((always_inline)) { wait(); cli(); SPIX.PUSHR = SPI_PUSHR_CTAS(1) | (w & 0xFFFF); SPIX.SR |= SPI_SR_TCF; sei(); }
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static void writeWordNoWait(uint16_t w) __attribute__((always_inline)) { cli(); SPIX.PUSHR = SPI_PUSHR_CTAS(1) | (w & 0xFFFF); SPIX.SR |= SPI_SR_TCF; sei(); }
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static void writeByte(uint8_t b) __attribute__((always_inline)) { wait(); cli(); SPIX.PUSHR = SPI_PUSHR_CTAS(0) | (b & 0xFF); SPIX.SR |= SPI_SR_TCF; sei(); }
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static void writeBytePostWait(uint8_t b) __attribute__((always_inline)) { cli(); SPIX.PUSHR = SPI_PUSHR_CTAS(0) | (b & 0xFF);SPIX.SR |= SPI_SR_TCF; sei(); wait(); }
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static void writeByteNoWait(uint8_t b) __attribute__((always_inline)) { cli(); SPIX.PUSHR = SPI_PUSHR_CTAS(0) | (b & 0xFF); SPIX.SR |= SPI_SR_TCF; sei(); }
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static void writeWordCont(uint16_t w) __attribute__((always_inline)) { wait(); cli(); SPIX.PUSHR = SPI_PUSHR_CONT | SPI_PUSHR_CTAS(1) | (w & 0xFFFF); SPIX.SR |= SPI_SR_TCF; sei(); }
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static void writeWordContNoWait(uint16_t w) __attribute__((always_inline)) { cli(); SPIX.PUSHR = SPI_PUSHR_CONT | SPI_PUSHR_CTAS(1) | (w & 0xFFFF); SPIX.SR |= SPI_SR_TCF; sei();}
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static void writeByteCont(uint8_t b) __attribute__((always_inline)) { wait(); cli(); SPIX.PUSHR = SPI_PUSHR_CONT | SPI_PUSHR_CTAS(0) | (b & 0xFF); SPIX.SR |= SPI_SR_TCF; sei(); }
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static void writeByteContPostWait(uint8_t b) __attribute__((always_inline)) { cli(); SPIX.PUSHR = SPI_PUSHR_CONT | SPI_PUSHR_CTAS(0) | (b & 0xFF); SPIX.SR |= SPI_SR_TCF; sei(); wait(); }
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static void writeByteContNoWait(uint8_t b) __attribute__((always_inline)) { cli(); SPIX.PUSHR = SPI_PUSHR_CONT | SPI_PUSHR_CTAS(0) | (b & 0xFF); SPIX.SR |= SPI_SR_TCF; sei(); }
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// not the most efficient mechanism in the world - but should be enough for sm16716 and friends
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template <uint8_t BIT> inline static void writeBit(uint8_t b) {
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uint32_t ctar1_save = SPIX.CTAR1;
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// Clear out the FMSZ bits, reset them for 1 bit transferd for the start bit
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uint32_t ctar1 = (ctar1_save & (~SPI_CTAR_FMSZ(15))) | SPI_CTAR_FMSZ(0);
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update_ctar1(ctar1);
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writeWord( (b & (1 << BIT)) != 0);
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update_ctar1(ctar1_save);
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}
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void inline select() __attribute__((always_inline)) {
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save_spi_state();
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if(m_pSelect != NULL) { m_pSelect->select(); }
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setSPIRate();
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enable_pins();
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}
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void inline release() __attribute__((always_inline)) {
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disable_pins();
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if(m_pSelect != NULL) { m_pSelect->release(); }
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restore_spi_state();
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}
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static void writeBytesValueRaw(uint8_t value, int len) {
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while(len--) { Write<CM, WM, NOTLAST>::writeByte(value); }
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}
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void writeBytesValue(uint8_t value, int len) {
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select();
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while(len--) {
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writeByte(value);
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}
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waitFully();
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release();
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}
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// Write a block of n uint8_ts out
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template <class D> void writeBytes(register uint8_t *data, int len) {
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uint8_t *end = data + len;
|
|
select();
|
|
// could be optimized to write 16bit words out instead of 8bit bytes
|
|
while(data != end) {
|
|
writeByte(D::adjust(*data++));
|
|
}
|
|
D::postBlock(len);
|
|
waitFully();
|
|
release();
|
|
}
|
|
|
|
void writeBytes(register uint8_t *data, int len) { writeBytes<DATA_NOP>(data, len); }
|
|
|
|
// write a block of uint8_ts out in groups of three. len is the total number of uint8_ts to write out. The template
|
|
// parameters indicate how many uint8_ts to skip at the beginning and/or end of each grouping
|
|
template <uint8_t FLAGS, class D, EOrder RGB_ORDER> void writePixels(PixelController<RGB_ORDER> pixels) {
|
|
select();
|
|
int len = pixels.mLen;
|
|
|
|
// Setup the pixel controller
|
|
if((FLAGS & FLAG_START_BIT) == 0) {
|
|
//If no start bit stupiditiy, write out as many 16-bit blocks as we can
|
|
while(pixels.has(2)) {
|
|
// Load and write out the first two bytes
|
|
if(WM == NONE) { wait1(); }
|
|
Write<CM, WM, NOTLAST>::writeWord(D::adjust(pixels.loadAndScale0()) << 8 | D::adjust(pixels.loadAndScale1()));
|
|
|
|
// Load and write out the next two bytes (step dithering, advance data in between since we
|
|
// cross pixels here)
|
|
Write<CM, WM, NOTLAST>::writeWord(D::adjust(pixels.loadAndScale2()) << 8 | D::adjust(pixels.stepAdvanceAndLoadAndScale0()));
|
|
|
|
// Load and write out the next two bytes
|
|
Write<CM, WM, NOTLAST>::writeWord(D::adjust(pixels.loadAndScale1()) << 8 | D::adjust(pixels.loadAndScale2()));
|
|
pixels.stepDithering();
|
|
pixels.advanceData();
|
|
}
|
|
|
|
if(pixels.has(1)) {
|
|
if(WM == NONE) { wait1(); }
|
|
// write out the rest as alternating 16/8-bit blocks (likely to be just one)
|
|
Write<CM, WM, NOTLAST>::writeWord(D::adjust(pixels.loadAndScale0()) << 8 | D::adjust(pixels.loadAndScale1()));
|
|
Write<CM, WM, NOTLAST>::writeByte(D::adjust(pixels.loadAndScale2()));
|
|
}
|
|
|
|
D::postBlock(len);
|
|
waitFully();
|
|
} else if(FLAGS & FLAG_START_BIT) {
|
|
uint32_t ctar1_save = SPIX.CTAR1;
|
|
|
|
// Clear out the FMSZ bits, reset them for 9 bits transferd for the start bit
|
|
uint32_t ctar1 = (ctar1_save & (~SPI_CTAR_FMSZ(15))) | SPI_CTAR_FMSZ(8);
|
|
update_ctar1(ctar1);
|
|
|
|
while(pixels.has(1)) {
|
|
writeWord( 0x100 | D::adjust(pixels.loadAndScale0()));
|
|
writeByte(D::adjust(pixels.loadAndScale1()));
|
|
writeByte(D::adjust(pixels.loadAndScale2()));
|
|
pixels.advanceData();
|
|
pixels.stepDithering();
|
|
}
|
|
D::postBlock(len);
|
|
waitFully();
|
|
|
|
// restore ctar1
|
|
update_ctar1(ctar1_save);
|
|
}
|
|
release();
|
|
}
|
|
};
|
|
#endif
|
|
|
|
FASTLED_NAMESPACE_END
|
|
|
|
#endif
|